dpll44xx.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * OMAP4-specific DPLL control functions
  4. *
  5. * Copyright (C) 2011 Texas Instruments, Inc.
  6. * Rajendra Nayak
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/errno.h>
  10. #include <linux/clk.h>
  11. #include <linux/io.h>
  12. #include <linux/bitops.h>
  13. #include <linux/clk/ti.h>
  14. #include "clock.h"
  15. /*
  16. * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
  17. * can supported when using the DPLL low-power mode. Frequencies are
  18. * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control,
  19. * Status, and Low-Power Operation Mode".
  20. */
  21. #define OMAP4_DPLL_LP_FINT_MAX 1000000
  22. #define OMAP4_DPLL_LP_FOUT_MAX 100000000
  23. /*
  24. * Bitfield declarations
  25. */
  26. #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BIT(8)
  27. #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BIT(10)
  28. #define OMAP4430_DPLL_REGM4XEN_MASK BIT(11)
  29. /* Static rate multiplier for OMAP4 REGM4XEN clocks */
  30. #define OMAP4430_REGM4XEN_MULT 4
  31. static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
  32. {
  33. u32 v;
  34. u32 mask;
  35. if (!clk)
  36. return;
  37. mask = clk->flags & CLOCK_CLKOUTX2 ?
  38. OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
  39. OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
  40. v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
  41. /* Clear the bit to allow gatectrl */
  42. v &= ~mask;
  43. ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
  44. }
  45. static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
  46. {
  47. u32 v;
  48. u32 mask;
  49. if (!clk)
  50. return;
  51. mask = clk->flags & CLOCK_CLKOUTX2 ?
  52. OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
  53. OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
  54. v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
  55. /* Set the bit to deny gatectrl */
  56. v |= mask;
  57. ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
  58. }
  59. const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
  60. .allow_idle = omap4_dpllmx_allow_gatectrl,
  61. .deny_idle = omap4_dpllmx_deny_gatectrl,
  62. };
  63. /**
  64. * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
  65. * @dd: pointer to the dpll data structure
  66. *
  67. * Calculates if low-power mode can be enabled based upon the last
  68. * multiplier and divider values calculated. If low-power mode can be
  69. * enabled, then the bit to enable low-power mode is stored in the
  70. * last_rounded_lpmode variable. This implementation is based upon the
  71. * criteria for enabling low-power mode as described in the OMAP4430/60
  72. * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
  73. * Operation Mode".
  74. */
  75. static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
  76. {
  77. long fint, fout;
  78. fint = clk_hw_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
  79. fout = fint * dd->last_rounded_m;
  80. if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
  81. dd->last_rounded_lpmode = 1;
  82. else
  83. dd->last_rounded_lpmode = 0;
  84. }
  85. /**
  86. * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
  87. * @clk: struct clk * of the DPLL to compute the rate for
  88. *
  89. * Compute the output rate for the OMAP4 DPLL represented by @clk.
  90. * Takes the REGM4XEN bit into consideration, which is needed for the
  91. * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
  92. * upon success, or 0 upon error.
  93. */
  94. unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
  95. unsigned long parent_rate)
  96. {
  97. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  98. u32 v;
  99. unsigned long rate;
  100. struct dpll_data *dd;
  101. if (!clk || !clk->dpll_data)
  102. return 0;
  103. dd = clk->dpll_data;
  104. rate = omap2_get_dpll_rate(clk);
  105. /* regm4xen adds a multiplier of 4 to DPLL calculations */
  106. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  107. if (v & OMAP4430_DPLL_REGM4XEN_MASK)
  108. rate *= OMAP4430_REGM4XEN_MULT;
  109. return rate;
  110. }
  111. /**
  112. * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
  113. * @clk: struct clk * of the DPLL to round a rate for
  114. * @target_rate: the desired rate of the DPLL
  115. *
  116. * Compute the rate that would be programmed into the DPLL hardware
  117. * for @clk if set_rate() were to be provided with the rate
  118. * @target_rate. Takes the REGM4XEN bit into consideration, which is
  119. * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
  120. * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
  121. * ~0 if an error occurred in omap2_dpll_round_rate().
  122. */
  123. long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
  124. unsigned long target_rate,
  125. unsigned long *parent_rate)
  126. {
  127. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  128. struct dpll_data *dd;
  129. long r;
  130. if (!clk || !clk->dpll_data)
  131. return -EINVAL;
  132. dd = clk->dpll_data;
  133. dd->last_rounded_m4xen = 0;
  134. /*
  135. * First try to compute the DPLL configuration for
  136. * target rate without using the 4X multiplier.
  137. */
  138. r = omap2_dpll_round_rate(hw, target_rate, NULL);
  139. if (r != ~0)
  140. goto out;
  141. /*
  142. * If we did not find a valid DPLL configuration, try again, but
  143. * this time see if using the 4X multiplier can help. Enabling the
  144. * 4X multiplier is equivalent to dividing the target rate by 4.
  145. */
  146. r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
  147. NULL);
  148. if (r == ~0)
  149. return r;
  150. dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
  151. dd->last_rounded_m4xen = 1;
  152. out:
  153. omap4_dpll_lpmode_recalc(dd);
  154. return dd->last_rounded_rate;
  155. }
  156. /**
  157. * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
  158. * @hw: pointer to the clock to determine rate for
  159. * @req: target rate request
  160. *
  161. * Determines which DPLL mode to use for reaching a desired rate.
  162. * Checks whether the DPLL shall be in bypass or locked mode, and if
  163. * locked, calculates the M,N values for the DPLL via round-rate.
  164. * Returns 0 on success and a negative error value otherwise.
  165. */
  166. int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
  167. struct clk_rate_request *req)
  168. {
  169. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  170. struct dpll_data *dd;
  171. if (!req->rate)
  172. return -EINVAL;
  173. dd = clk->dpll_data;
  174. if (!dd)
  175. return -EINVAL;
  176. if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
  177. (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
  178. req->best_parent_hw = dd->clk_bypass;
  179. } else {
  180. req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate,
  181. &req->best_parent_rate);
  182. req->best_parent_hw = dd->clk_ref;
  183. }
  184. req->best_parent_rate = req->rate;
  185. return 0;
  186. }