dpll.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693
  1. /*
  2. * OMAP DPLL clock support
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc.
  5. *
  6. * Tero Kristo <t-kristo@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/clk.h>
  18. #include <linux/clk-provider.h>
  19. #include <linux/slab.h>
  20. #include <linux/err.h>
  21. #include <linux/of.h>
  22. #include <linux/of_address.h>
  23. #include <linux/clk/ti.h>
  24. #include "clock.h"
  25. #undef pr_fmt
  26. #define pr_fmt(fmt) "%s: " fmt, __func__
  27. #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
  28. defined(CONFIG_SOC_DRA7XX)
  29. static const struct clk_ops dpll_m4xen_ck_ops = {
  30. .enable = &omap3_noncore_dpll_enable,
  31. .disable = &omap3_noncore_dpll_disable,
  32. .recalc_rate = &omap4_dpll_regm4xen_recalc,
  33. .round_rate = &omap4_dpll_regm4xen_round_rate,
  34. .set_rate = &omap3_noncore_dpll_set_rate,
  35. .set_parent = &omap3_noncore_dpll_set_parent,
  36. .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
  37. .determine_rate = &omap4_dpll_regm4xen_determine_rate,
  38. .get_parent = &omap2_init_dpll_parent,
  39. .save_context = &omap3_core_dpll_save_context,
  40. .restore_context = &omap3_core_dpll_restore_context,
  41. };
  42. #else
  43. static const struct clk_ops dpll_m4xen_ck_ops = {};
  44. #endif
  45. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
  46. defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
  47. defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
  48. static const struct clk_ops dpll_core_ck_ops = {
  49. .recalc_rate = &omap3_dpll_recalc,
  50. .get_parent = &omap2_init_dpll_parent,
  51. };
  52. static const struct clk_ops dpll_ck_ops = {
  53. .enable = &omap3_noncore_dpll_enable,
  54. .disable = &omap3_noncore_dpll_disable,
  55. .recalc_rate = &omap3_dpll_recalc,
  56. .round_rate = &omap2_dpll_round_rate,
  57. .set_rate = &omap3_noncore_dpll_set_rate,
  58. .set_parent = &omap3_noncore_dpll_set_parent,
  59. .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
  60. .determine_rate = &omap3_noncore_dpll_determine_rate,
  61. .get_parent = &omap2_init_dpll_parent,
  62. .save_context = &omap3_noncore_dpll_save_context,
  63. .restore_context = &omap3_noncore_dpll_restore_context,
  64. };
  65. static const struct clk_ops dpll_no_gate_ck_ops = {
  66. .recalc_rate = &omap3_dpll_recalc,
  67. .get_parent = &omap2_init_dpll_parent,
  68. .round_rate = &omap2_dpll_round_rate,
  69. .set_rate = &omap3_noncore_dpll_set_rate,
  70. .set_parent = &omap3_noncore_dpll_set_parent,
  71. .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
  72. .determine_rate = &omap3_noncore_dpll_determine_rate,
  73. .save_context = &omap3_noncore_dpll_save_context,
  74. .restore_context = &omap3_noncore_dpll_restore_context
  75. };
  76. #else
  77. static const struct clk_ops dpll_core_ck_ops = {};
  78. static const struct clk_ops dpll_ck_ops = {};
  79. static const struct clk_ops dpll_no_gate_ck_ops = {};
  80. const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
  81. #endif
  82. #ifdef CONFIG_ARCH_OMAP2
  83. static const struct clk_ops omap2_dpll_core_ck_ops = {
  84. .get_parent = &omap2_init_dpll_parent,
  85. .recalc_rate = &omap2_dpllcore_recalc,
  86. .round_rate = &omap2_dpll_round_rate,
  87. .set_rate = &omap2_reprogram_dpllcore,
  88. };
  89. #else
  90. static const struct clk_ops omap2_dpll_core_ck_ops = {};
  91. #endif
  92. #ifdef CONFIG_ARCH_OMAP3
  93. static const struct clk_ops omap3_dpll_core_ck_ops = {
  94. .get_parent = &omap2_init_dpll_parent,
  95. .recalc_rate = &omap3_dpll_recalc,
  96. .round_rate = &omap2_dpll_round_rate,
  97. };
  98. #else
  99. static const struct clk_ops omap3_dpll_core_ck_ops = {};
  100. #endif
  101. #ifdef CONFIG_ARCH_OMAP3
  102. static const struct clk_ops omap3_dpll_ck_ops = {
  103. .enable = &omap3_noncore_dpll_enable,
  104. .disable = &omap3_noncore_dpll_disable,
  105. .get_parent = &omap2_init_dpll_parent,
  106. .recalc_rate = &omap3_dpll_recalc,
  107. .set_rate = &omap3_noncore_dpll_set_rate,
  108. .set_parent = &omap3_noncore_dpll_set_parent,
  109. .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
  110. .determine_rate = &omap3_noncore_dpll_determine_rate,
  111. .round_rate = &omap2_dpll_round_rate,
  112. };
  113. static const struct clk_ops omap3_dpll5_ck_ops = {
  114. .enable = &omap3_noncore_dpll_enable,
  115. .disable = &omap3_noncore_dpll_disable,
  116. .get_parent = &omap2_init_dpll_parent,
  117. .recalc_rate = &omap3_dpll_recalc,
  118. .set_rate = &omap3_dpll5_set_rate,
  119. .set_parent = &omap3_noncore_dpll_set_parent,
  120. .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
  121. .determine_rate = &omap3_noncore_dpll_determine_rate,
  122. .round_rate = &omap2_dpll_round_rate,
  123. };
  124. static const struct clk_ops omap3_dpll_per_ck_ops = {
  125. .enable = &omap3_noncore_dpll_enable,
  126. .disable = &omap3_noncore_dpll_disable,
  127. .get_parent = &omap2_init_dpll_parent,
  128. .recalc_rate = &omap3_dpll_recalc,
  129. .set_rate = &omap3_dpll4_set_rate,
  130. .set_parent = &omap3_noncore_dpll_set_parent,
  131. .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
  132. .determine_rate = &omap3_noncore_dpll_determine_rate,
  133. .round_rate = &omap2_dpll_round_rate,
  134. };
  135. #endif
  136. static const struct clk_ops dpll_x2_ck_ops = {
  137. .recalc_rate = &omap3_clkoutx2_recalc,
  138. };
  139. /**
  140. * _register_dpll - low level registration of a DPLL clock
  141. * @hw: hardware clock definition for the clock
  142. * @node: device node for the clock
  143. *
  144. * Finalizes DPLL registration process. In case a failure (clk-ref or
  145. * clk-bypass is missing), the clock is added to retry list and
  146. * the initialization is retried on later stage.
  147. */
  148. static void __init _register_dpll(void *user,
  149. struct device_node *node)
  150. {
  151. struct clk_hw *hw = user;
  152. struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
  153. struct dpll_data *dd = clk_hw->dpll_data;
  154. struct clk *clk;
  155. const struct clk_init_data *init = hw->init;
  156. clk = of_clk_get(node, 0);
  157. if (IS_ERR(clk)) {
  158. pr_debug("clk-ref missing for %pOFn, retry later\n",
  159. node);
  160. if (!ti_clk_retry_init(node, hw, _register_dpll))
  161. return;
  162. goto cleanup;
  163. }
  164. dd->clk_ref = __clk_get_hw(clk);
  165. clk = of_clk_get(node, 1);
  166. if (IS_ERR(clk)) {
  167. pr_debug("clk-bypass missing for %pOFn, retry later\n",
  168. node);
  169. if (!ti_clk_retry_init(node, hw, _register_dpll))
  170. return;
  171. goto cleanup;
  172. }
  173. dd->clk_bypass = __clk_get_hw(clk);
  174. /* register the clock */
  175. clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);
  176. if (!IS_ERR(clk)) {
  177. of_clk_add_provider(node, of_clk_src_simple_get, clk);
  178. kfree(init->parent_names);
  179. kfree(init);
  180. return;
  181. }
  182. cleanup:
  183. kfree(clk_hw->dpll_data);
  184. kfree(init->parent_names);
  185. kfree(init);
  186. kfree(clk_hw);
  187. }
  188. #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
  189. defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
  190. defined(CONFIG_SOC_AM43XX)
  191. /**
  192. * _register_dpll_x2 - Registers a DPLLx2 clock
  193. * @node: device node for this clock
  194. * @ops: clk_ops for this clock
  195. * @hw_ops: clk_hw_ops for this clock
  196. *
  197. * Initializes a DPLL x 2 clock from device tree data.
  198. */
  199. static void _register_dpll_x2(struct device_node *node,
  200. const struct clk_ops *ops,
  201. const struct clk_hw_omap_ops *hw_ops)
  202. {
  203. struct clk *clk;
  204. struct clk_init_data init = { NULL };
  205. struct clk_hw_omap *clk_hw;
  206. const char *name = node->name;
  207. const char *parent_name;
  208. parent_name = of_clk_get_parent_name(node, 0);
  209. if (!parent_name) {
  210. pr_err("%pOFn must have parent\n", node);
  211. return;
  212. }
  213. clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
  214. if (!clk_hw)
  215. return;
  216. clk_hw->ops = hw_ops;
  217. clk_hw->hw.init = &init;
  218. init.name = name;
  219. init.ops = ops;
  220. init.parent_names = &parent_name;
  221. init.num_parents = 1;
  222. #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
  223. defined(CONFIG_SOC_DRA7XX)
  224. if (hw_ops == &clkhwops_omap4_dpllmx) {
  225. int ret;
  226. /* Check if register defined, if not, drop hw-ops */
  227. ret = of_property_count_elems_of_size(node, "reg", 1);
  228. if (ret <= 0) {
  229. clk_hw->ops = NULL;
  230. } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {
  231. kfree(clk_hw);
  232. return;
  233. }
  234. }
  235. #endif
  236. /* register the clock */
  237. clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
  238. if (IS_ERR(clk))
  239. kfree(clk_hw);
  240. else
  241. of_clk_add_provider(node, of_clk_src_simple_get, clk);
  242. }
  243. #endif
  244. /**
  245. * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
  246. * @node: device node containing the DPLL info
  247. * @ops: ops for the DPLL
  248. * @ddt: DPLL data template to use
  249. *
  250. * Initializes a DPLL clock from device tree data.
  251. */
  252. static void __init of_ti_dpll_setup(struct device_node *node,
  253. const struct clk_ops *ops,
  254. const struct dpll_data *ddt)
  255. {
  256. struct clk_hw_omap *clk_hw = NULL;
  257. struct clk_init_data *init = NULL;
  258. const char **parent_names = NULL;
  259. struct dpll_data *dd = NULL;
  260. u8 dpll_mode = 0;
  261. dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL);
  262. clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
  263. init = kzalloc(sizeof(*init), GFP_KERNEL);
  264. if (!dd || !clk_hw || !init)
  265. goto cleanup;
  266. clk_hw->dpll_data = dd;
  267. clk_hw->ops = &clkhwops_omap3_dpll;
  268. clk_hw->hw.init = init;
  269. init->name = node->name;
  270. init->ops = ops;
  271. init->num_parents = of_clk_get_parent_count(node);
  272. if (!init->num_parents) {
  273. pr_err("%pOFn must have parent(s)\n", node);
  274. goto cleanup;
  275. }
  276. parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
  277. if (!parent_names)
  278. goto cleanup;
  279. of_clk_parent_fill(node, parent_names, init->num_parents);
  280. init->parent_names = parent_names;
  281. if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
  282. goto cleanup;
  283. /*
  284. * Special case for OMAP2 DPLL, register order is different due to
  285. * missing idlest_reg, also clkhwops is different. Detected from
  286. * missing idlest_mask.
  287. */
  288. if (!dd->idlest_mask) {
  289. if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))
  290. goto cleanup;
  291. #ifdef CONFIG_ARCH_OMAP2
  292. clk_hw->ops = &clkhwops_omap2xxx_dpll;
  293. omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
  294. #endif
  295. } else {
  296. if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))
  297. goto cleanup;
  298. if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))
  299. goto cleanup;
  300. }
  301. if (dd->autoidle_mask) {
  302. if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
  303. goto cleanup;
  304. }
  305. if (of_property_read_bool(node, "ti,low-power-stop"))
  306. dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
  307. if (of_property_read_bool(node, "ti,low-power-bypass"))
  308. dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
  309. if (of_property_read_bool(node, "ti,lock"))
  310. dpll_mode |= 1 << DPLL_LOCKED;
  311. if (dpll_mode)
  312. dd->modes = dpll_mode;
  313. _register_dpll(&clk_hw->hw, node);
  314. return;
  315. cleanup:
  316. kfree(dd);
  317. kfree(parent_names);
  318. kfree(init);
  319. kfree(clk_hw);
  320. }
  321. #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
  322. defined(CONFIG_SOC_DRA7XX)
  323. static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
  324. {
  325. _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
  326. }
  327. CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
  328. of_ti_omap4_dpll_x2_setup);
  329. #endif
  330. #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
  331. static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
  332. {
  333. _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
  334. }
  335. CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
  336. of_ti_am3_dpll_x2_setup);
  337. #endif
  338. #ifdef CONFIG_ARCH_OMAP3
  339. static void __init of_ti_omap3_dpll_setup(struct device_node *node)
  340. {
  341. const struct dpll_data dd = {
  342. .idlest_mask = 0x1,
  343. .enable_mask = 0x7,
  344. .autoidle_mask = 0x7,
  345. .mult_mask = 0x7ff << 8,
  346. .div1_mask = 0x7f,
  347. .max_multiplier = 2047,
  348. .max_divider = 128,
  349. .min_divider = 1,
  350. .freqsel_mask = 0xf0,
  351. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  352. };
  353. if ((of_machine_is_compatible("ti,omap3630") ||
  354. of_machine_is_compatible("ti,omap36xx")) &&
  355. of_node_name_eq(node, "dpll5_ck"))
  356. of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd);
  357. else
  358. of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
  359. }
  360. CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
  361. of_ti_omap3_dpll_setup);
  362. static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
  363. {
  364. const struct dpll_data dd = {
  365. .idlest_mask = 0x1,
  366. .enable_mask = 0x7,
  367. .autoidle_mask = 0x7,
  368. .mult_mask = 0x7ff << 16,
  369. .div1_mask = 0x7f << 8,
  370. .max_multiplier = 2047,
  371. .max_divider = 128,
  372. .min_divider = 1,
  373. .freqsel_mask = 0xf0,
  374. };
  375. of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
  376. }
  377. CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
  378. of_ti_omap3_core_dpll_setup);
  379. static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
  380. {
  381. const struct dpll_data dd = {
  382. .idlest_mask = 0x1 << 1,
  383. .enable_mask = 0x7 << 16,
  384. .autoidle_mask = 0x7 << 3,
  385. .mult_mask = 0x7ff << 8,
  386. .div1_mask = 0x7f,
  387. .max_multiplier = 2047,
  388. .max_divider = 128,
  389. .min_divider = 1,
  390. .freqsel_mask = 0xf00000,
  391. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  392. };
  393. of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
  394. }
  395. CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
  396. of_ti_omap3_per_dpll_setup);
  397. static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
  398. {
  399. const struct dpll_data dd = {
  400. .idlest_mask = 0x1 << 1,
  401. .enable_mask = 0x7 << 16,
  402. .autoidle_mask = 0x7 << 3,
  403. .mult_mask = 0xfff << 8,
  404. .div1_mask = 0x7f,
  405. .max_multiplier = 4095,
  406. .max_divider = 128,
  407. .min_divider = 1,
  408. .sddiv_mask = 0xff << 24,
  409. .dco_mask = 0xe << 20,
  410. .flags = DPLL_J_TYPE,
  411. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  412. };
  413. of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
  414. }
  415. CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
  416. of_ti_omap3_per_jtype_dpll_setup);
  417. #endif
  418. static void __init of_ti_omap4_dpll_setup(struct device_node *node)
  419. {
  420. const struct dpll_data dd = {
  421. .idlest_mask = 0x1,
  422. .enable_mask = 0x7,
  423. .autoidle_mask = 0x7,
  424. .mult_mask = 0x7ff << 8,
  425. .div1_mask = 0x7f,
  426. .max_multiplier = 2047,
  427. .max_divider = 128,
  428. .min_divider = 1,
  429. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  430. };
  431. of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
  432. }
  433. CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
  434. of_ti_omap4_dpll_setup);
  435. static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
  436. {
  437. const struct dpll_data dd = {
  438. .idlest_mask = 0x1,
  439. .enable_mask = 0x7,
  440. .autoidle_mask = 0x7,
  441. .mult_mask = 0x7ff << 8,
  442. .div1_mask = 0x7f,
  443. .max_multiplier = 2047,
  444. .max_divider = 128,
  445. .dcc_mask = BIT(22),
  446. .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
  447. .min_divider = 1,
  448. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  449. };
  450. of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
  451. }
  452. CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
  453. of_ti_omap5_mpu_dpll_setup);
  454. static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
  455. {
  456. const struct dpll_data dd = {
  457. .idlest_mask = 0x1,
  458. .enable_mask = 0x7,
  459. .autoidle_mask = 0x7,
  460. .mult_mask = 0x7ff << 8,
  461. .div1_mask = 0x7f,
  462. .max_multiplier = 2047,
  463. .max_divider = 128,
  464. .min_divider = 1,
  465. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  466. };
  467. of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
  468. }
  469. CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
  470. of_ti_omap4_core_dpll_setup);
  471. #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
  472. defined(CONFIG_SOC_DRA7XX)
  473. static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
  474. {
  475. const struct dpll_data dd = {
  476. .idlest_mask = 0x1,
  477. .enable_mask = 0x7,
  478. .autoidle_mask = 0x7,
  479. .mult_mask = 0x7ff << 8,
  480. .div1_mask = 0x7f,
  481. .max_multiplier = 2047,
  482. .max_divider = 128,
  483. .min_divider = 1,
  484. .m4xen_mask = 0x800,
  485. .lpmode_mask = 1 << 10,
  486. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  487. };
  488. of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
  489. }
  490. CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
  491. of_ti_omap4_m4xen_dpll_setup);
  492. static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
  493. {
  494. const struct dpll_data dd = {
  495. .idlest_mask = 0x1,
  496. .enable_mask = 0x7,
  497. .autoidle_mask = 0x7,
  498. .mult_mask = 0xfff << 8,
  499. .div1_mask = 0xff,
  500. .max_multiplier = 4095,
  501. .max_divider = 256,
  502. .min_divider = 1,
  503. .sddiv_mask = 0xff << 24,
  504. .flags = DPLL_J_TYPE,
  505. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  506. };
  507. of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
  508. }
  509. CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
  510. of_ti_omap4_jtype_dpll_setup);
  511. #endif
  512. static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
  513. {
  514. const struct dpll_data dd = {
  515. .idlest_mask = 0x1,
  516. .enable_mask = 0x7,
  517. .mult_mask = 0x7ff << 8,
  518. .div1_mask = 0x7f,
  519. .max_multiplier = 2047,
  520. .max_divider = 128,
  521. .min_divider = 1,
  522. .max_rate = 1000000000,
  523. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  524. };
  525. of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
  526. }
  527. CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
  528. of_ti_am3_no_gate_dpll_setup);
  529. static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
  530. {
  531. const struct dpll_data dd = {
  532. .idlest_mask = 0x1,
  533. .enable_mask = 0x7,
  534. .mult_mask = 0x7ff << 8,
  535. .div1_mask = 0x7f,
  536. .max_multiplier = 4095,
  537. .max_divider = 256,
  538. .min_divider = 2,
  539. .flags = DPLL_J_TYPE,
  540. .max_rate = 2000000000,
  541. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  542. };
  543. of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
  544. }
  545. CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
  546. of_ti_am3_jtype_dpll_setup);
  547. static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
  548. {
  549. const struct dpll_data dd = {
  550. .idlest_mask = 0x1,
  551. .enable_mask = 0x7,
  552. .mult_mask = 0x7ff << 8,
  553. .div1_mask = 0x7f,
  554. .max_multiplier = 2047,
  555. .max_divider = 128,
  556. .min_divider = 1,
  557. .max_rate = 2000000000,
  558. .flags = DPLL_J_TYPE,
  559. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  560. };
  561. of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
  562. }
  563. CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
  564. "ti,am3-dpll-no-gate-j-type-clock",
  565. of_ti_am3_no_gate_jtype_dpll_setup);
  566. static void __init of_ti_am3_dpll_setup(struct device_node *node)
  567. {
  568. const struct dpll_data dd = {
  569. .idlest_mask = 0x1,
  570. .enable_mask = 0x7,
  571. .mult_mask = 0x7ff << 8,
  572. .div1_mask = 0x7f,
  573. .max_multiplier = 2047,
  574. .max_divider = 128,
  575. .min_divider = 1,
  576. .max_rate = 1000000000,
  577. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  578. };
  579. of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
  580. }
  581. CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
  582. static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
  583. {
  584. const struct dpll_data dd = {
  585. .idlest_mask = 0x1,
  586. .enable_mask = 0x7,
  587. .mult_mask = 0x7ff << 8,
  588. .div1_mask = 0x7f,
  589. .max_multiplier = 2047,
  590. .max_divider = 128,
  591. .min_divider = 1,
  592. .max_rate = 1000000000,
  593. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  594. };
  595. of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
  596. }
  597. CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
  598. of_ti_am3_core_dpll_setup);
  599. static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
  600. {
  601. const struct dpll_data dd = {
  602. .enable_mask = 0x3,
  603. .mult_mask = 0x3ff << 12,
  604. .div1_mask = 0xf << 8,
  605. .max_divider = 16,
  606. .min_divider = 1,
  607. };
  608. of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
  609. }
  610. CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
  611. of_ti_omap2_core_dpll_setup);