clock.h 9.1 KB

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  1. /*
  2. * TI Clock driver internal definitions
  3. *
  4. * Copyright (C) 2014 Texas Instruments, Inc
  5. * Tero Kristo (t-kristo@ti.com)
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #ifndef __DRIVERS_CLK_TI_CLOCK__
  17. #define __DRIVERS_CLK_TI_CLOCK__
  18. struct clk_omap_divider {
  19. struct clk_hw hw;
  20. struct clk_omap_reg reg;
  21. u8 shift;
  22. u8 flags;
  23. s8 latch;
  24. u16 min;
  25. u16 max;
  26. u16 mask;
  27. const struct clk_div_table *table;
  28. u32 context;
  29. };
  30. #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
  31. struct clk_omap_mux {
  32. struct clk_hw hw;
  33. struct clk_omap_reg reg;
  34. u32 *table;
  35. u32 mask;
  36. u8 shift;
  37. s8 latch;
  38. u8 flags;
  39. u8 saved_parent;
  40. };
  41. #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
  42. enum {
  43. TI_CLK_FIXED,
  44. TI_CLK_MUX,
  45. TI_CLK_DIVIDER,
  46. TI_CLK_COMPOSITE,
  47. TI_CLK_FIXED_FACTOR,
  48. TI_CLK_GATE,
  49. TI_CLK_DPLL,
  50. };
  51. /* Global flags */
  52. #define CLKF_INDEX_POWER_OF_TWO (1 << 0)
  53. #define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
  54. #define CLKF_SET_RATE_PARENT (1 << 2)
  55. #define CLKF_OMAP3 (1 << 3)
  56. #define CLKF_AM35XX (1 << 4)
  57. /* Gate flags */
  58. #define CLKF_SET_BIT_TO_DISABLE (1 << 5)
  59. #define CLKF_INTERFACE (1 << 6)
  60. #define CLKF_SSI (1 << 7)
  61. #define CLKF_DSS (1 << 8)
  62. #define CLKF_HSOTGUSB (1 << 9)
  63. #define CLKF_WAIT (1 << 10)
  64. #define CLKF_NO_WAIT (1 << 11)
  65. #define CLKF_HSDIV (1 << 12)
  66. #define CLKF_CLKDM (1 << 13)
  67. /* DPLL flags */
  68. #define CLKF_LOW_POWER_STOP (1 << 5)
  69. #define CLKF_LOCK (1 << 6)
  70. #define CLKF_LOW_POWER_BYPASS (1 << 7)
  71. #define CLKF_PER (1 << 8)
  72. #define CLKF_CORE (1 << 9)
  73. #define CLKF_J_TYPE (1 << 10)
  74. /* CLKCTRL flags */
  75. #define CLKF_SW_SUP BIT(5)
  76. #define CLKF_HW_SUP BIT(6)
  77. #define CLKF_NO_IDLEST BIT(7)
  78. #define CLKF_SOC_MASK GENMASK(11, 8)
  79. #define CLKF_SOC_NONSEC BIT(8)
  80. #define CLKF_SOC_DRA72 BIT(9)
  81. #define CLKF_SOC_DRA74 BIT(10)
  82. #define CLKF_SOC_DRA76 BIT(11)
  83. #define CLK(dev, con, ck) \
  84. { \
  85. .lk = { \
  86. .dev_id = dev, \
  87. .con_id = con, \
  88. }, \
  89. .clk = ck, \
  90. }
  91. struct ti_clk {
  92. const char *name;
  93. const char *clkdm_name;
  94. int type;
  95. void *data;
  96. struct ti_clk *patch;
  97. struct clk *clk;
  98. };
  99. struct ti_clk_mux {
  100. u8 bit_shift;
  101. int num_parents;
  102. u16 reg;
  103. u8 module;
  104. const char * const *parents;
  105. u16 flags;
  106. };
  107. struct ti_clk_divider {
  108. const char *parent;
  109. u8 bit_shift;
  110. u16 max_div;
  111. u16 reg;
  112. u8 module;
  113. int *dividers;
  114. int num_dividers;
  115. u16 flags;
  116. };
  117. struct ti_clk_gate {
  118. const char *parent;
  119. u8 bit_shift;
  120. u16 reg;
  121. u8 module;
  122. u16 flags;
  123. };
  124. /* Composite clock component types */
  125. enum {
  126. CLK_COMPONENT_TYPE_GATE = 0,
  127. CLK_COMPONENT_TYPE_DIVIDER,
  128. CLK_COMPONENT_TYPE_MUX,
  129. CLK_COMPONENT_TYPE_MAX,
  130. };
  131. /**
  132. * struct ti_dt_clk - OMAP DT clock alias declarations
  133. * @lk: clock lookup definition
  134. * @node_name: clock DT node to map to
  135. */
  136. struct ti_dt_clk {
  137. struct clk_lookup lk;
  138. char *node_name;
  139. };
  140. #define DT_CLK(dev, con, name) \
  141. { \
  142. .lk = { \
  143. .dev_id = dev, \
  144. .con_id = con, \
  145. }, \
  146. .node_name = name, \
  147. }
  148. /* CLKCTRL type definitions */
  149. struct omap_clkctrl_div_data {
  150. const int *dividers;
  151. int max_div;
  152. u32 flags;
  153. };
  154. struct omap_clkctrl_bit_data {
  155. u8 bit;
  156. u8 type;
  157. const char * const *parents;
  158. const void *data;
  159. };
  160. struct omap_clkctrl_reg_data {
  161. u16 offset;
  162. const struct omap_clkctrl_bit_data *bit_data;
  163. u16 flags;
  164. const char *parent;
  165. const char *clkdm_name;
  166. };
  167. struct omap_clkctrl_data {
  168. u32 addr;
  169. const struct omap_clkctrl_reg_data *regs;
  170. };
  171. extern const struct omap_clkctrl_data omap4_clkctrl_data[];
  172. extern const struct omap_clkctrl_data omap5_clkctrl_data[];
  173. extern const struct omap_clkctrl_data dra7_clkctrl_data[];
  174. extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[];
  175. extern struct ti_dt_clk dra7xx_compat_clks[];
  176. extern const struct omap_clkctrl_data am3_clkctrl_data[];
  177. extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
  178. extern struct ti_dt_clk am33xx_compat_clks[];
  179. extern const struct omap_clkctrl_data am4_clkctrl_data[];
  180. extern const struct omap_clkctrl_data am4_clkctrl_compat_data[];
  181. extern struct ti_dt_clk am43xx_compat_clks[];
  182. extern const struct omap_clkctrl_data am438x_clkctrl_data[];
  183. extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[];
  184. extern const struct omap_clkctrl_data dm814_clkctrl_data[];
  185. extern const struct omap_clkctrl_data dm816_clkctrl_data[];
  186. typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
  187. struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
  188. const char *con);
  189. struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw,
  190. const char *con);
  191. int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
  192. void ti_clk_add_aliases(void);
  193. void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);
  194. struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
  195. int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
  196. u8 flags, struct clk_omap_divider *div);
  197. int ti_clk_get_reg_addr(struct device_node *node, int index,
  198. struct clk_omap_reg *reg);
  199. void ti_dt_clocks_register(struct ti_dt_clk *oclks);
  200. int ti_clk_retry_init(struct device_node *node, void *user,
  201. ti_of_clk_init_cb_t func);
  202. int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
  203. int of_ti_clk_autoidle_setup(struct device_node *node);
  204. void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
  205. extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
  206. extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
  207. extern const struct clk_hw_omap_ops clkhwops_wait;
  208. extern const struct clk_hw_omap_ops clkhwops_iclk;
  209. extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
  210. extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
  211. extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
  212. extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
  213. extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
  214. extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
  215. extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
  216. extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
  217. extern const struct clk_ops ti_clk_divider_ops;
  218. extern const struct clk_ops ti_clk_mux_ops;
  219. extern const struct clk_ops omap_gate_clk_ops;
  220. extern struct ti_clk_features ti_clk_features;
  221. int omap2_init_clk_clkdm(struct clk_hw *hw);
  222. int omap2_clkops_enable_clkdm(struct clk_hw *hw);
  223. void omap2_clkops_disable_clkdm(struct clk_hw *hw);
  224. int omap2_dflt_clk_enable(struct clk_hw *hw);
  225. void omap2_dflt_clk_disable(struct clk_hw *hw);
  226. int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
  227. void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
  228. struct clk_omap_reg *other_reg,
  229. u8 *other_bit);
  230. void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
  231. struct clk_omap_reg *idlest_reg,
  232. u8 *idlest_bit, u8 *idlest_val);
  233. void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
  234. void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
  235. u8 omap2_init_dpll_parent(struct clk_hw *hw);
  236. int omap3_noncore_dpll_enable(struct clk_hw *hw);
  237. void omap3_noncore_dpll_disable(struct clk_hw *hw);
  238. int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
  239. int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
  240. unsigned long parent_rate);
  241. int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
  242. unsigned long rate,
  243. unsigned long parent_rate,
  244. u8 index);
  245. int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
  246. struct clk_rate_request *req);
  247. long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
  248. unsigned long *parent_rate);
  249. unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
  250. unsigned long parent_rate);
  251. /*
  252. * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
  253. * that are sourced by DPLL5, and both of these require this clock
  254. * to be at 120 MHz for proper operation.
  255. */
  256. #define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000
  257. unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
  258. int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
  259. unsigned long parent_rate);
  260. int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
  261. unsigned long parent_rate, u8 index);
  262. int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
  263. unsigned long parent_rate);
  264. void omap3_clk_lock_dpll5(void);
  265. unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
  266. unsigned long parent_rate);
  267. long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
  268. unsigned long target_rate,
  269. unsigned long *parent_rate);
  270. int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
  271. struct clk_rate_request *req);
  272. int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw));
  273. extern struct ti_clk_ll_ops *ti_clk_ll_ops;
  274. #endif