clkt_dpll.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * OMAP2/3/4 DPLL clock functions
  4. *
  5. * Copyright (C) 2005-2008 Texas Instruments, Inc.
  6. * Copyright (C) 2004-2010 Nokia Corporation
  7. *
  8. * Contacts:
  9. * Richard Woodruff <r-woodruff2@ti.com>
  10. * Paul Walmsley
  11. */
  12. #undef DEBUG
  13. #include <linux/kernel.h>
  14. #include <linux/errno.h>
  15. #include <linux/clk.h>
  16. #include <linux/clk-provider.h>
  17. #include <linux/io.h>
  18. #include <linux/clk/ti.h>
  19. #include <asm/div64.h>
  20. #include "clock.h"
  21. /* DPLL rate rounding: minimum DPLL multiplier, divider values */
  22. #define DPLL_MIN_MULTIPLIER 2
  23. #define DPLL_MIN_DIVIDER 1
  24. /* Possible error results from _dpll_test_mult */
  25. #define DPLL_MULT_UNDERFLOW -1
  26. /*
  27. * Scale factor to mitigate roundoff errors in DPLL rate rounding.
  28. * The higher the scale factor, the greater the risk of arithmetic overflow,
  29. * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
  30. * must be a power of DPLL_SCALE_BASE.
  31. */
  32. #define DPLL_SCALE_FACTOR 64
  33. #define DPLL_SCALE_BASE 2
  34. #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
  35. (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
  36. /*
  37. * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
  38. * From device data manual section 4.3 "DPLL and DLL Specifications".
  39. */
  40. #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
  41. #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
  42. /* _dpll_test_fint() return codes */
  43. #define DPLL_FINT_UNDERFLOW -1
  44. #define DPLL_FINT_INVALID -2
  45. /* Private functions */
  46. /*
  47. * _dpll_test_fint - test whether an Fint value is valid for the DPLL
  48. * @clk: DPLL struct clk to test
  49. * @n: divider value (N) to test
  50. *
  51. * Tests whether a particular divider @n will result in a valid DPLL
  52. * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
  53. * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
  54. * (assuming that it is counting N upwards), or -2 if the enclosing loop
  55. * should skip to the next iteration (again assuming N is increasing).
  56. */
  57. static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
  58. {
  59. struct dpll_data *dd;
  60. long fint, fint_min, fint_max;
  61. int ret = 0;
  62. dd = clk->dpll_data;
  63. /* DPLL divider must result in a valid jitter correction val */
  64. fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n;
  65. if (dd->flags & DPLL_J_TYPE) {
  66. fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
  67. fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
  68. } else {
  69. fint_min = ti_clk_get_features()->fint_min;
  70. fint_max = ti_clk_get_features()->fint_max;
  71. }
  72. if (!fint_min || !fint_max) {
  73. WARN(1, "No fint limits available!\n");
  74. return DPLL_FINT_INVALID;
  75. }
  76. if (fint < ti_clk_get_features()->fint_min) {
  77. pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
  78. n);
  79. dd->max_divider = n;
  80. ret = DPLL_FINT_UNDERFLOW;
  81. } else if (fint > ti_clk_get_features()->fint_max) {
  82. pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
  83. n);
  84. dd->min_divider = n;
  85. ret = DPLL_FINT_INVALID;
  86. } else if (fint > ti_clk_get_features()->fint_band1_max &&
  87. fint < ti_clk_get_features()->fint_band2_min) {
  88. pr_debug("rejecting n=%d due to Fint failure\n", n);
  89. ret = DPLL_FINT_INVALID;
  90. }
  91. return ret;
  92. }
  93. static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
  94. unsigned int m, unsigned int n)
  95. {
  96. unsigned long long num;
  97. num = (unsigned long long)parent_rate * m;
  98. do_div(num, n);
  99. return num;
  100. }
  101. /*
  102. * _dpll_test_mult - test a DPLL multiplier value
  103. * @m: pointer to the DPLL m (multiplier) value under test
  104. * @n: current DPLL n (divider) value under test
  105. * @new_rate: pointer to storage for the resulting rounded rate
  106. * @target_rate: the desired DPLL rate
  107. * @parent_rate: the DPLL's parent clock rate
  108. *
  109. * This code tests a DPLL multiplier value, ensuring that the
  110. * resulting rate will not be higher than the target_rate, and that
  111. * the multiplier value itself is valid for the DPLL. Initially, the
  112. * integer pointed to by the m argument should be prescaled by
  113. * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
  114. * a non-scaled m upon return. This non-scaled m will result in a
  115. * new_rate as close as possible to target_rate (but not greater than
  116. * target_rate) given the current (parent_rate, n, prescaled m)
  117. * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
  118. * non-scaled m attempted to underflow, which can allow the calling
  119. * function to bail out early; or 0 upon success.
  120. */
  121. static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
  122. unsigned long target_rate,
  123. unsigned long parent_rate)
  124. {
  125. int r = 0, carry = 0;
  126. /* Unscale m and round if necessary */
  127. if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
  128. carry = 1;
  129. *m = (*m / DPLL_SCALE_FACTOR) + carry;
  130. /*
  131. * The new rate must be <= the target rate to avoid programming
  132. * a rate that is impossible for the hardware to handle
  133. */
  134. *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
  135. if (*new_rate > target_rate) {
  136. (*m)--;
  137. *new_rate = 0;
  138. }
  139. /* Guard against m underflow */
  140. if (*m < DPLL_MIN_MULTIPLIER) {
  141. *m = DPLL_MIN_MULTIPLIER;
  142. *new_rate = 0;
  143. r = DPLL_MULT_UNDERFLOW;
  144. }
  145. if (*new_rate == 0)
  146. *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
  147. return r;
  148. }
  149. /**
  150. * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
  151. * @v: bitfield value of the DPLL enable
  152. *
  153. * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
  154. * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
  155. */
  156. static int _omap2_dpll_is_in_bypass(u32 v)
  157. {
  158. u8 mask, val;
  159. mask = ti_clk_get_features()->dpll_bypass_vals;
  160. /*
  161. * Each set bit in the mask corresponds to a bypass value equal
  162. * to the bitshift. Go through each set-bit in the mask and
  163. * compare against the given register value.
  164. */
  165. while (mask) {
  166. val = __ffs(mask);
  167. mask ^= (1 << val);
  168. if (v == val)
  169. return 1;
  170. }
  171. return 0;
  172. }
  173. /* Public functions */
  174. u8 omap2_init_dpll_parent(struct clk_hw *hw)
  175. {
  176. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  177. u32 v;
  178. struct dpll_data *dd;
  179. dd = clk->dpll_data;
  180. if (!dd)
  181. return -EINVAL;
  182. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  183. v &= dd->enable_mask;
  184. v >>= __ffs(dd->enable_mask);
  185. /* Reparent the struct clk in case the dpll is in bypass */
  186. if (_omap2_dpll_is_in_bypass(v))
  187. return 1;
  188. return 0;
  189. }
  190. /**
  191. * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
  192. * @clk: struct clk * of a DPLL
  193. *
  194. * DPLLs can be locked or bypassed - basically, enabled or disabled.
  195. * When locked, the DPLL output depends on the M and N values. When
  196. * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
  197. * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
  198. * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
  199. * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
  200. * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
  201. * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
  202. * if the clock @clk is not a DPLL.
  203. */
  204. unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
  205. {
  206. u64 dpll_clk;
  207. u32 dpll_mult, dpll_div, v;
  208. struct dpll_data *dd;
  209. dd = clk->dpll_data;
  210. if (!dd)
  211. return 0;
  212. /* Return bypass rate if DPLL is bypassed */
  213. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  214. v &= dd->enable_mask;
  215. v >>= __ffs(dd->enable_mask);
  216. if (_omap2_dpll_is_in_bypass(v))
  217. return clk_hw_get_rate(dd->clk_bypass);
  218. v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
  219. dpll_mult = v & dd->mult_mask;
  220. dpll_mult >>= __ffs(dd->mult_mask);
  221. dpll_div = v & dd->div1_mask;
  222. dpll_div >>= __ffs(dd->div1_mask);
  223. dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult;
  224. do_div(dpll_clk, dpll_div + 1);
  225. return dpll_clk;
  226. }
  227. /* DPLL rate rounding code */
  228. /**
  229. * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
  230. * @clk: struct clk * for a DPLL
  231. * @target_rate: desired DPLL clock rate
  232. *
  233. * Given a DPLL and a desired target rate, round the target rate to a
  234. * possible, programmable rate for this DPLL. Attempts to select the
  235. * minimum possible n. Stores the computed (m, n) in the DPLL's
  236. * dpll_data structure so set_rate() will not need to call this
  237. * (expensive) function again. Returns ~0 if the target rate cannot
  238. * be rounded, or the rounded rate upon success.
  239. */
  240. long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
  241. unsigned long *parent_rate)
  242. {
  243. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  244. int m, n, r, scaled_max_m;
  245. int min_delta_m = INT_MAX, min_delta_n = INT_MAX;
  246. unsigned long scaled_rt_rp;
  247. unsigned long new_rate = 0;
  248. struct dpll_data *dd;
  249. unsigned long ref_rate;
  250. long delta;
  251. long prev_min_delta = LONG_MAX;
  252. const char *clk_name;
  253. if (!clk || !clk->dpll_data)
  254. return ~0;
  255. dd = clk->dpll_data;
  256. if (dd->max_rate && target_rate > dd->max_rate)
  257. target_rate = dd->max_rate;
  258. ref_rate = clk_hw_get_rate(dd->clk_ref);
  259. clk_name = clk_hw_get_name(hw);
  260. pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
  261. clk_name, target_rate);
  262. scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
  263. scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
  264. dd->last_rounded_rate = 0;
  265. for (n = dd->min_divider; n <= dd->max_divider; n++) {
  266. /* Is the (input clk, divider) pair valid for the DPLL? */
  267. r = _dpll_test_fint(clk, n);
  268. if (r == DPLL_FINT_UNDERFLOW)
  269. break;
  270. else if (r == DPLL_FINT_INVALID)
  271. continue;
  272. /* Compute the scaled DPLL multiplier, based on the divider */
  273. m = scaled_rt_rp * n;
  274. /*
  275. * Since we're counting n up, a m overflow means we
  276. * can bail out completely (since as n increases in
  277. * the next iteration, there's no way that m can
  278. * increase beyond the current m)
  279. */
  280. if (m > scaled_max_m)
  281. break;
  282. r = _dpll_test_mult(&m, n, &new_rate, target_rate,
  283. ref_rate);
  284. /* m can't be set low enough for this n - try with a larger n */
  285. if (r == DPLL_MULT_UNDERFLOW)
  286. continue;
  287. /* skip rates above our target rate */
  288. delta = target_rate - new_rate;
  289. if (delta < 0)
  290. continue;
  291. if (delta < prev_min_delta) {
  292. prev_min_delta = delta;
  293. min_delta_m = m;
  294. min_delta_n = n;
  295. }
  296. pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
  297. clk_name, m, n, new_rate);
  298. if (delta == 0)
  299. break;
  300. }
  301. if (prev_min_delta == LONG_MAX) {
  302. pr_debug("clock: %s: cannot round to rate %lu\n",
  303. clk_name, target_rate);
  304. return ~0;
  305. }
  306. dd->last_rounded_m = min_delta_m;
  307. dd->last_rounded_n = min_delta_n;
  308. dd->last_rounded_rate = target_rate - prev_min_delta;
  309. return dd->last_rounded_rate;
  310. }