clkctrl.c 18 KB

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  1. /*
  2. * OMAP clkctrl clock support
  3. *
  4. * Copyright (C) 2017 Texas Instruments, Inc.
  5. *
  6. * Tero Kristo <t-kristo@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/clk-provider.h>
  18. #include <linux/slab.h>
  19. #include <linux/of.h>
  20. #include <linux/of_address.h>
  21. #include <linux/clk/ti.h>
  22. #include <linux/delay.h>
  23. #include <linux/timekeeping.h>
  24. #include "clock.h"
  25. #define NO_IDLEST 0
  26. #define OMAP4_MODULEMODE_MASK 0x3
  27. #define MODULEMODE_HWCTRL 0x1
  28. #define MODULEMODE_SWCTRL 0x2
  29. #define OMAP4_IDLEST_MASK (0x3 << 16)
  30. #define OMAP4_IDLEST_SHIFT 16
  31. #define OMAP4_STBYST_MASK BIT(18)
  32. #define OMAP4_STBYST_SHIFT 18
  33. #define CLKCTRL_IDLEST_FUNCTIONAL 0x0
  34. #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
  35. #define CLKCTRL_IDLEST_DISABLED 0x3
  36. /* These timeouts are in us */
  37. #define OMAP4_MAX_MODULE_READY_TIME 2000
  38. #define OMAP4_MAX_MODULE_DISABLE_TIME 5000
  39. static bool _early_timeout = true;
  40. struct omap_clkctrl_provider {
  41. void __iomem *base;
  42. struct list_head clocks;
  43. char *clkdm_name;
  44. };
  45. struct omap_clkctrl_clk {
  46. struct clk_hw *clk;
  47. u16 reg_offset;
  48. int bit_offset;
  49. struct list_head node;
  50. };
  51. union omap4_timeout {
  52. u32 cycles;
  53. ktime_t start;
  54. };
  55. static const struct omap_clkctrl_data default_clkctrl_data[] __initconst = {
  56. { 0 },
  57. };
  58. static u32 _omap4_idlest(u32 val)
  59. {
  60. val &= OMAP4_IDLEST_MASK;
  61. val >>= OMAP4_IDLEST_SHIFT;
  62. return val;
  63. }
  64. static bool _omap4_is_idle(u32 val)
  65. {
  66. val = _omap4_idlest(val);
  67. return val == CLKCTRL_IDLEST_DISABLED;
  68. }
  69. static bool _omap4_is_ready(u32 val)
  70. {
  71. val = _omap4_idlest(val);
  72. return val == CLKCTRL_IDLEST_FUNCTIONAL ||
  73. val == CLKCTRL_IDLEST_INTERFACE_IDLE;
  74. }
  75. static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
  76. {
  77. /*
  78. * There are two special cases where ktime_to_ns() can't be
  79. * used to track the timeouts. First one is during early boot
  80. * when the timers haven't been initialized yet. The second
  81. * one is during suspend-resume cycle while timekeeping is
  82. * being suspended / resumed. Clocksource for the system
  83. * can be from a timer that requires pm_runtime access, which
  84. * will eventually bring us here with timekeeping_suspended,
  85. * during both suspend entry and resume paths. This happens
  86. * at least on am43xx platform. Account for flakeyness
  87. * with udelay() by multiplying the timeout value by 2.
  88. */
  89. if (unlikely(_early_timeout || timekeeping_suspended)) {
  90. if (time->cycles++ < timeout) {
  91. udelay(1 * 2);
  92. return false;
  93. }
  94. } else {
  95. if (!ktime_to_ns(time->start)) {
  96. time->start = ktime_get();
  97. return false;
  98. }
  99. if (ktime_us_delta(ktime_get(), time->start) < timeout) {
  100. cpu_relax();
  101. return false;
  102. }
  103. }
  104. return true;
  105. }
  106. static int __init _omap4_disable_early_timeout(void)
  107. {
  108. _early_timeout = false;
  109. return 0;
  110. }
  111. arch_initcall(_omap4_disable_early_timeout);
  112. static int _omap4_clkctrl_clk_enable(struct clk_hw *hw)
  113. {
  114. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  115. u32 val;
  116. int ret;
  117. union omap4_timeout timeout = { 0 };
  118. if (clk->clkdm) {
  119. ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
  120. if (ret) {
  121. WARN(1,
  122. "%s: could not enable %s's clockdomain %s: %d\n",
  123. __func__, clk_hw_get_name(hw),
  124. clk->clkdm_name, ret);
  125. return ret;
  126. }
  127. }
  128. if (!clk->enable_bit)
  129. return 0;
  130. val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
  131. val &= ~OMAP4_MODULEMODE_MASK;
  132. val |= clk->enable_bit;
  133. ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
  134. if (test_bit(NO_IDLEST, &clk->flags))
  135. return 0;
  136. /* Wait until module is enabled */
  137. while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
  138. if (_omap4_is_timeout(&timeout, OMAP4_MAX_MODULE_READY_TIME)) {
  139. pr_err("%s: failed to enable\n", clk_hw_get_name(hw));
  140. return -EBUSY;
  141. }
  142. }
  143. return 0;
  144. }
  145. static void _omap4_clkctrl_clk_disable(struct clk_hw *hw)
  146. {
  147. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  148. u32 val;
  149. union omap4_timeout timeout = { 0 };
  150. if (!clk->enable_bit)
  151. goto exit;
  152. val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
  153. val &= ~OMAP4_MODULEMODE_MASK;
  154. ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
  155. if (test_bit(NO_IDLEST, &clk->flags))
  156. goto exit;
  157. /* Wait until module is disabled */
  158. while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
  159. if (_omap4_is_timeout(&timeout,
  160. OMAP4_MAX_MODULE_DISABLE_TIME)) {
  161. pr_err("%s: failed to disable\n", clk_hw_get_name(hw));
  162. break;
  163. }
  164. }
  165. exit:
  166. if (clk->clkdm)
  167. ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
  168. }
  169. static int _omap4_clkctrl_clk_is_enabled(struct clk_hw *hw)
  170. {
  171. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  172. u32 val;
  173. val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
  174. if (val & clk->enable_bit)
  175. return 1;
  176. return 0;
  177. }
  178. static const struct clk_ops omap4_clkctrl_clk_ops = {
  179. .enable = _omap4_clkctrl_clk_enable,
  180. .disable = _omap4_clkctrl_clk_disable,
  181. .is_enabled = _omap4_clkctrl_clk_is_enabled,
  182. .init = omap2_init_clk_clkdm,
  183. };
  184. static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
  185. void *data)
  186. {
  187. struct omap_clkctrl_provider *provider = data;
  188. struct omap_clkctrl_clk *entry;
  189. bool found = false;
  190. if (clkspec->args_count != 2)
  191. return ERR_PTR(-EINVAL);
  192. pr_debug("%s: looking for %x:%x\n", __func__,
  193. clkspec->args[0], clkspec->args[1]);
  194. list_for_each_entry(entry, &provider->clocks, node) {
  195. if (entry->reg_offset == clkspec->args[0] &&
  196. entry->bit_offset == clkspec->args[1]) {
  197. found = true;
  198. break;
  199. }
  200. }
  201. if (!found)
  202. return ERR_PTR(-EINVAL);
  203. return entry->clk;
  204. }
  205. /* Get clkctrl clock base name based on clkctrl_name or dts node */
  206. static const char * __init clkctrl_get_clock_name(struct device_node *np,
  207. const char *clkctrl_name,
  208. int offset, int index,
  209. bool legacy_naming)
  210. {
  211. char *clock_name;
  212. /* l4per-clkctrl:1234:0 style naming based on clkctrl_name */
  213. if (clkctrl_name && !legacy_naming) {
  214. clock_name = kasprintf(GFP_KERNEL, "%s-clkctrl:%04x:%d",
  215. clkctrl_name, offset, index);
  216. strreplace(clock_name, '_', '-');
  217. return clock_name;
  218. }
  219. /* l4per:1234:0 old style naming based on clkctrl_name */
  220. if (clkctrl_name)
  221. return kasprintf(GFP_KERNEL, "%s_cm:clk:%04x:%d",
  222. clkctrl_name, offset, index);
  223. /* l4per_cm:1234:0 old style naming based on parent node name */
  224. if (legacy_naming)
  225. return kasprintf(GFP_KERNEL, "%pOFn:clk:%04x:%d",
  226. np->parent, offset, index);
  227. /* l4per-clkctrl:1234:0 style naming based on node name */
  228. return kasprintf(GFP_KERNEL, "%pOFn:%04x:%d", np, offset, index);
  229. }
  230. static int __init
  231. _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
  232. struct device_node *node, struct clk_hw *clk_hw,
  233. u16 offset, u8 bit, const char * const *parents,
  234. int num_parents, const struct clk_ops *ops,
  235. const char *clkctrl_name)
  236. {
  237. struct clk_init_data init = { NULL };
  238. struct clk *clk;
  239. struct omap_clkctrl_clk *clkctrl_clk;
  240. int ret = 0;
  241. init.name = clkctrl_get_clock_name(node, clkctrl_name, offset, bit,
  242. ti_clk_get_features()->flags &
  243. TI_CLK_CLKCTRL_COMPAT);
  244. clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
  245. if (!init.name || !clkctrl_clk) {
  246. ret = -ENOMEM;
  247. goto cleanup;
  248. }
  249. clk_hw->init = &init;
  250. init.parent_names = parents;
  251. init.num_parents = num_parents;
  252. init.ops = ops;
  253. init.flags = 0;
  254. clk = ti_clk_register(NULL, clk_hw, init.name);
  255. if (IS_ERR_OR_NULL(clk)) {
  256. ret = -EINVAL;
  257. goto cleanup;
  258. }
  259. clkctrl_clk->reg_offset = offset;
  260. clkctrl_clk->bit_offset = bit;
  261. clkctrl_clk->clk = clk_hw;
  262. list_add(&clkctrl_clk->node, &provider->clocks);
  263. return 0;
  264. cleanup:
  265. kfree(init.name);
  266. kfree(clkctrl_clk);
  267. return ret;
  268. }
  269. static void __init
  270. _ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider,
  271. struct device_node *node, u16 offset,
  272. const struct omap_clkctrl_bit_data *data,
  273. void __iomem *reg, const char *clkctrl_name)
  274. {
  275. struct clk_hw_omap *clk_hw;
  276. clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
  277. if (!clk_hw)
  278. return;
  279. clk_hw->enable_bit = data->bit;
  280. clk_hw->enable_reg.ptr = reg;
  281. if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset,
  282. data->bit, data->parents, 1,
  283. &omap_gate_clk_ops, clkctrl_name))
  284. kfree(clk_hw);
  285. }
  286. static void __init
  287. _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
  288. struct device_node *node, u16 offset,
  289. const struct omap_clkctrl_bit_data *data,
  290. void __iomem *reg, const char *clkctrl_name)
  291. {
  292. struct clk_omap_mux *mux;
  293. int num_parents = 0;
  294. const char * const *pname;
  295. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  296. if (!mux)
  297. return;
  298. pname = data->parents;
  299. while (*pname) {
  300. num_parents++;
  301. pname++;
  302. }
  303. mux->mask = num_parents;
  304. if (!(mux->flags & CLK_MUX_INDEX_ONE))
  305. mux->mask--;
  306. mux->mask = (1 << fls(mux->mask)) - 1;
  307. mux->shift = data->bit;
  308. mux->reg.ptr = reg;
  309. if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset,
  310. data->bit, data->parents, num_parents,
  311. &ti_clk_mux_ops, clkctrl_name))
  312. kfree(mux);
  313. }
  314. static void __init
  315. _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
  316. struct device_node *node, u16 offset,
  317. const struct omap_clkctrl_bit_data *data,
  318. void __iomem *reg, const char *clkctrl_name)
  319. {
  320. struct clk_omap_divider *div;
  321. const struct omap_clkctrl_div_data *div_data = data->data;
  322. u8 div_flags = 0;
  323. div = kzalloc(sizeof(*div), GFP_KERNEL);
  324. if (!div)
  325. return;
  326. div->reg.ptr = reg;
  327. div->shift = data->bit;
  328. div->flags = div_data->flags;
  329. if (div->flags & CLK_DIVIDER_POWER_OF_TWO)
  330. div_flags |= CLKF_INDEX_POWER_OF_TWO;
  331. if (ti_clk_parse_divider_data((int *)div_data->dividers, 0,
  332. div_data->max_div, div_flags,
  333. div)) {
  334. pr_err("%s: Data parsing for %pOF:%04x:%d failed\n", __func__,
  335. node, offset, data->bit);
  336. kfree(div);
  337. return;
  338. }
  339. if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset,
  340. data->bit, data->parents, 1,
  341. &ti_clk_divider_ops, clkctrl_name))
  342. kfree(div);
  343. }
  344. static void __init
  345. _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
  346. struct device_node *node,
  347. const struct omap_clkctrl_reg_data *data,
  348. void __iomem *reg, const char *clkctrl_name)
  349. {
  350. const struct omap_clkctrl_bit_data *bits = data->bit_data;
  351. if (!bits)
  352. return;
  353. while (bits->bit) {
  354. switch (bits->type) {
  355. case TI_CLK_GATE:
  356. _ti_clkctrl_setup_gate(provider, node, data->offset,
  357. bits, reg, clkctrl_name);
  358. break;
  359. case TI_CLK_DIVIDER:
  360. _ti_clkctrl_setup_div(provider, node, data->offset,
  361. bits, reg, clkctrl_name);
  362. break;
  363. case TI_CLK_MUX:
  364. _ti_clkctrl_setup_mux(provider, node, data->offset,
  365. bits, reg, clkctrl_name);
  366. break;
  367. default:
  368. pr_err("%s: bad subclk type: %d\n", __func__,
  369. bits->type);
  370. return;
  371. }
  372. bits++;
  373. }
  374. }
  375. static void __init _clkctrl_add_provider(void *data,
  376. struct device_node *np)
  377. {
  378. of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data);
  379. }
  380. /* Get clock name based on compatible string for clkctrl */
  381. static char * __init clkctrl_get_name(struct device_node *np)
  382. {
  383. struct property *prop;
  384. const int prefix_len = 11;
  385. const char *compat;
  386. char *name;
  387. of_property_for_each_string(np, "compatible", prop, compat) {
  388. if (!strncmp("ti,clkctrl-", compat, prefix_len)) {
  389. /* Two letter minimum name length for l3, l4 etc */
  390. if (strnlen(compat + prefix_len, 16) < 2)
  391. continue;
  392. name = kasprintf(GFP_KERNEL, "%s", compat + prefix_len);
  393. if (!name)
  394. continue;
  395. strreplace(name, '-', '_');
  396. return name;
  397. }
  398. }
  399. return NULL;
  400. }
  401. static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
  402. {
  403. struct omap_clkctrl_provider *provider;
  404. const struct omap_clkctrl_data *data = default_clkctrl_data;
  405. const struct omap_clkctrl_reg_data *reg_data;
  406. struct clk_init_data init = { NULL };
  407. struct clk_hw_omap *hw;
  408. struct clk *clk;
  409. struct omap_clkctrl_clk *clkctrl_clk = NULL;
  410. const __be32 *addrp;
  411. bool legacy_naming;
  412. char *clkctrl_name;
  413. u32 addr;
  414. int ret;
  415. char *c;
  416. u16 soc_mask = 0;
  417. if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
  418. of_node_name_eq(node, "clk"))
  419. ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT;
  420. addrp = of_get_address(node, 0, NULL, NULL);
  421. addr = (u32)of_translate_address(node, addrp);
  422. #ifdef CONFIG_ARCH_OMAP4
  423. if (of_machine_is_compatible("ti,omap4"))
  424. data = omap4_clkctrl_data;
  425. #endif
  426. #ifdef CONFIG_SOC_OMAP5
  427. if (of_machine_is_compatible("ti,omap5"))
  428. data = omap5_clkctrl_data;
  429. #endif
  430. #ifdef CONFIG_SOC_DRA7XX
  431. if (of_machine_is_compatible("ti,dra7")) {
  432. if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
  433. data = dra7_clkctrl_compat_data;
  434. else
  435. data = dra7_clkctrl_data;
  436. }
  437. if (of_machine_is_compatible("ti,dra72"))
  438. soc_mask = CLKF_SOC_DRA72;
  439. if (of_machine_is_compatible("ti,dra74"))
  440. soc_mask = CLKF_SOC_DRA74;
  441. if (of_machine_is_compatible("ti,dra76"))
  442. soc_mask = CLKF_SOC_DRA76;
  443. #endif
  444. #ifdef CONFIG_SOC_AM33XX
  445. if (of_machine_is_compatible("ti,am33xx")) {
  446. if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
  447. data = am3_clkctrl_compat_data;
  448. else
  449. data = am3_clkctrl_data;
  450. }
  451. #endif
  452. #ifdef CONFIG_SOC_AM43XX
  453. if (of_machine_is_compatible("ti,am4372")) {
  454. if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
  455. data = am4_clkctrl_compat_data;
  456. else
  457. data = am4_clkctrl_data;
  458. }
  459. if (of_machine_is_compatible("ti,am438x")) {
  460. if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
  461. data = am438x_clkctrl_compat_data;
  462. else
  463. data = am438x_clkctrl_data;
  464. }
  465. #endif
  466. #ifdef CONFIG_SOC_TI81XX
  467. if (of_machine_is_compatible("ti,dm814"))
  468. data = dm814_clkctrl_data;
  469. if (of_machine_is_compatible("ti,dm816"))
  470. data = dm816_clkctrl_data;
  471. #endif
  472. if (ti_clk_get_features()->flags & TI_CLK_DEVICE_TYPE_GP)
  473. soc_mask |= CLKF_SOC_NONSEC;
  474. while (data->addr) {
  475. if (addr == data->addr)
  476. break;
  477. data++;
  478. }
  479. if (!data->addr) {
  480. pr_err("%pOF not found from clkctrl data.\n", node);
  481. return;
  482. }
  483. provider = kzalloc(sizeof(*provider), GFP_KERNEL);
  484. if (!provider)
  485. return;
  486. provider->base = of_iomap(node, 0);
  487. legacy_naming = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT;
  488. clkctrl_name = clkctrl_get_name(node);
  489. if (clkctrl_name) {
  490. provider->clkdm_name = kasprintf(GFP_KERNEL,
  491. "%s_clkdm", clkctrl_name);
  492. goto clkdm_found;
  493. }
  494. /*
  495. * The code below can be removed when all clkctrl nodes use domain
  496. * specific compatible proprerty and standard clock node naming
  497. */
  498. if (legacy_naming) {
  499. provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent);
  500. if (!provider->clkdm_name) {
  501. kfree(provider);
  502. return;
  503. }
  504. /*
  505. * Create default clkdm name, replace _cm from end of parent
  506. * node name with _clkdm
  507. */
  508. provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
  509. } else {
  510. provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFn", node);
  511. if (!provider->clkdm_name) {
  512. kfree(provider);
  513. return;
  514. }
  515. /*
  516. * Create default clkdm name, replace _clkctrl from end of
  517. * node name with _clkdm
  518. */
  519. provider->clkdm_name[strlen(provider->clkdm_name) - 7] = 0;
  520. }
  521. strcat(provider->clkdm_name, "clkdm");
  522. /* Replace any dash from the clkdm name with underscore */
  523. c = provider->clkdm_name;
  524. while (*c) {
  525. if (*c == '-')
  526. *c = '_';
  527. c++;
  528. }
  529. clkdm_found:
  530. INIT_LIST_HEAD(&provider->clocks);
  531. /* Generate clocks */
  532. reg_data = data->regs;
  533. while (reg_data->parent) {
  534. if ((reg_data->flags & CLKF_SOC_MASK) &&
  535. (reg_data->flags & soc_mask) == 0) {
  536. reg_data++;
  537. continue;
  538. }
  539. hw = kzalloc(sizeof(*hw), GFP_KERNEL);
  540. if (!hw)
  541. return;
  542. hw->enable_reg.ptr = provider->base + reg_data->offset;
  543. _ti_clkctrl_setup_subclks(provider, node, reg_data,
  544. hw->enable_reg.ptr, clkctrl_name);
  545. if (reg_data->flags & CLKF_SW_SUP)
  546. hw->enable_bit = MODULEMODE_SWCTRL;
  547. if (reg_data->flags & CLKF_HW_SUP)
  548. hw->enable_bit = MODULEMODE_HWCTRL;
  549. if (reg_data->flags & CLKF_NO_IDLEST)
  550. set_bit(NO_IDLEST, &hw->flags);
  551. if (reg_data->clkdm_name)
  552. hw->clkdm_name = reg_data->clkdm_name;
  553. else
  554. hw->clkdm_name = provider->clkdm_name;
  555. init.parent_names = &reg_data->parent;
  556. init.num_parents = 1;
  557. init.flags = 0;
  558. if (reg_data->flags & CLKF_SET_RATE_PARENT)
  559. init.flags |= CLK_SET_RATE_PARENT;
  560. init.name = clkctrl_get_clock_name(node, clkctrl_name,
  561. reg_data->offset, 0,
  562. legacy_naming);
  563. if (!init.name)
  564. goto cleanup;
  565. clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
  566. if (!clkctrl_clk)
  567. goto cleanup;
  568. init.ops = &omap4_clkctrl_clk_ops;
  569. hw->hw.init = &init;
  570. clk = ti_clk_register_omap_hw(NULL, &hw->hw, init.name);
  571. if (IS_ERR_OR_NULL(clk))
  572. goto cleanup;
  573. clkctrl_clk->reg_offset = reg_data->offset;
  574. clkctrl_clk->clk = &hw->hw;
  575. list_add(&clkctrl_clk->node, &provider->clocks);
  576. reg_data++;
  577. }
  578. ret = of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
  579. if (ret == -EPROBE_DEFER)
  580. ti_clk_retry_init(node, provider, _clkctrl_add_provider);
  581. kfree(clkctrl_name);
  582. return;
  583. cleanup:
  584. kfree(hw);
  585. kfree(init.name);
  586. kfree(clkctrl_name);
  587. kfree(clkctrl_clk);
  588. }
  589. CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
  590. _ti_omap4_clkctrl_setup);
  591. /**
  592. * ti_clk_is_in_standby - Check if clkctrl clock is in standby or not
  593. * @clk: clock to check standby status for
  594. *
  595. * Finds whether the provided clock is in standby mode or not. Returns
  596. * true if the provided clock is a clkctrl type clock and it is in standby,
  597. * false otherwise.
  598. */
  599. bool ti_clk_is_in_standby(struct clk *clk)
  600. {
  601. struct clk_hw *hw;
  602. struct clk_hw_omap *hwclk;
  603. u32 val;
  604. hw = __clk_get_hw(clk);
  605. if (!omap2_clk_is_hw_omap(hw))
  606. return false;
  607. hwclk = to_clk_hw_omap(hw);
  608. val = ti_clk_ll_ops->clk_readl(&hwclk->enable_reg);
  609. if (val & OMAP4_STBYST_MASK)
  610. return true;
  611. return false;
  612. }
  613. EXPORT_SYMBOL_GPL(ti_clk_is_in_standby);