clk-814x.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. #include <linux/kernel.h>
  3. #include <linux/clk.h>
  4. #include <linux/clk-provider.h>
  5. #include <linux/clk/ti.h>
  6. #include <linux/of_platform.h>
  7. #include <dt-bindings/clock/dm814.h>
  8. #include "clock.h"
  9. static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = {
  10. { DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" },
  11. { 0 },
  12. };
  13. static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = {
  14. { DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
  15. { DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
  16. { DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
  17. { DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
  18. { DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
  19. { DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
  20. { DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
  21. { DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
  22. { DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
  23. { DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
  24. { DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
  25. { DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
  26. { DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
  27. { DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
  28. { DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
  29. { DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
  30. { DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
  31. { DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
  32. { DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
  33. { DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
  34. { 0 },
  35. };
  36. static const struct
  37. omap_clkctrl_reg_data dm814_alwon_ethernet_clkctrl_regs[] __initconst = {
  38. { 0, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
  39. };
  40. const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
  41. { 0x48180500, dm814_default_clkctrl_regs },
  42. { 0x48181400, dm814_alwon_clkctrl_regs },
  43. { 0x481815d4, dm814_alwon_ethernet_clkctrl_regs },
  44. { 0 },
  45. };
  46. static struct ti_dt_clk dm814_clks[] = {
  47. DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
  48. { .node_name = NULL },
  49. };
  50. static bool timer_clocks_initialized;
  51. static int __init dm814x_adpll_early_init(void)
  52. {
  53. struct device_node *np;
  54. if (!timer_clocks_initialized)
  55. return -ENODEV;
  56. np = of_find_node_by_name(NULL, "pllss");
  57. if (!np) {
  58. pr_err("Could not find node for plls\n");
  59. return -ENODEV;
  60. }
  61. of_platform_populate(np, NULL, NULL, NULL);
  62. of_node_put(np);
  63. return 0;
  64. }
  65. core_initcall(dm814x_adpll_early_init);
  66. static const char * const init_clocks[] = {
  67. "pll040clkout", /* MPU 481c5040.adpll.clkout */
  68. "pll290clkout", /* DDR 481c5290.adpll.clkout */
  69. };
  70. static int __init dm814x_adpll_enable_init_clocks(void)
  71. {
  72. int i, err;
  73. if (!timer_clocks_initialized)
  74. return -ENODEV;
  75. for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
  76. struct clk *clock;
  77. clock = clk_get(NULL, init_clocks[i]);
  78. if (WARN(IS_ERR(clock), "could not find init clock %s\n",
  79. init_clocks[i]))
  80. continue;
  81. err = clk_prepare_enable(clock);
  82. if (WARN(err, "could not enable init clock %s\n",
  83. init_clocks[i]))
  84. continue;
  85. }
  86. return 0;
  87. }
  88. postcore_initcall(dm814x_adpll_enable_init_clocks);
  89. int __init dm814x_dt_clk_init(void)
  90. {
  91. ti_dt_clocks_register(dm814_clks);
  92. omap2_clk_disable_autoidle_all();
  93. ti_clk_add_aliases();
  94. omap2_clk_enable_init_clocks(NULL, 0);
  95. timer_clocks_initialized = true;
  96. return 0;
  97. }