clk-43xx.c 12 KB

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  1. /*
  2. * AM43XX Clock init
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc
  5. * Tero Kristo (t-kristo@ti.com)
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/list.h>
  18. #include <linux/clk.h>
  19. #include <linux/clk-provider.h>
  20. #include <linux/clk/ti.h>
  21. #include <dt-bindings/clock/am4.h>
  22. #include "clock.h"
  23. static const struct omap_clkctrl_reg_data am4_l3s_tsc_clkctrl_regs[] __initconst = {
  24. { AM4_L3S_TSC_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
  25. { 0 },
  26. };
  27. static const char * const am4_synctimer_32kclk_parents[] __initconst = {
  28. "mux_synctimer32k_ck",
  29. NULL,
  30. };
  31. static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
  32. { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
  33. { 0 },
  34. };
  35. static const struct omap_clkctrl_reg_data am4_l4_wkup_aon_clkctrl_regs[] __initconst = {
  36. { AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sys_clkin_ck" },
  37. { AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl:0008:8" },
  38. { 0 },
  39. };
  40. static const char * const am4_gpio0_dbclk_parents[] __initconst = {
  41. "gpio0_dbclk_mux_ck",
  42. NULL,
  43. };
  44. static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
  45. { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
  46. { 0 },
  47. };
  48. static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
  49. { AM4_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
  50. { AM4_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
  51. { AM4_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
  52. { AM4_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
  53. { AM4_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
  54. { AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
  55. { AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
  56. { AM4_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
  57. { AM4_L4_WKUP_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck" },
  58. { 0 },
  59. };
  60. static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
  61. { AM4_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
  62. { 0 },
  63. };
  64. static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
  65. { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
  66. { 0 },
  67. };
  68. static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
  69. { AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ick" },
  70. { 0 },
  71. };
  72. static const struct omap_clkctrl_reg_data am4_l3_clkctrl_regs[] __initconst = {
  73. { AM4_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  74. { AM4_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
  75. { AM4_L3_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  76. { AM4_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  77. { AM4_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  78. { AM4_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  79. { AM4_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  80. { AM4_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  81. { AM4_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  82. { AM4_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  83. { AM4_L3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
  84. { 0 },
  85. };
  86. static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
  87. "dpll_per_clkdcoldo",
  88. NULL,
  89. };
  90. static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
  91. { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
  92. { 0 },
  93. };
  94. static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
  95. { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
  96. { 0 },
  97. };
  98. static const struct omap_clkctrl_reg_data am4_l3s_clkctrl_regs[] __initconst = {
  99. { AM4_L3S_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  100. { AM4_L3S_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  101. { AM4_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
  102. { AM4_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
  103. { AM4_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
  104. { AM4_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  105. { AM4_L3S_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
  106. { AM4_L3S_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk" },
  107. { AM4_L3S_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk" },
  108. { 0 },
  109. };
  110. static const struct omap_clkctrl_reg_data am4_pruss_ocp_clkctrl_regs[] __initconst = {
  111. { AM4_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" },
  112. { 0 },
  113. };
  114. static const char * const am4_gpio1_dbclk_parents[] __initconst = {
  115. "clkdiv32k_ick",
  116. NULL,
  117. };
  118. static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
  119. { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
  120. { 0 },
  121. };
  122. static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
  123. { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
  124. { 0 },
  125. };
  126. static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
  127. { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
  128. { 0 },
  129. };
  130. static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
  131. { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
  132. { 0 },
  133. };
  134. static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
  135. { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
  136. { 0 },
  137. };
  138. static const struct omap_clkctrl_reg_data am4_l4ls_clkctrl_regs[] __initconst = {
  139. { AM4_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  140. { AM4_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
  141. { AM4_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
  142. { AM4_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  143. { AM4_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  144. { AM4_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  145. { AM4_L4LS_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  146. { AM4_L4LS_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  147. { AM4_L4LS_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  148. { AM4_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  149. { AM4_L4LS_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  150. { AM4_L4LS_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  151. { AM4_L4LS_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  152. { AM4_L4LS_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  153. { AM4_L4LS_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  154. { AM4_L4LS_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
  155. { AM4_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  156. { AM4_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  157. { AM4_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  158. { AM4_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  159. { AM4_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  160. { AM4_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
  161. { AM4_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  162. { AM4_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  163. { AM4_L4LS_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  164. { AM4_L4LS_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  165. { AM4_L4LS_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  166. { AM4_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  167. { AM4_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
  168. { AM4_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
  169. { AM4_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
  170. { AM4_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
  171. { AM4_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
  172. { AM4_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
  173. { AM4_L4LS_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
  174. { AM4_L4LS_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
  175. { AM4_L4LS_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
  176. { AM4_L4LS_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
  177. { AM4_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  178. { AM4_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  179. { AM4_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  180. { AM4_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  181. { AM4_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  182. { AM4_L4LS_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  183. { AM4_L4LS_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  184. { 0 },
  185. };
  186. static const struct omap_clkctrl_reg_data am4_emif_clkctrl_regs[] __initconst = {
  187. { AM4_EMIF_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck" },
  188. { 0 },
  189. };
  190. static const struct omap_clkctrl_reg_data am4_dss_clkctrl_regs[] __initconst = {
  191. { AM4_DSS_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk" },
  192. { 0 },
  193. };
  194. static const struct omap_clkctrl_reg_data am4_cpsw_125mhz_clkctrl_regs[] __initconst = {
  195. { AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
  196. { 0 },
  197. };
  198. const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
  199. { 0x44df2920, am4_l3s_tsc_clkctrl_regs },
  200. { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
  201. { 0x44df2a20, am4_l4_wkup_clkctrl_regs },
  202. { 0x44df8320, am4_mpu_clkctrl_regs },
  203. { 0x44df8420, am4_gfx_l3_clkctrl_regs },
  204. { 0x44df8520, am4_l4_rtc_clkctrl_regs },
  205. { 0x44df8820, am4_l3_clkctrl_regs },
  206. { 0x44df8868, am4_l3s_clkctrl_regs },
  207. { 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
  208. { 0x44df8c20, am4_l4ls_clkctrl_regs },
  209. { 0x44df8f20, am4_emif_clkctrl_regs },
  210. { 0x44df9220, am4_dss_clkctrl_regs },
  211. { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
  212. { 0 },
  213. };
  214. const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = {
  215. { 0x44df2920, am4_l3s_tsc_clkctrl_regs },
  216. { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
  217. { 0x44df2a20, am4_l4_wkup_clkctrl_regs },
  218. { 0x44df8320, am4_mpu_clkctrl_regs },
  219. { 0x44df8420, am4_gfx_l3_clkctrl_regs },
  220. { 0x44df8820, am4_l3_clkctrl_regs },
  221. { 0x44df8868, am4_l3s_clkctrl_regs },
  222. { 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
  223. { 0x44df8c20, am4_l4ls_clkctrl_regs },
  224. { 0x44df8f20, am4_emif_clkctrl_regs },
  225. { 0x44df9220, am4_dss_clkctrl_regs },
  226. { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
  227. { 0 },
  228. };
  229. static struct ti_dt_clk am43xx_clks[] = {
  230. DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
  231. DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
  232. DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"),
  233. DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"),
  234. DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"),
  235. DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"),
  236. DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"),
  237. DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"),
  238. DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"),
  239. DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"),
  240. DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"),
  241. { .node_name = NULL },
  242. };
  243. int __init am43xx_dt_clk_init(void)
  244. {
  245. struct clk *clk1, *clk2;
  246. if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
  247. ti_dt_clocks_register(am43xx_compat_clks);
  248. else
  249. ti_dt_clocks_register(am43xx_clks);
  250. omap2_clk_disable_autoidle_all();
  251. ti_clk_add_aliases();
  252. /*
  253. * cpsw_cpts_rft_clk has got the choice of 3 clocksources
  254. * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
  255. * By default dpll_core_m4_ck is selected, witn this as clock
  256. * source the CPTS doesnot work properly. It gives clockcheck errors
  257. * while running PTP.
  258. * clockcheck: clock jumped backward or running slower than expected!
  259. * By selecting dpll_core_m5_ck as the clocksource fixes this issue.
  260. * In AM335x dpll_core_m5_ck is the default clocksource.
  261. */
  262. clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");
  263. clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");
  264. clk_set_parent(clk1, clk2);
  265. return 0;
  266. }