clk-3xxx.c 12 KB

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  1. /*
  2. * OMAP3 Clock init
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc
  5. * Tero Kristo (t-kristo@ti.com)
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/list.h>
  18. #include <linux/clk.h>
  19. #include <linux/clk-provider.h>
  20. #include <linux/clk/ti.h>
  21. #include "clock.h"
  22. #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
  23. #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5
  24. #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
  25. #define OMAP34XX_CM_IDLEST_VAL 1
  26. /*
  27. * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported
  28. * in the same register at a bit offset of 0x8. The EN_ACK for ICK is
  29. * at an offset of 4 from ICK enable bit.
  30. */
  31. #define AM35XX_IPSS_ICK_MASK 0xF
  32. #define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4
  33. #define AM35XX_IPSS_ICK_FCK_OFFSET 0x8
  34. #define AM35XX_IPSS_CLK_IDLEST_VAL 0
  35. #define AM35XX_ST_IPSS_SHIFT 5
  36. /**
  37. * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
  38. * @clk: struct clk * being enabled
  39. * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  40. * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  41. * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
  42. *
  43. * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
  44. * from the CM_{I,F}CLKEN bit. Pass back the correct info via
  45. * @idlest_reg and @idlest_bit. No return value.
  46. */
  47. static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk,
  48. struct clk_omap_reg *idlest_reg,
  49. u8 *idlest_bit,
  50. u8 *idlest_val)
  51. {
  52. memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
  53. idlest_reg->offset &= ~0xf0;
  54. idlest_reg->offset |= 0x20;
  55. *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
  56. *idlest_val = OMAP34XX_CM_IDLEST_VAL;
  57. }
  58. const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = {
  59. .allow_idle = omap2_clkt_iclk_allow_idle,
  60. .deny_idle = omap2_clkt_iclk_deny_idle,
  61. .find_idlest = omap3430es2_clk_ssi_find_idlest,
  62. .find_companion = omap2_clk_dflt_find_companion,
  63. };
  64. /**
  65. * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
  66. * @clk: struct clk * being enabled
  67. * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  68. * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  69. * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
  70. *
  71. * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
  72. * target IDLEST bits. For our purposes, we are concerned with the
  73. * target IDLEST bits, which exist at a different bit position than
  74. * the *CLKEN bit position for these modules (DSS and USBHOST) (The
  75. * default find_idlest code assumes that they are at the same
  76. * position.) No return value.
  77. */
  78. static void
  79. omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk,
  80. struct clk_omap_reg *idlest_reg,
  81. u8 *idlest_bit, u8 *idlest_val)
  82. {
  83. memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
  84. idlest_reg->offset &= ~0xf0;
  85. idlest_reg->offset |= 0x20;
  86. /* USBHOST_IDLE has same shift */
  87. *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
  88. *idlest_val = OMAP34XX_CM_IDLEST_VAL;
  89. }
  90. const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = {
  91. .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
  92. .find_companion = omap2_clk_dflt_find_companion,
  93. };
  94. const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = {
  95. .allow_idle = omap2_clkt_iclk_allow_idle,
  96. .deny_idle = omap2_clkt_iclk_deny_idle,
  97. .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
  98. .find_companion = omap2_clk_dflt_find_companion,
  99. };
  100. /**
  101. * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
  102. * @clk: struct clk * being enabled
  103. * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  104. * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  105. * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
  106. *
  107. * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
  108. * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
  109. * @idlest_reg and @idlest_bit. No return value.
  110. */
  111. static void
  112. omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk,
  113. struct clk_omap_reg *idlest_reg,
  114. u8 *idlest_bit,
  115. u8 *idlest_val)
  116. {
  117. memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
  118. idlest_reg->offset &= ~0xf0;
  119. idlest_reg->offset |= 0x20;
  120. *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
  121. *idlest_val = OMAP34XX_CM_IDLEST_VAL;
  122. }
  123. const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = {
  124. .allow_idle = omap2_clkt_iclk_allow_idle,
  125. .deny_idle = omap2_clkt_iclk_deny_idle,
  126. .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
  127. .find_companion = omap2_clk_dflt_find_companion,
  128. };
  129. /**
  130. * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS
  131. * @clk: struct clk * being enabled
  132. * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  133. * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  134. * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
  135. *
  136. * The interface clocks on AM35xx IPSS reflects the clock idle status
  137. * in the enable register itsel at a bit offset of 4 from the enable
  138. * bit. A value of 1 indicates that clock is enabled.
  139. */
  140. static void am35xx_clk_find_idlest(struct clk_hw_omap *clk,
  141. struct clk_omap_reg *idlest_reg,
  142. u8 *idlest_bit,
  143. u8 *idlest_val)
  144. {
  145. memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
  146. *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET;
  147. *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL;
  148. }
  149. /**
  150. * am35xx_clk_find_companion - find companion clock to @clk
  151. * @clk: struct clk * to find the companion clock of
  152. * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
  153. * @other_bit: u8 ** to return the companion clock bit shift in
  154. *
  155. * Some clocks don't have companion clocks. For example, modules with
  156. * only an interface clock (such as HECC) don't have a companion
  157. * clock. Right now, this code relies on the hardware exporting a bit
  158. * in the correct companion register that indicates that the
  159. * nonexistent 'companion clock' is active. Future patches will
  160. * associate this type of code with per-module data structures to
  161. * avoid this issue, and remove the casts. No return value.
  162. */
  163. static void am35xx_clk_find_companion(struct clk_hw_omap *clk,
  164. struct clk_omap_reg *other_reg,
  165. u8 *other_bit)
  166. {
  167. memcpy(other_reg, &clk->enable_reg, sizeof(*other_reg));
  168. if (clk->enable_bit & AM35XX_IPSS_ICK_MASK)
  169. *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET;
  170. else
  171. *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET;
  172. }
  173. const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = {
  174. .find_idlest = am35xx_clk_find_idlest,
  175. .find_companion = am35xx_clk_find_companion,
  176. };
  177. /**
  178. * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS
  179. * @clk: struct clk * being enabled
  180. * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  181. * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  182. * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
  183. *
  184. * The IPSS target CM_IDLEST bit is at a different shift from the
  185. * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg
  186. * and @idlest_bit. No return value.
  187. */
  188. static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk,
  189. struct clk_omap_reg *idlest_reg,
  190. u8 *idlest_bit,
  191. u8 *idlest_val)
  192. {
  193. memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
  194. idlest_reg->offset &= ~0xf0;
  195. idlest_reg->offset |= 0x20;
  196. *idlest_bit = AM35XX_ST_IPSS_SHIFT;
  197. *idlest_val = OMAP34XX_CM_IDLEST_VAL;
  198. }
  199. const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
  200. .allow_idle = omap2_clkt_iclk_allow_idle,
  201. .deny_idle = omap2_clkt_iclk_deny_idle,
  202. .find_idlest = am35xx_clk_ipss_find_idlest,
  203. .find_companion = omap2_clk_dflt_find_companion,
  204. };
  205. static struct ti_dt_clk omap3xxx_clks[] = {
  206. DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
  207. DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
  208. { .node_name = NULL },
  209. };
  210. static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
  211. DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
  212. DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
  213. DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
  214. DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
  215. { .node_name = NULL },
  216. };
  217. static struct ti_dt_clk omap3430es1_clks[] = {
  218. DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
  219. DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
  220. DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
  221. DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
  222. DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
  223. DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
  224. { .node_name = NULL },
  225. };
  226. static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
  227. DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
  228. DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
  229. { .node_name = NULL },
  230. };
  231. static struct ti_dt_clk am35xx_clks[] = {
  232. DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
  233. DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
  234. DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
  235. DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
  236. { .node_name = NULL },
  237. };
  238. static const char *enable_init_clks[] = {
  239. "sdrc_ick",
  240. "gpmc_fck",
  241. "omapctrl_ick",
  242. };
  243. enum {
  244. OMAP3_SOC_AM35XX,
  245. OMAP3_SOC_OMAP3430_ES1,
  246. OMAP3_SOC_OMAP3430_ES2_PLUS,
  247. OMAP3_SOC_OMAP3630,
  248. };
  249. /**
  250. * omap3_clk_lock_dpll5 - locks DPLL5
  251. *
  252. * Locks DPLL5 to a pre-defined frequency. This is required for proper
  253. * operation of USB.
  254. */
  255. void __init omap3_clk_lock_dpll5(void)
  256. {
  257. struct clk *dpll5_clk;
  258. struct clk *dpll5_m2_clk;
  259. /*
  260. * Errata sprz319f advisory 2.1 documents a USB host clock drift issue
  261. * that can be worked around using specially crafted dpll5 settings
  262. * with a dpll5_m2 divider set to 8. Set the dpll5 rate to 8x the USB
  263. * host clock rate, its .set_rate handler() will detect that frequency
  264. * and use the errata settings.
  265. */
  266. dpll5_clk = clk_get(NULL, "dpll5_ck");
  267. clk_set_rate(dpll5_clk, OMAP3_DPLL5_FREQ_FOR_USBHOST * 8);
  268. clk_prepare_enable(dpll5_clk);
  269. /* Program dpll5_m2_clk divider */
  270. dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
  271. clk_prepare_enable(dpll5_m2_clk);
  272. clk_set_rate(dpll5_m2_clk, OMAP3_DPLL5_FREQ_FOR_USBHOST);
  273. clk_disable_unprepare(dpll5_m2_clk);
  274. clk_disable_unprepare(dpll5_clk);
  275. }
  276. static int __init omap3xxx_dt_clk_init(int soc_type)
  277. {
  278. if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
  279. soc_type == OMAP3_SOC_OMAP3430_ES1 ||
  280. soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
  281. ti_dt_clocks_register(omap3xxx_clks);
  282. if (soc_type == OMAP3_SOC_AM35XX)
  283. ti_dt_clocks_register(am35xx_clks);
  284. if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
  285. soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
  286. ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
  287. if (soc_type == OMAP3_SOC_OMAP3430_ES1)
  288. ti_dt_clocks_register(omap3430es1_clks);
  289. if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
  290. soc_type == OMAP3_SOC_OMAP3630)
  291. ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
  292. omap2_clk_disable_autoidle_all();
  293. ti_clk_add_aliases();
  294. omap2_clk_enable_init_clocks(enable_init_clks,
  295. ARRAY_SIZE(enable_init_clks));
  296. pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
  297. (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
  298. (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
  299. (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
  300. (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
  301. if (soc_type != OMAP3_SOC_OMAP3430_ES1)
  302. omap3_clk_lock_dpll5();
  303. return 0;
  304. }
  305. int __init omap3430_dt_clk_init(void)
  306. {
  307. return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
  308. }
  309. int __init omap3630_dt_clk_init(void)
  310. {
  311. return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630);
  312. }
  313. int __init am35xx_dt_clk_init(void)
  314. {
  315. return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX);
  316. }