clk-33xx.c 12 KB

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  1. /*
  2. * AM33XX Clock init
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc
  5. * Tero Kristo (t-kristo@ti.com)
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/list.h>
  18. #include <linux/clk.h>
  19. #include <linux/clk-provider.h>
  20. #include <linux/clk/ti.h>
  21. #include <dt-bindings/clock/am3.h>
  22. #include "clock.h"
  23. static const char * const am3_gpio1_dbclk_parents[] __initconst = {
  24. "clk-24mhz-clkctrl:0000:0",
  25. NULL,
  26. };
  27. static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
  28. { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
  29. { 0 },
  30. };
  31. static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
  32. { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
  33. { 0 },
  34. };
  35. static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
  36. { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
  37. { 0 },
  38. };
  39. static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = {
  40. { AM3_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  41. { AM3_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  42. { AM3_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  43. { AM3_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  44. { AM3_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  45. { AM3_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  46. { AM3_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  47. { AM3_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  48. { AM3_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  49. { AM3_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  50. { AM3_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  51. { AM3_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  52. { AM3_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
  53. { AM3_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
  54. { AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
  55. { AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
  56. { AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
  57. { AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  58. { AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  59. { AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  60. { AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
  61. { AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
  62. { AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  63. { AM3_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  64. { AM3_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  65. { AM3_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
  66. { AM3_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
  67. { AM3_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  68. { AM3_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  69. { AM3_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  70. { AM3_L4LS_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  71. { 0 },
  72. };
  73. static const struct omap_clkctrl_reg_data am3_l3s_clkctrl_regs[] __initconst = {
  74. { AM3_L3S_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck" },
  75. { AM3_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
  76. { AM3_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
  77. { AM3_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
  78. { AM3_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  79. { 0 },
  80. };
  81. static const struct omap_clkctrl_reg_data am3_l3_clkctrl_regs[] __initconst = {
  82. { AM3_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  83. { AM3_L3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck" },
  84. { AM3_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  85. { AM3_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
  86. { AM3_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  87. { AM3_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  88. { AM3_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  89. { AM3_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  90. { AM3_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  91. { AM3_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  92. { 0 },
  93. };
  94. static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = {
  95. { AM3_L4HS_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
  96. { 0 },
  97. };
  98. static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = {
  99. { AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" },
  100. { 0 },
  101. };
  102. static const struct omap_clkctrl_reg_data am3_cpsw_125mhz_clkctrl_regs[] __initconst = {
  103. { AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
  104. { 0 },
  105. };
  106. static const struct omap_clkctrl_reg_data am3_lcdc_clkctrl_regs[] __initconst = {
  107. { AM3_LCDC_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk" },
  108. { 0 },
  109. };
  110. static const struct omap_clkctrl_reg_data am3_clk_24mhz_clkctrl_regs[] __initconst = {
  111. { AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck" },
  112. { 0 },
  113. };
  114. static const char * const am3_gpio0_dbclk_parents[] __initconst = {
  115. "gpio0_dbclk_mux_ck",
  116. NULL,
  117. };
  118. static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
  119. { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
  120. { 0 },
  121. };
  122. static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
  123. { AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
  124. { AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
  125. { AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
  126. { AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
  127. { AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
  128. { AM3_L4_WKUP_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
  129. { AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
  130. { AM3_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
  131. { AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
  132. { AM3_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
  133. { 0 },
  134. };
  135. static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
  136. "sys_clkin_ck",
  137. NULL,
  138. };
  139. static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
  140. "l3-aon-clkctrl:0000:19",
  141. "l3-aon-clkctrl:0000:30",
  142. NULL,
  143. };
  144. static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
  145. "l3-aon-clkctrl:0000:20",
  146. NULL,
  147. };
  148. static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
  149. .max_div = 64,
  150. .flags = CLK_DIVIDER_POWER_OF_TWO,
  151. };
  152. static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
  153. "l3-aon-clkctrl:0000:22",
  154. NULL,
  155. };
  156. static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
  157. .max_div = 64,
  158. .flags = CLK_DIVIDER_POWER_OF_TWO,
  159. };
  160. static const char * const am3_dbg_clka_ck_parents[] __initconst = {
  161. "dpll_core_m4_ck",
  162. NULL,
  163. };
  164. static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
  165. { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
  166. { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
  167. { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
  168. { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
  169. { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
  170. { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
  171. { 0 },
  172. };
  173. static const struct omap_clkctrl_reg_data am3_l3_aon_clkctrl_regs[] __initconst = {
  174. { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
  175. { 0 },
  176. };
  177. static const struct omap_clkctrl_reg_data am3_l4_wkup_aon_clkctrl_regs[] __initconst = {
  178. { AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck" },
  179. { 0 },
  180. };
  181. static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
  182. { AM3_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
  183. { 0 },
  184. };
  185. static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
  186. { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" },
  187. { 0 },
  188. };
  189. static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
  190. { AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
  191. { 0 },
  192. };
  193. static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
  194. { AM3_L4_CEFUSE_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
  195. { 0 },
  196. };
  197. const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
  198. { 0x44e00038, am3_l4ls_clkctrl_regs },
  199. { 0x44e0001c, am3_l3s_clkctrl_regs },
  200. { 0x44e00024, am3_l3_clkctrl_regs },
  201. { 0x44e00120, am3_l4hs_clkctrl_regs },
  202. { 0x44e000e8, am3_pruss_ocp_clkctrl_regs },
  203. { 0x44e00000, am3_cpsw_125mhz_clkctrl_regs },
  204. { 0x44e00018, am3_lcdc_clkctrl_regs },
  205. { 0x44e0014c, am3_clk_24mhz_clkctrl_regs },
  206. { 0x44e00400, am3_l4_wkup_clkctrl_regs },
  207. { 0x44e00414, am3_l3_aon_clkctrl_regs },
  208. { 0x44e004b0, am3_l4_wkup_aon_clkctrl_regs },
  209. { 0x44e00600, am3_mpu_clkctrl_regs },
  210. { 0x44e00800, am3_l4_rtc_clkctrl_regs },
  211. { 0x44e00900, am3_gfx_l3_clkctrl_regs },
  212. { 0x44e00a00, am3_l4_cefuse_clkctrl_regs },
  213. { 0 },
  214. };
  215. static struct ti_dt_clk am33xx_clks[] = {
  216. DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
  217. DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
  218. DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
  219. DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
  220. DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
  221. DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0008:18"),
  222. DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0074:18"),
  223. DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0078:18"),
  224. DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:007c:18"),
  225. DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
  226. DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
  227. DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
  228. DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l3-aon-clkctrl:0000:20"),
  229. { .node_name = NULL },
  230. };
  231. static const char *enable_init_clks[] = {
  232. "dpll_ddr_m2_ck",
  233. "dpll_mpu_m2_ck",
  234. "l3_gclk",
  235. "l4hs_gclk",
  236. "l4fw_gclk",
  237. "l4ls_gclk",
  238. /* Required for external peripherals like, Audio codecs */
  239. "clkout2_ck",
  240. };
  241. int __init am33xx_dt_clk_init(void)
  242. {
  243. struct clk *clk1, *clk2;
  244. if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
  245. ti_dt_clocks_register(am33xx_compat_clks);
  246. else
  247. ti_dt_clocks_register(am33xx_clks);
  248. omap2_clk_disable_autoidle_all();
  249. ti_clk_add_aliases();
  250. omap2_clk_enable_init_clocks(enable_init_clks,
  251. ARRAY_SIZE(enable_init_clks));
  252. /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
  253. * physically present, in such a case HWMOD enabling of
  254. * clock would be failure with default parent. And timer
  255. * probe thinks clock is already enabled, this leads to
  256. * crash upon accessing timer 3 & 6 registers in probe.
  257. * Fix by setting parent of both these timers to master
  258. * oscillator clock.
  259. */
  260. clk1 = clk_get_sys(NULL, "sys_clkin_ck");
  261. clk2 = clk_get_sys(NULL, "timer3_fck");
  262. clk_set_parent(clk2, clk1);
  263. clk2 = clk_get_sys(NULL, "timer6_fck");
  264. clk_set_parent(clk2, clk1);
  265. /*
  266. * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
  267. * the design/spec, so as a result, for example, timer which supposed
  268. * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
  269. * not expected by any use-case, so change WDT1 clock source to PRCM
  270. * 32KHz clock.
  271. */
  272. clk1 = clk_get_sys(NULL, "wdt1_fck");
  273. clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
  274. clk_set_parent(clk1, clk2);
  275. return 0;
  276. }