clk-33xx-compat.c 8.7 KB

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  1. /*
  2. * AM33XX Clock init
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc
  5. * Tero Kristo (t-kristo@ti.com)
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/list.h>
  18. #include <linux/clk.h>
  19. #include <linux/clk-provider.h>
  20. #include <linux/clk/ti.h>
  21. #include <dt-bindings/clock/am3.h>
  22. #include "clock.h"
  23. static const char * const am3_gpio1_dbclk_parents[] __initconst = {
  24. "l4_per_cm:clk:0138:0",
  25. NULL,
  26. };
  27. static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
  28. { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
  29. { 0 },
  30. };
  31. static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
  32. { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
  33. { 0 },
  34. };
  35. static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
  36. { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
  37. { 0 },
  38. };
  39. static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
  40. { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
  41. { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },
  42. { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
  43. { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  44. { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
  45. { AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  46. { AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
  47. { AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
  48. { AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  49. { AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  50. { AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  51. { AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  52. { AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  53. { AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  54. { AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  55. { AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  56. { AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
  57. { AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  58. { AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  59. { AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  60. { AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  61. { AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
  62. { AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
  63. { AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
  64. { AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
  65. { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
  66. { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
  67. { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  68. { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  69. { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  70. { AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  71. { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  72. { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
  73. { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
  74. { AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  75. { AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  76. { AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  77. { AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  78. { AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  79. { AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
  80. { AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
  81. { AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
  82. { AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  83. { AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
  84. { AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  85. { AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
  86. { AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  87. { AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  88. { AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
  89. { AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  90. { AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
  91. { 0 },
  92. };
  93. static const char * const am3_gpio0_dbclk_parents[] __initconst = {
  94. "gpio0_dbclk_mux_ck",
  95. NULL,
  96. };
  97. static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
  98. { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
  99. { 0 },
  100. };
  101. static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
  102. "sys_clkin_ck",
  103. NULL,
  104. };
  105. static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
  106. "l4_wkup_cm:clk:0010:19",
  107. "l4_wkup_cm:clk:0010:30",
  108. NULL,
  109. };
  110. static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
  111. "l4_wkup_cm:clk:0010:20",
  112. NULL,
  113. };
  114. static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
  115. .max_div = 64,
  116. .flags = CLK_DIVIDER_POWER_OF_TWO,
  117. };
  118. static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
  119. "l4_wkup_cm:clk:0010:22",
  120. NULL,
  121. };
  122. static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
  123. .max_div = 64,
  124. .flags = CLK_DIVIDER_POWER_OF_TWO,
  125. };
  126. static const char * const am3_dbg_clka_ck_parents[] __initconst = {
  127. "dpll_core_m4_ck",
  128. NULL,
  129. };
  130. static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
  131. { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
  132. { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
  133. { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
  134. { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
  135. { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
  136. { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
  137. { 0 },
  138. };
  139. static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
  140. { AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
  141. { AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
  142. { AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
  143. { AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
  144. { AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
  145. { AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
  146. { AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
  147. { AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
  148. { AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
  149. { AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
  150. { AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
  151. { AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
  152. { 0 },
  153. };
  154. static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
  155. { AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
  156. { 0 },
  157. };
  158. static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
  159. { AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
  160. { 0 },
  161. };
  162. static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
  163. { AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
  164. { 0 },
  165. };
  166. static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
  167. { AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
  168. { 0 },
  169. };
  170. const struct omap_clkctrl_data am3_clkctrl_compat_data[] __initconst = {
  171. { 0x44e00014, am3_l4_per_clkctrl_regs },
  172. { 0x44e00404, am3_l4_wkup_clkctrl_regs },
  173. { 0x44e00604, am3_mpu_clkctrl_regs },
  174. { 0x44e00800, am3_l4_rtc_clkctrl_regs },
  175. { 0x44e00904, am3_gfx_l3_clkctrl_regs },
  176. { 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
  177. { 0 },
  178. };
  179. struct ti_dt_clk am33xx_compat_clks[] = {
  180. DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
  181. DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
  182. DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
  183. DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
  184. DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
  185. DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
  186. DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
  187. DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
  188. DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
  189. DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
  190. DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
  191. DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
  192. DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
  193. { .node_name = NULL },
  194. };