apll.c 9.5 KB

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  1. /*
  2. * OMAP APLL clock support
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc.
  5. *
  6. * J Keerthy <j-keerthy@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/clk.h>
  18. #include <linux/clk-provider.h>
  19. #include <linux/module.h>
  20. #include <linux/slab.h>
  21. #include <linux/io.h>
  22. #include <linux/err.h>
  23. #include <linux/string.h>
  24. #include <linux/log2.h>
  25. #include <linux/of.h>
  26. #include <linux/of_address.h>
  27. #include <linux/clk/ti.h>
  28. #include <linux/delay.h>
  29. #include "clock.h"
  30. #define APLL_FORCE_LOCK 0x1
  31. #define APLL_AUTO_IDLE 0x2
  32. #define MAX_APLL_WAIT_TRIES 1000000
  33. #undef pr_fmt
  34. #define pr_fmt(fmt) "%s: " fmt, __func__
  35. static int dra7_apll_enable(struct clk_hw *hw)
  36. {
  37. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  38. int r = 0, i = 0;
  39. struct dpll_data *ad;
  40. const char *clk_name;
  41. u8 state = 1;
  42. u32 v;
  43. ad = clk->dpll_data;
  44. if (!ad)
  45. return -EINVAL;
  46. clk_name = clk_hw_get_name(&clk->hw);
  47. state <<= __ffs(ad->idlest_mask);
  48. /* Check is already locked */
  49. v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
  50. if ((v & ad->idlest_mask) == state)
  51. return r;
  52. v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
  53. v &= ~ad->enable_mask;
  54. v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
  55. ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
  56. state <<= __ffs(ad->idlest_mask);
  57. while (1) {
  58. v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
  59. if ((v & ad->idlest_mask) == state)
  60. break;
  61. if (i > MAX_APLL_WAIT_TRIES)
  62. break;
  63. i++;
  64. udelay(1);
  65. }
  66. if (i == MAX_APLL_WAIT_TRIES) {
  67. pr_warn("clock: %s failed transition to '%s'\n",
  68. clk_name, (state) ? "locked" : "bypassed");
  69. r = -EBUSY;
  70. } else
  71. pr_debug("clock: %s transition to '%s' in %d loops\n",
  72. clk_name, (state) ? "locked" : "bypassed", i);
  73. return r;
  74. }
  75. static void dra7_apll_disable(struct clk_hw *hw)
  76. {
  77. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  78. struct dpll_data *ad;
  79. u8 state = 1;
  80. u32 v;
  81. ad = clk->dpll_data;
  82. state <<= __ffs(ad->idlest_mask);
  83. v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
  84. v &= ~ad->enable_mask;
  85. v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
  86. ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
  87. }
  88. static int dra7_apll_is_enabled(struct clk_hw *hw)
  89. {
  90. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  91. struct dpll_data *ad;
  92. u32 v;
  93. ad = clk->dpll_data;
  94. v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
  95. v &= ad->enable_mask;
  96. v >>= __ffs(ad->enable_mask);
  97. return v == APLL_AUTO_IDLE ? 0 : 1;
  98. }
  99. static u8 dra7_init_apll_parent(struct clk_hw *hw)
  100. {
  101. return 0;
  102. }
  103. static const struct clk_ops apll_ck_ops = {
  104. .enable = &dra7_apll_enable,
  105. .disable = &dra7_apll_disable,
  106. .is_enabled = &dra7_apll_is_enabled,
  107. .get_parent = &dra7_init_apll_parent,
  108. };
  109. static void __init omap_clk_register_apll(void *user,
  110. struct device_node *node)
  111. {
  112. struct clk_hw *hw = user;
  113. struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
  114. struct dpll_data *ad = clk_hw->dpll_data;
  115. struct clk *clk;
  116. const struct clk_init_data *init = clk_hw->hw.init;
  117. clk = of_clk_get(node, 0);
  118. if (IS_ERR(clk)) {
  119. pr_debug("clk-ref for %pOFn not ready, retry\n",
  120. node);
  121. if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
  122. return;
  123. goto cleanup;
  124. }
  125. ad->clk_ref = __clk_get_hw(clk);
  126. clk = of_clk_get(node, 1);
  127. if (IS_ERR(clk)) {
  128. pr_debug("clk-bypass for %pOFn not ready, retry\n",
  129. node);
  130. if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
  131. return;
  132. goto cleanup;
  133. }
  134. ad->clk_bypass = __clk_get_hw(clk);
  135. clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);
  136. if (!IS_ERR(clk)) {
  137. of_clk_add_provider(node, of_clk_src_simple_get, clk);
  138. kfree(init->parent_names);
  139. kfree(init);
  140. return;
  141. }
  142. cleanup:
  143. kfree(clk_hw->dpll_data);
  144. kfree(init->parent_names);
  145. kfree(init);
  146. kfree(clk_hw);
  147. }
  148. static void __init of_dra7_apll_setup(struct device_node *node)
  149. {
  150. struct dpll_data *ad = NULL;
  151. struct clk_hw_omap *clk_hw = NULL;
  152. struct clk_init_data *init = NULL;
  153. const char **parent_names = NULL;
  154. int ret;
  155. ad = kzalloc(sizeof(*ad), GFP_KERNEL);
  156. clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
  157. init = kzalloc(sizeof(*init), GFP_KERNEL);
  158. if (!ad || !clk_hw || !init)
  159. goto cleanup;
  160. clk_hw->dpll_data = ad;
  161. clk_hw->hw.init = init;
  162. init->name = node->name;
  163. init->ops = &apll_ck_ops;
  164. init->num_parents = of_clk_get_parent_count(node);
  165. if (init->num_parents < 1) {
  166. pr_err("dra7 apll %pOFn must have parent(s)\n", node);
  167. goto cleanup;
  168. }
  169. parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
  170. if (!parent_names)
  171. goto cleanup;
  172. of_clk_parent_fill(node, parent_names, init->num_parents);
  173. init->parent_names = parent_names;
  174. ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
  175. ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg);
  176. if (ret)
  177. goto cleanup;
  178. ad->idlest_mask = 0x1;
  179. ad->enable_mask = 0x3;
  180. omap_clk_register_apll(&clk_hw->hw, node);
  181. return;
  182. cleanup:
  183. kfree(parent_names);
  184. kfree(ad);
  185. kfree(clk_hw);
  186. kfree(init);
  187. }
  188. CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
  189. #define OMAP2_EN_APLL_LOCKED 0x3
  190. #define OMAP2_EN_APLL_STOPPED 0x0
  191. static int omap2_apll_is_enabled(struct clk_hw *hw)
  192. {
  193. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  194. struct dpll_data *ad = clk->dpll_data;
  195. u32 v;
  196. v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
  197. v &= ad->enable_mask;
  198. v >>= __ffs(ad->enable_mask);
  199. return v == OMAP2_EN_APLL_LOCKED ? 1 : 0;
  200. }
  201. static unsigned long omap2_apll_recalc(struct clk_hw *hw,
  202. unsigned long parent_rate)
  203. {
  204. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  205. if (omap2_apll_is_enabled(hw))
  206. return clk->fixed_rate;
  207. return 0;
  208. }
  209. static int omap2_apll_enable(struct clk_hw *hw)
  210. {
  211. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  212. struct dpll_data *ad = clk->dpll_data;
  213. u32 v;
  214. int i = 0;
  215. v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
  216. v &= ~ad->enable_mask;
  217. v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);
  218. ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
  219. while (1) {
  220. v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
  221. if (v & ad->idlest_mask)
  222. break;
  223. if (i > MAX_APLL_WAIT_TRIES)
  224. break;
  225. i++;
  226. udelay(1);
  227. }
  228. if (i == MAX_APLL_WAIT_TRIES) {
  229. pr_warn("%s failed to transition to locked\n",
  230. clk_hw_get_name(&clk->hw));
  231. return -EBUSY;
  232. }
  233. return 0;
  234. }
  235. static void omap2_apll_disable(struct clk_hw *hw)
  236. {
  237. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  238. struct dpll_data *ad = clk->dpll_data;
  239. u32 v;
  240. v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
  241. v &= ~ad->enable_mask;
  242. v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);
  243. ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
  244. }
  245. static const struct clk_ops omap2_apll_ops = {
  246. .enable = &omap2_apll_enable,
  247. .disable = &omap2_apll_disable,
  248. .is_enabled = &omap2_apll_is_enabled,
  249. .recalc_rate = &omap2_apll_recalc,
  250. };
  251. static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val)
  252. {
  253. struct dpll_data *ad = clk->dpll_data;
  254. u32 v;
  255. v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg);
  256. v &= ~ad->autoidle_mask;
  257. v |= val << __ffs(ad->autoidle_mask);
  258. ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
  259. }
  260. #define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
  261. #define OMAP2_APLL_AUTOIDLE_DISABLE 0x0
  262. static void omap2_apll_allow_idle(struct clk_hw_omap *clk)
  263. {
  264. omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP);
  265. }
  266. static void omap2_apll_deny_idle(struct clk_hw_omap *clk)
  267. {
  268. omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE);
  269. }
  270. static const struct clk_hw_omap_ops omap2_apll_hwops = {
  271. .allow_idle = &omap2_apll_allow_idle,
  272. .deny_idle = &omap2_apll_deny_idle,
  273. };
  274. static void __init of_omap2_apll_setup(struct device_node *node)
  275. {
  276. struct dpll_data *ad = NULL;
  277. struct clk_hw_omap *clk_hw = NULL;
  278. struct clk_init_data *init = NULL;
  279. struct clk *clk;
  280. const char *parent_name;
  281. u32 val;
  282. int ret;
  283. ad = kzalloc(sizeof(*ad), GFP_KERNEL);
  284. clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
  285. init = kzalloc(sizeof(*init), GFP_KERNEL);
  286. if (!ad || !clk_hw || !init)
  287. goto cleanup;
  288. clk_hw->dpll_data = ad;
  289. clk_hw->hw.init = init;
  290. init->ops = &omap2_apll_ops;
  291. init->name = node->name;
  292. clk_hw->ops = &omap2_apll_hwops;
  293. init->num_parents = of_clk_get_parent_count(node);
  294. if (init->num_parents != 1) {
  295. pr_err("%pOFn must have one parent\n", node);
  296. goto cleanup;
  297. }
  298. parent_name = of_clk_get_parent_name(node, 0);
  299. init->parent_names = &parent_name;
  300. if (of_property_read_u32(node, "ti,clock-frequency", &val)) {
  301. pr_err("%pOFn missing clock-frequency\n", node);
  302. goto cleanup;
  303. }
  304. clk_hw->fixed_rate = val;
  305. if (of_property_read_u32(node, "ti,bit-shift", &val)) {
  306. pr_err("%pOFn missing bit-shift\n", node);
  307. goto cleanup;
  308. }
  309. clk_hw->enable_bit = val;
  310. ad->enable_mask = 0x3 << val;
  311. ad->autoidle_mask = 0x3 << val;
  312. if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
  313. pr_err("%pOFn missing idlest-shift\n", node);
  314. goto cleanup;
  315. }
  316. ad->idlest_mask = 1 << val;
  317. ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
  318. ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg);
  319. ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg);
  320. if (ret)
  321. goto cleanup;
  322. clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);
  323. if (!IS_ERR(clk)) {
  324. of_clk_add_provider(node, of_clk_src_simple_get, clk);
  325. kfree(init);
  326. return;
  327. }
  328. cleanup:
  329. kfree(ad);
  330. kfree(clk_hw);
  331. kfree(init);
  332. }
  333. CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock",
  334. of_omap2_apll_setup);