adpll.c 24 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or
  3. * modify it under the terms of the GNU General Public License as
  4. * published by the Free Software Foundation version 2.
  5. *
  6. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  7. * kind, whether express or implied; without even the implied warranty
  8. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  9. * GNU General Public License for more details.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clkdev.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/delay.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/math64.h>
  18. #include <linux/module.h>
  19. #include <linux/of_device.h>
  20. #include <linux/string.h>
  21. #define ADPLL_PLLSS_MMR_LOCK_OFFSET 0x00 /* Managed by MPPULL */
  22. #define ADPLL_PLLSS_MMR_LOCK_ENABLED 0x1f125B64
  23. #define ADPLL_PLLSS_MMR_UNLOCK_MAGIC 0x1eda4c3d
  24. #define ADPLL_PWRCTRL_OFFSET 0x00
  25. #define ADPLL_PWRCTRL_PONIN 5
  26. #define ADPLL_PWRCTRL_PGOODIN 4
  27. #define ADPLL_PWRCTRL_RET 3
  28. #define ADPLL_PWRCTRL_ISORET 2
  29. #define ADPLL_PWRCTRL_ISOSCAN 1
  30. #define ADPLL_PWRCTRL_OFFMODE 0
  31. #define ADPLL_CLKCTRL_OFFSET 0x04
  32. #define ADPLL_CLKCTRL_CLKDCOLDOEN 29
  33. #define ADPLL_CLKCTRL_IDLE 23
  34. #define ADPLL_CLKCTRL_CLKOUTEN 20
  35. #define ADPLL_CLKINPHIFSEL_ADPLL_S 19 /* REVISIT: which bit? */
  36. #define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19
  37. #define ADPLL_CLKCTRL_ULOWCLKEN 18
  38. #define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ 17
  39. #define ADPLL_CLKCTRL_M2PWDNZ 16
  40. #define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S 15
  41. #define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13
  42. #define ADPLL_CLKCTRL_LPMODE_ADPLL_S 12
  43. #define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S 10
  44. #define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10
  45. #define ADPLL_CLKCTRL_TINITZ 0
  46. #define ADPLL_TENABLE_OFFSET 0x08
  47. #define ADPLL_TENABLEDIV_OFFSET 0x8c
  48. #define ADPLL_M2NDIV_OFFSET 0x10
  49. #define ADPLL_M2NDIV_M2 16
  50. #define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH 5
  51. #define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH 7
  52. #define ADPLL_MN2DIV_OFFSET 0x14
  53. #define ADPLL_MN2DIV_N2 16
  54. #define ADPLL_FRACDIV_OFFSET 0x18
  55. #define ADPLL_FRACDIV_REGSD 24
  56. #define ADPLL_FRACDIV_FRACTIONALM 0
  57. #define ADPLL_FRACDIV_FRACTIONALM_MASK 0x3ffff
  58. #define ADPLL_BWCTRL_OFFSET 0x1c
  59. #define ADPLL_BWCTRL_BWCONTROL 1
  60. #define ADPLL_BWCTRL_BW_INCR_DECRZ 0
  61. #define ADPLL_RESERVED_OFFSET 0x20
  62. #define ADPLL_STATUS_OFFSET 0x24
  63. #define ADPLL_STATUS_PONOUT 31
  64. #define ADPLL_STATUS_PGOODOUT 30
  65. #define ADPLL_STATUS_LDOPWDN 29
  66. #define ADPLL_STATUS_RECAL_BSTATUS3 28
  67. #define ADPLL_STATUS_RECAL_OPPIN 27
  68. #define ADPLL_STATUS_PHASELOCK 10
  69. #define ADPLL_STATUS_FREQLOCK 9
  70. #define ADPLL_STATUS_BYPASSACK 8
  71. #define ADPLL_STATUS_LOSSREF 6
  72. #define ADPLL_STATUS_CLKOUTENACK 5
  73. #define ADPLL_STATUS_LOCK2 4
  74. #define ADPLL_STATUS_M2CHANGEACK 3
  75. #define ADPLL_STATUS_HIGHJITTER 1
  76. #define ADPLL_STATUS_BYPASS 0
  77. #define ADPLL_STATUS_PREPARED_MASK (BIT(ADPLL_STATUS_PHASELOCK) | \
  78. BIT(ADPLL_STATUS_FREQLOCK))
  79. #define ADPLL_M3DIV_OFFSET 0x28 /* Only on MPUPLL */
  80. #define ADPLL_M3DIV_M3 0
  81. #define ADPLL_M3DIV_M3_WIDTH 5
  82. #define ADPLL_M3DIV_M3_MASK 0x1f
  83. #define ADPLL_RAMPCTRL_OFFSET 0x2c /* Only on MPUPLL */
  84. #define ADPLL_RAMPCTRL_CLKRAMPLEVEL 19
  85. #define ADPLL_RAMPCTRL_CLKRAMPRATE 16
  86. #define ADPLL_RAMPCTRL_RELOCK_RAMP_EN 0
  87. #define MAX_ADPLL_INPUTS 3
  88. #define MAX_ADPLL_OUTPUTS 4
  89. #define ADPLL_MAX_RETRIES 5
  90. #define to_dco(_hw) container_of(_hw, struct ti_adpll_dco_data, hw)
  91. #define to_adpll(_hw) container_of(_hw, struct ti_adpll_data, dco)
  92. #define to_clkout(_hw) container_of(_hw, struct ti_adpll_clkout_data, hw)
  93. enum ti_adpll_clocks {
  94. TI_ADPLL_DCO,
  95. TI_ADPLL_DCO_GATE,
  96. TI_ADPLL_N2,
  97. TI_ADPLL_M2,
  98. TI_ADPLL_M2_GATE,
  99. TI_ADPLL_BYPASS,
  100. TI_ADPLL_HIF,
  101. TI_ADPLL_DIV2,
  102. TI_ADPLL_CLKOUT,
  103. TI_ADPLL_CLKOUT2,
  104. TI_ADPLL_M3,
  105. };
  106. #define TI_ADPLL_NR_CLOCKS (TI_ADPLL_M3 + 1)
  107. enum ti_adpll_inputs {
  108. TI_ADPLL_CLKINP,
  109. TI_ADPLL_CLKINPULOW,
  110. TI_ADPLL_CLKINPHIF,
  111. };
  112. enum ti_adpll_s_outputs {
  113. TI_ADPLL_S_DCOCLKLDO,
  114. TI_ADPLL_S_CLKOUT,
  115. TI_ADPLL_S_CLKOUTX2,
  116. TI_ADPLL_S_CLKOUTHIF,
  117. };
  118. enum ti_adpll_lj_outputs {
  119. TI_ADPLL_LJ_CLKDCOLDO,
  120. TI_ADPLL_LJ_CLKOUT,
  121. TI_ADPLL_LJ_CLKOUTLDO,
  122. };
  123. struct ti_adpll_platform_data {
  124. const bool is_type_s;
  125. const int nr_max_inputs;
  126. const int nr_max_outputs;
  127. const int output_index;
  128. };
  129. struct ti_adpll_clock {
  130. struct clk *clk;
  131. struct clk_lookup *cl;
  132. void (*unregister)(struct clk *clk);
  133. };
  134. struct ti_adpll_dco_data {
  135. struct clk_hw hw;
  136. };
  137. struct ti_adpll_clkout_data {
  138. struct ti_adpll_data *adpll;
  139. struct clk_gate gate;
  140. struct clk_hw hw;
  141. };
  142. struct ti_adpll_data {
  143. struct device *dev;
  144. const struct ti_adpll_platform_data *c;
  145. struct device_node *np;
  146. unsigned long pa;
  147. void __iomem *iobase;
  148. void __iomem *regs;
  149. spinlock_t lock; /* For ADPLL shared register access */
  150. const char *parent_names[MAX_ADPLL_INPUTS];
  151. struct clk *parent_clocks[MAX_ADPLL_INPUTS];
  152. struct ti_adpll_clock *clocks;
  153. struct clk_onecell_data outputs;
  154. struct ti_adpll_dco_data dco;
  155. };
  156. static const char *ti_adpll_clk_get_name(struct ti_adpll_data *d,
  157. int output_index,
  158. const char *postfix)
  159. {
  160. const char *name;
  161. int err;
  162. if (output_index >= 0) {
  163. err = of_property_read_string_index(d->np,
  164. "clock-output-names",
  165. output_index,
  166. &name);
  167. if (err)
  168. return NULL;
  169. } else {
  170. name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s",
  171. d->pa, postfix);
  172. }
  173. return name;
  174. }
  175. #define ADPLL_MAX_CON_ID 16 /* See MAX_CON_ID */
  176. static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
  177. int index, int output_index, const char *name,
  178. void (*unregister)(struct clk *clk))
  179. {
  180. struct clk_lookup *cl;
  181. const char *postfix = NULL;
  182. char con_id[ADPLL_MAX_CON_ID];
  183. d->clocks[index].clk = clock;
  184. d->clocks[index].unregister = unregister;
  185. /* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */
  186. postfix = strrchr(name, '.');
  187. if (postfix && strlen(postfix) > 1) {
  188. if (strlen(postfix) > ADPLL_MAX_CON_ID)
  189. dev_warn(d->dev, "clock %s con_id lookup may fail\n",
  190. name);
  191. snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1);
  192. cl = clkdev_create(clock, con_id, NULL);
  193. if (!cl)
  194. return -ENOMEM;
  195. d->clocks[index].cl = cl;
  196. } else {
  197. dev_warn(d->dev, "no con_id for clock %s\n", name);
  198. }
  199. if (output_index < 0)
  200. return 0;
  201. d->outputs.clks[output_index] = clock;
  202. d->outputs.clk_num++;
  203. return 0;
  204. }
  205. static int ti_adpll_init_divider(struct ti_adpll_data *d,
  206. enum ti_adpll_clocks index,
  207. int output_index, char *name,
  208. struct clk *parent_clock,
  209. void __iomem *reg,
  210. u8 shift, u8 width,
  211. u8 clk_divider_flags)
  212. {
  213. const char *child_name;
  214. const char *parent_name;
  215. struct clk *clock;
  216. child_name = ti_adpll_clk_get_name(d, output_index, name);
  217. if (!child_name)
  218. return -EINVAL;
  219. parent_name = __clk_get_name(parent_clock);
  220. clock = clk_register_divider(d->dev, child_name, parent_name, 0,
  221. reg, shift, width, clk_divider_flags,
  222. &d->lock);
  223. if (IS_ERR(clock)) {
  224. dev_err(d->dev, "failed to register divider %s: %li\n",
  225. name, PTR_ERR(clock));
  226. return PTR_ERR(clock);
  227. }
  228. return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
  229. clk_unregister_divider);
  230. }
  231. static int ti_adpll_init_mux(struct ti_adpll_data *d,
  232. enum ti_adpll_clocks index,
  233. char *name, struct clk *clk0,
  234. struct clk *clk1,
  235. void __iomem *reg,
  236. u8 shift)
  237. {
  238. const char *child_name;
  239. const char *parents[2];
  240. struct clk *clock;
  241. child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
  242. if (!child_name)
  243. return -ENOMEM;
  244. parents[0] = __clk_get_name(clk0);
  245. parents[1] = __clk_get_name(clk1);
  246. clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
  247. reg, shift, 1, 0, &d->lock);
  248. if (IS_ERR(clock)) {
  249. dev_err(d->dev, "failed to register mux %s: %li\n",
  250. name, PTR_ERR(clock));
  251. return PTR_ERR(clock);
  252. }
  253. return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
  254. clk_unregister_mux);
  255. }
  256. static int ti_adpll_init_gate(struct ti_adpll_data *d,
  257. enum ti_adpll_clocks index,
  258. int output_index, char *name,
  259. struct clk *parent_clock,
  260. void __iomem *reg,
  261. u8 bit_idx,
  262. u8 clk_gate_flags)
  263. {
  264. const char *child_name;
  265. const char *parent_name;
  266. struct clk *clock;
  267. child_name = ti_adpll_clk_get_name(d, output_index, name);
  268. if (!child_name)
  269. return -EINVAL;
  270. parent_name = __clk_get_name(parent_clock);
  271. clock = clk_register_gate(d->dev, child_name, parent_name, 0,
  272. reg, bit_idx, clk_gate_flags,
  273. &d->lock);
  274. if (IS_ERR(clock)) {
  275. dev_err(d->dev, "failed to register gate %s: %li\n",
  276. name, PTR_ERR(clock));
  277. return PTR_ERR(clock);
  278. }
  279. return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
  280. clk_unregister_gate);
  281. }
  282. static int ti_adpll_init_fixed_factor(struct ti_adpll_data *d,
  283. enum ti_adpll_clocks index,
  284. char *name,
  285. struct clk *parent_clock,
  286. unsigned int mult,
  287. unsigned int div)
  288. {
  289. const char *child_name;
  290. const char *parent_name;
  291. struct clk *clock;
  292. child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
  293. if (!child_name)
  294. return -ENOMEM;
  295. parent_name = __clk_get_name(parent_clock);
  296. clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
  297. 0, mult, div);
  298. if (IS_ERR(clock))
  299. return PTR_ERR(clock);
  300. return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
  301. clk_unregister);
  302. }
  303. static void ti_adpll_set_idle_bypass(struct ti_adpll_data *d)
  304. {
  305. unsigned long flags;
  306. u32 v;
  307. spin_lock_irqsave(&d->lock, flags);
  308. v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
  309. v |= BIT(ADPLL_CLKCTRL_IDLE);
  310. writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
  311. spin_unlock_irqrestore(&d->lock, flags);
  312. }
  313. static void ti_adpll_clear_idle_bypass(struct ti_adpll_data *d)
  314. {
  315. unsigned long flags;
  316. u32 v;
  317. spin_lock_irqsave(&d->lock, flags);
  318. v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
  319. v &= ~BIT(ADPLL_CLKCTRL_IDLE);
  320. writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
  321. spin_unlock_irqrestore(&d->lock, flags);
  322. }
  323. static bool ti_adpll_clock_is_bypass(struct ti_adpll_data *d)
  324. {
  325. u32 v;
  326. v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
  327. return v & BIT(ADPLL_STATUS_BYPASS);
  328. }
  329. /*
  330. * Locked and bypass are not actually mutually exclusive: if you only care
  331. * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
  332. * the PLL, resulting in status (FREQLOCK | PHASELOCK | BYPASS) after lock.
  333. */
  334. static bool ti_adpll_is_locked(struct ti_adpll_data *d)
  335. {
  336. u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
  337. return (v & ADPLL_STATUS_PREPARED_MASK) == ADPLL_STATUS_PREPARED_MASK;
  338. }
  339. static int ti_adpll_wait_lock(struct ti_adpll_data *d)
  340. {
  341. int retries = ADPLL_MAX_RETRIES;
  342. do {
  343. if (ti_adpll_is_locked(d))
  344. return 0;
  345. usleep_range(200, 300);
  346. } while (retries--);
  347. dev_err(d->dev, "pll failed to lock\n");
  348. return -ETIMEDOUT;
  349. }
  350. static int ti_adpll_prepare(struct clk_hw *hw)
  351. {
  352. struct ti_adpll_dco_data *dco = to_dco(hw);
  353. struct ti_adpll_data *d = to_adpll(dco);
  354. ti_adpll_clear_idle_bypass(d);
  355. ti_adpll_wait_lock(d);
  356. return 0;
  357. }
  358. static void ti_adpll_unprepare(struct clk_hw *hw)
  359. {
  360. struct ti_adpll_dco_data *dco = to_dco(hw);
  361. struct ti_adpll_data *d = to_adpll(dco);
  362. ti_adpll_set_idle_bypass(d);
  363. }
  364. static int ti_adpll_is_prepared(struct clk_hw *hw)
  365. {
  366. struct ti_adpll_dco_data *dco = to_dco(hw);
  367. struct ti_adpll_data *d = to_adpll(dco);
  368. return ti_adpll_is_locked(d);
  369. }
  370. /*
  371. * Note that the DCO clock is never subject to bypass: if the PLL is off,
  372. * dcoclk is low.
  373. */
  374. static unsigned long ti_adpll_recalc_rate(struct clk_hw *hw,
  375. unsigned long parent_rate)
  376. {
  377. struct ti_adpll_dco_data *dco = to_dco(hw);
  378. struct ti_adpll_data *d = to_adpll(dco);
  379. u32 frac_m, divider, v;
  380. u64 rate;
  381. unsigned long flags;
  382. if (ti_adpll_clock_is_bypass(d))
  383. return 0;
  384. spin_lock_irqsave(&d->lock, flags);
  385. frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET);
  386. frac_m &= ADPLL_FRACDIV_FRACTIONALM_MASK;
  387. rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18;
  388. rate += frac_m;
  389. rate *= parent_rate;
  390. divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
  391. spin_unlock_irqrestore(&d->lock, flags);
  392. do_div(rate, divider);
  393. if (d->c->is_type_s) {
  394. v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
  395. if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S))
  396. rate *= 4;
  397. rate *= 2;
  398. }
  399. return rate;
  400. }
  401. /* PLL parent is always clkinp, bypass only affects the children */
  402. static u8 ti_adpll_get_parent(struct clk_hw *hw)
  403. {
  404. return 0;
  405. }
  406. static const struct clk_ops ti_adpll_ops = {
  407. .prepare = ti_adpll_prepare,
  408. .unprepare = ti_adpll_unprepare,
  409. .is_prepared = ti_adpll_is_prepared,
  410. .recalc_rate = ti_adpll_recalc_rate,
  411. .get_parent = ti_adpll_get_parent,
  412. };
  413. static int ti_adpll_init_dco(struct ti_adpll_data *d)
  414. {
  415. struct clk_init_data init;
  416. struct clk *clock;
  417. const char *postfix;
  418. int width, err;
  419. d->outputs.clks = devm_kcalloc(d->dev,
  420. MAX_ADPLL_OUTPUTS,
  421. sizeof(struct clk *),
  422. GFP_KERNEL);
  423. if (!d->outputs.clks)
  424. return -ENOMEM;
  425. if (d->c->output_index < 0)
  426. postfix = "dco";
  427. else
  428. postfix = NULL;
  429. init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix);
  430. if (!init.name)
  431. return -EINVAL;
  432. init.parent_names = d->parent_names;
  433. init.num_parents = d->c->nr_max_inputs;
  434. init.ops = &ti_adpll_ops;
  435. init.flags = CLK_GET_RATE_NOCACHE;
  436. d->dco.hw.init = &init;
  437. if (d->c->is_type_s)
  438. width = 5;
  439. else
  440. width = 4;
  441. /* Internal input clock divider N2 */
  442. err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2",
  443. d->parent_clocks[TI_ADPLL_CLKINP],
  444. d->regs + ADPLL_MN2DIV_OFFSET,
  445. ADPLL_MN2DIV_N2, width, 0);
  446. if (err)
  447. return err;
  448. clock = devm_clk_register(d->dev, &d->dco.hw);
  449. if (IS_ERR(clock))
  450. return PTR_ERR(clock);
  451. return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,
  452. init.name, NULL);
  453. }
  454. static int ti_adpll_clkout_enable(struct clk_hw *hw)
  455. {
  456. struct ti_adpll_clkout_data *co = to_clkout(hw);
  457. struct clk_hw *gate_hw = &co->gate.hw;
  458. __clk_hw_set_clk(gate_hw, hw);
  459. return clk_gate_ops.enable(gate_hw);
  460. }
  461. static void ti_adpll_clkout_disable(struct clk_hw *hw)
  462. {
  463. struct ti_adpll_clkout_data *co = to_clkout(hw);
  464. struct clk_hw *gate_hw = &co->gate.hw;
  465. __clk_hw_set_clk(gate_hw, hw);
  466. clk_gate_ops.disable(gate_hw);
  467. }
  468. static int ti_adpll_clkout_is_enabled(struct clk_hw *hw)
  469. {
  470. struct ti_adpll_clkout_data *co = to_clkout(hw);
  471. struct clk_hw *gate_hw = &co->gate.hw;
  472. __clk_hw_set_clk(gate_hw, hw);
  473. return clk_gate_ops.is_enabled(gate_hw);
  474. }
  475. /* Setting PLL bypass puts clkout and clkoutx2 into bypass */
  476. static u8 ti_adpll_clkout_get_parent(struct clk_hw *hw)
  477. {
  478. struct ti_adpll_clkout_data *co = to_clkout(hw);
  479. struct ti_adpll_data *d = co->adpll;
  480. return ti_adpll_clock_is_bypass(d);
  481. }
  482. static int ti_adpll_init_clkout(struct ti_adpll_data *d,
  483. enum ti_adpll_clocks index,
  484. int output_index, int gate_bit,
  485. char *name, struct clk *clk0,
  486. struct clk *clk1)
  487. {
  488. struct ti_adpll_clkout_data *co;
  489. struct clk_init_data init;
  490. struct clk_ops *ops;
  491. const char *parent_names[2];
  492. const char *child_name;
  493. struct clk *clock;
  494. int err;
  495. co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL);
  496. if (!co)
  497. return -ENOMEM;
  498. co->adpll = d;
  499. err = of_property_read_string_index(d->np,
  500. "clock-output-names",
  501. output_index,
  502. &child_name);
  503. if (err)
  504. return err;
  505. ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL);
  506. if (!ops)
  507. return -ENOMEM;
  508. init.name = child_name;
  509. init.ops = ops;
  510. init.flags = 0;
  511. co->hw.init = &init;
  512. parent_names[0] = __clk_get_name(clk0);
  513. parent_names[1] = __clk_get_name(clk1);
  514. init.parent_names = parent_names;
  515. init.num_parents = 2;
  516. ops->get_parent = ti_adpll_clkout_get_parent;
  517. ops->determine_rate = __clk_mux_determine_rate;
  518. if (gate_bit) {
  519. co->gate.lock = &d->lock;
  520. co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET;
  521. co->gate.bit_idx = gate_bit;
  522. ops->enable = ti_adpll_clkout_enable;
  523. ops->disable = ti_adpll_clkout_disable;
  524. ops->is_enabled = ti_adpll_clkout_is_enabled;
  525. }
  526. clock = devm_clk_register(d->dev, &co->hw);
  527. if (IS_ERR(clock)) {
  528. dev_err(d->dev, "failed to register output %s: %li\n",
  529. name, PTR_ERR(clock));
  530. return PTR_ERR(clock);
  531. }
  532. return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
  533. NULL);
  534. }
  535. static int ti_adpll_init_children_adpll_s(struct ti_adpll_data *d)
  536. {
  537. int err;
  538. if (!d->c->is_type_s)
  539. return 0;
  540. /* Internal mux, sources from divider N2 or clkinpulow */
  541. err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
  542. d->clocks[TI_ADPLL_N2].clk,
  543. d->parent_clocks[TI_ADPLL_CLKINPULOW],
  544. d->regs + ADPLL_CLKCTRL_OFFSET,
  545. ADPLL_CLKCTRL_ULOWCLKEN);
  546. if (err)
  547. return err;
  548. /* Internal divider M2, sources DCO */
  549. err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2",
  550. d->clocks[TI_ADPLL_DCO].clk,
  551. d->regs + ADPLL_M2NDIV_OFFSET,
  552. ADPLL_M2NDIV_M2,
  553. ADPLL_M2NDIV_M2_ADPLL_S_WIDTH,
  554. CLK_DIVIDER_ONE_BASED);
  555. if (err)
  556. return err;
  557. /* Internal fixed divider, after M2 before clkout */
  558. err = ti_adpll_init_fixed_factor(d, TI_ADPLL_DIV2, "div2",
  559. d->clocks[TI_ADPLL_M2].clk,
  560. 1, 2);
  561. if (err)
  562. return err;
  563. /* Output clkout with a mux and gate, sources from div2 or bypass */
  564. err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
  565. ADPLL_CLKCTRL_CLKOUTEN, "clkout",
  566. d->clocks[TI_ADPLL_DIV2].clk,
  567. d->clocks[TI_ADPLL_BYPASS].clk);
  568. if (err)
  569. return err;
  570. /* Output clkoutx2 with a mux and gate, sources from M2 or bypass */
  571. err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT2, TI_ADPLL_S_CLKOUTX2, 0,
  572. "clkout2", d->clocks[TI_ADPLL_M2].clk,
  573. d->clocks[TI_ADPLL_BYPASS].clk);
  574. if (err)
  575. return err;
  576. /* Internal mux, sources from DCO and clkinphif */
  577. if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) {
  578. err = ti_adpll_init_mux(d, TI_ADPLL_HIF, "hif",
  579. d->clocks[TI_ADPLL_DCO].clk,
  580. d->parent_clocks[TI_ADPLL_CLKINPHIF],
  581. d->regs + ADPLL_CLKCTRL_OFFSET,
  582. ADPLL_CLKINPHIFSEL_ADPLL_S);
  583. if (err)
  584. return err;
  585. }
  586. /* Output clkouthif with a divider M3, sources from hif */
  587. err = ti_adpll_init_divider(d, TI_ADPLL_M3, TI_ADPLL_S_CLKOUTHIF, "m3",
  588. d->clocks[TI_ADPLL_HIF].clk,
  589. d->regs + ADPLL_M3DIV_OFFSET,
  590. ADPLL_M3DIV_M3,
  591. ADPLL_M3DIV_M3_WIDTH,
  592. CLK_DIVIDER_ONE_BASED);
  593. if (err)
  594. return err;
  595. /* Output clock dcoclkldo is the DCO */
  596. return 0;
  597. }
  598. static int ti_adpll_init_children_adpll_lj(struct ti_adpll_data *d)
  599. {
  600. int err;
  601. if (d->c->is_type_s)
  602. return 0;
  603. /* Output clkdcoldo, gated output of DCO */
  604. err = ti_adpll_init_gate(d, TI_ADPLL_DCO_GATE, TI_ADPLL_LJ_CLKDCOLDO,
  605. "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk,
  606. d->regs + ADPLL_CLKCTRL_OFFSET,
  607. ADPLL_CLKCTRL_CLKDCOLDOEN, 0);
  608. if (err)
  609. return err;
  610. /* Internal divider M2, sources from DCO */
  611. err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV,
  612. "m2", d->clocks[TI_ADPLL_DCO].clk,
  613. d->regs + ADPLL_M2NDIV_OFFSET,
  614. ADPLL_M2NDIV_M2,
  615. ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH,
  616. CLK_DIVIDER_ONE_BASED);
  617. if (err)
  618. return err;
  619. /* Output clkoutldo, gated output of M2 */
  620. err = ti_adpll_init_gate(d, TI_ADPLL_M2_GATE, TI_ADPLL_LJ_CLKOUTLDO,
  621. "clkoutldo", d->clocks[TI_ADPLL_M2].clk,
  622. d->regs + ADPLL_CLKCTRL_OFFSET,
  623. ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ,
  624. 0);
  625. if (err)
  626. return err;
  627. /* Internal mux, sources from divider N2 or clkinpulow */
  628. err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
  629. d->clocks[TI_ADPLL_N2].clk,
  630. d->parent_clocks[TI_ADPLL_CLKINPULOW],
  631. d->regs + ADPLL_CLKCTRL_OFFSET,
  632. ADPLL_CLKCTRL_ULOWCLKEN);
  633. if (err)
  634. return err;
  635. /* Output clkout, sources M2 or bypass */
  636. err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
  637. ADPLL_CLKCTRL_CLKOUTEN, "clkout",
  638. d->clocks[TI_ADPLL_M2].clk,
  639. d->clocks[TI_ADPLL_BYPASS].clk);
  640. if (err)
  641. return err;
  642. return 0;
  643. }
  644. static void ti_adpll_free_resources(struct ti_adpll_data *d)
  645. {
  646. int i;
  647. for (i = TI_ADPLL_M3; i >= 0; i--) {
  648. struct ti_adpll_clock *ac = &d->clocks[i];
  649. if (!ac || IS_ERR_OR_NULL(ac->clk))
  650. continue;
  651. if (ac->cl)
  652. clkdev_drop(ac->cl);
  653. if (ac->unregister)
  654. ac->unregister(ac->clk);
  655. }
  656. }
  657. /* MPU PLL manages the lock register for all PLLs */
  658. static void ti_adpll_unlock_all(void __iomem *reg)
  659. {
  660. u32 v;
  661. v = readl_relaxed(reg);
  662. if (v == ADPLL_PLLSS_MMR_LOCK_ENABLED)
  663. writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg);
  664. }
  665. static int ti_adpll_init_registers(struct ti_adpll_data *d)
  666. {
  667. int register_offset = 0;
  668. if (d->c->is_type_s) {
  669. register_offset = 8;
  670. ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET);
  671. }
  672. d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET;
  673. return 0;
  674. }
  675. static int ti_adpll_init_inputs(struct ti_adpll_data *d)
  676. {
  677. const char *error = "need at least %i inputs";
  678. struct clk *clock;
  679. int nr_inputs;
  680. nr_inputs = of_clk_get_parent_count(d->np);
  681. if (nr_inputs < d->c->nr_max_inputs) {
  682. dev_err(d->dev, error, nr_inputs);
  683. return -EINVAL;
  684. }
  685. of_clk_parent_fill(d->np, d->parent_names, nr_inputs);
  686. clock = devm_clk_get(d->dev, d->parent_names[0]);
  687. if (IS_ERR(clock)) {
  688. dev_err(d->dev, "could not get clkinp\n");
  689. return PTR_ERR(clock);
  690. }
  691. d->parent_clocks[TI_ADPLL_CLKINP] = clock;
  692. clock = devm_clk_get(d->dev, d->parent_names[1]);
  693. if (IS_ERR(clock)) {
  694. dev_err(d->dev, "could not get clkinpulow clock\n");
  695. return PTR_ERR(clock);
  696. }
  697. d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
  698. if (d->c->is_type_s) {
  699. clock = devm_clk_get(d->dev, d->parent_names[2]);
  700. if (IS_ERR(clock)) {
  701. dev_err(d->dev, "could not get clkinphif clock\n");
  702. return PTR_ERR(clock);
  703. }
  704. d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
  705. }
  706. return 0;
  707. }
  708. static const struct ti_adpll_platform_data ti_adpll_type_s = {
  709. .is_type_s = true,
  710. .nr_max_inputs = MAX_ADPLL_INPUTS,
  711. .nr_max_outputs = MAX_ADPLL_OUTPUTS,
  712. .output_index = TI_ADPLL_S_DCOCLKLDO,
  713. };
  714. static const struct ti_adpll_platform_data ti_adpll_type_lj = {
  715. .is_type_s = false,
  716. .nr_max_inputs = MAX_ADPLL_INPUTS - 1,
  717. .nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
  718. .output_index = -EINVAL,
  719. };
  720. static const struct of_device_id ti_adpll_match[] = {
  721. { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
  722. { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
  723. {},
  724. };
  725. MODULE_DEVICE_TABLE(of, ti_adpll_match);
  726. static int ti_adpll_probe(struct platform_device *pdev)
  727. {
  728. struct device_node *node = pdev->dev.of_node;
  729. struct device *dev = &pdev->dev;
  730. const struct of_device_id *match;
  731. const struct ti_adpll_platform_data *pdata;
  732. struct ti_adpll_data *d;
  733. struct resource *res;
  734. int err;
  735. match = of_match_device(ti_adpll_match, dev);
  736. if (match)
  737. pdata = match->data;
  738. else
  739. return -ENODEV;
  740. d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
  741. if (!d)
  742. return -ENOMEM;
  743. d->dev = dev;
  744. d->np = node;
  745. d->c = pdata;
  746. dev_set_drvdata(d->dev, d);
  747. spin_lock_init(&d->lock);
  748. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  749. if (!res)
  750. return -ENODEV;
  751. d->pa = res->start;
  752. d->iobase = devm_ioremap_resource(dev, res);
  753. if (IS_ERR(d->iobase)) {
  754. dev_err(dev, "could not get IO base: %li\n",
  755. PTR_ERR(d->iobase));
  756. return PTR_ERR(d->iobase);
  757. }
  758. err = ti_adpll_init_registers(d);
  759. if (err)
  760. return err;
  761. err = ti_adpll_init_inputs(d);
  762. if (err)
  763. return err;
  764. d->clocks = devm_kcalloc(d->dev,
  765. TI_ADPLL_NR_CLOCKS,
  766. sizeof(struct ti_adpll_clock),
  767. GFP_KERNEL);
  768. if (!d->clocks)
  769. return -ENOMEM;
  770. err = ti_adpll_init_dco(d);
  771. if (err) {
  772. dev_err(dev, "could not register dco: %i\n", err);
  773. goto free;
  774. }
  775. err = ti_adpll_init_children_adpll_s(d);
  776. if (err)
  777. goto free;
  778. err = ti_adpll_init_children_adpll_lj(d);
  779. if (err)
  780. goto free;
  781. err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs);
  782. if (err)
  783. goto free;
  784. return 0;
  785. free:
  786. WARN_ON(1);
  787. ti_adpll_free_resources(d);
  788. return err;
  789. }
  790. static int ti_adpll_remove(struct platform_device *pdev)
  791. {
  792. struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev);
  793. ti_adpll_free_resources(d);
  794. return 0;
  795. }
  796. static struct platform_driver ti_adpll_driver = {
  797. .driver = {
  798. .name = "ti-adpll",
  799. .of_match_table = ti_adpll_match,
  800. },
  801. .probe = ti_adpll_probe,
  802. .remove = ti_adpll_remove,
  803. };
  804. static int __init ti_adpll_init(void)
  805. {
  806. return platform_driver_register(&ti_adpll_driver);
  807. }
  808. core_initcall(ti_adpll_init);
  809. static void __exit ti_adpll_exit(void)
  810. {
  811. platform_driver_unregister(&ti_adpll_driver);
  812. }
  813. module_exit(ti_adpll_exit);
  814. MODULE_DESCRIPTION("Clock driver for dm814x ADPLL");
  815. MODULE_ALIAS("platform:dm814-adpll-clock");
  816. MODULE_AUTHOR("Tony LIndgren <tony@atomide.com>");
  817. MODULE_LICENSE("GPL v2");