clk.h 1.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
  4. *
  5. * based on drivers/clk/tegra/clk.h
  6. */
  7. #ifndef __SOCFPGA_CLK_H
  8. #define __SOCFPGA_CLK_H
  9. #include <linux/clk-provider.h>
  10. /* Clock Manager offsets */
  11. #define CLKMGR_CTRL 0x0
  12. #define CLKMGR_BYPASS 0x4
  13. #define CLKMGR_DBCTRL 0x10
  14. #define CLKMGR_L4SRC 0x70
  15. #define CLKMGR_PERPLL_SRC 0xAC
  16. #define SOCFPGA_MAX_PARENTS 5
  17. #define streq(a, b) (strcmp((a), (b)) == 0)
  18. #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
  19. ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
  20. #define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \
  21. ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
  22. extern void __iomem *clk_mgr_base_addr;
  23. extern void __iomem *clk_mgr_a10_base_addr;
  24. void __init socfpga_pll_init(struct device_node *node);
  25. void __init socfpga_periph_init(struct device_node *node);
  26. void __init socfpga_gate_init(struct device_node *node);
  27. void socfpga_a10_pll_init(struct device_node *node);
  28. void socfpga_a10_periph_init(struct device_node *node);
  29. void socfpga_a10_gate_init(struct device_node *node);
  30. struct socfpga_pll {
  31. struct clk_gate hw;
  32. };
  33. struct socfpga_gate_clk {
  34. struct clk_gate hw;
  35. char *parent_name;
  36. u32 fixed_div;
  37. void __iomem *div_reg;
  38. void __iomem *bypass_reg;
  39. struct regmap *sys_mgr_base_addr;
  40. u32 width; /* only valid if div_reg != 0 */
  41. u32 shift; /* only valid if div_reg != 0 */
  42. u32 bypass_shift; /* only valid if bypass_reg != 0 */
  43. u32 clk_phase[2];
  44. };
  45. struct socfpga_periph_clk {
  46. struct clk_gate hw;
  47. char *parent_name;
  48. u32 fixed_div;
  49. void __iomem *div_reg;
  50. void __iomem *bypass_reg;
  51. u32 width; /* only valid if div_reg != 0 */
  52. u32 shift; /* only valid if div_reg != 0 */
  53. u32 bypass_shift; /* only valid if bypass_reg != 0 */
  54. };
  55. #endif /* SOCFPGA_CLK_H */