clk-s10.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017, Intel Corporation
  4. */
  5. #include <linux/slab.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/of_device.h>
  8. #include <linux/of_address.h>
  9. #include <linux/platform_device.h>
  10. #include <dt-bindings/clock/stratix10-clock.h>
  11. #include "stratix10-clk.h"
  12. static const struct clk_parent_data pll_mux[] = {
  13. { .fw_name = "osc1",
  14. .name = "osc1" },
  15. { .fw_name = "cb-intosc-hs-div2-clk",
  16. .name = "cb-intosc-hs-div2-clk" },
  17. { .fw_name = "f2s-free-clk",
  18. .name = "f2s-free-clk" },
  19. };
  20. static const struct clk_parent_data cntr_mux[] = {
  21. { .fw_name = "main_pll",
  22. .name = "main_pll", },
  23. { .fw_name = "periph_pll",
  24. .name = "periph_pll", },
  25. { .fw_name = "osc1",
  26. .name = "osc1", },
  27. { .fw_name = "cb-intosc-hs-div2-clk",
  28. .name = "cb-intosc-hs-div2-clk", },
  29. { .fw_name = "f2s-free-clk",
  30. .name = "f2s-free-clk", },
  31. };
  32. static const struct clk_parent_data boot_mux[] = {
  33. { .fw_name = "osc1",
  34. .name = "osc1" },
  35. { .fw_name = "cb-intosc-hs-div2-clk",
  36. .name = "cb-intosc-hs-div2-clk" },
  37. };
  38. static const struct clk_parent_data noc_free_mux[] = {
  39. { .fw_name = "main_noc_base_clk",
  40. .name = "main_noc_base_clk", },
  41. { .fw_name = "peri_noc_base_clk",
  42. .name = "peri_noc_base_clk", },
  43. { .fw_name = "osc1",
  44. .name = "osc1", },
  45. { .fw_name = "cb-intosc-hs-div2-clk",
  46. .name = "cb-intosc-hs-div2-clk", },
  47. { .fw_name = "f2s-free-clk",
  48. .name = "f2s-free-clk", },
  49. };
  50. static const struct clk_parent_data emaca_free_mux[] = {
  51. { .fw_name = "peri_emaca_clk",
  52. .name = "peri_emaca_clk", },
  53. { .fw_name = "boot_clk",
  54. .name = "boot_clk", },
  55. };
  56. static const struct clk_parent_data emacb_free_mux[] = {
  57. { .fw_name = "peri_emacb_clk",
  58. .name = "peri_emacb_clk", },
  59. { .fw_name = "boot_clk",
  60. .name = "boot_clk", },
  61. };
  62. static const struct clk_parent_data emac_ptp_free_mux[] = {
  63. { .fw_name = "peri_emac_ptp_clk",
  64. .name = "peri_emac_ptp_clk", },
  65. { .fw_name = "boot_clk",
  66. .name = "boot_clk", },
  67. };
  68. static const struct clk_parent_data gpio_db_free_mux[] = {
  69. { .fw_name = "peri_gpio_db_clk",
  70. .name = "peri_gpio_db_clk", },
  71. { .fw_name = "boot_clk",
  72. .name = "boot_clk", },
  73. };
  74. static const struct clk_parent_data sdmmc_free_mux[] = {
  75. { .fw_name = "main_sdmmc_clk",
  76. .name = "main_sdmmc_clk", },
  77. { .fw_name = "boot_clk",
  78. .name = "boot_clk", },
  79. };
  80. static const struct clk_parent_data s2f_usr1_free_mux[] = {
  81. { .fw_name = "peri_s2f_usr1_clk",
  82. .name = "peri_s2f_usr1_clk", },
  83. { .fw_name = "boot_clk",
  84. .name = "boot_clk", },
  85. };
  86. static const struct clk_parent_data psi_ref_free_mux[] = {
  87. { .fw_name = "peri_psi_ref_clk",
  88. .name = "peri_psi_ref_clk", },
  89. { .fw_name = "boot_clk",
  90. .name = "boot_clk", },
  91. };
  92. static const struct clk_parent_data mpu_mux[] = {
  93. { .fw_name = "mpu_free_clk",
  94. .name = "mpu_free_clk", },
  95. { .fw_name = "boot_clk",
  96. .name = "boot_clk", },
  97. };
  98. static const struct clk_parent_data s2f_usr0_mux[] = {
  99. { .fw_name = "f2s-free-clk",
  100. .name = "f2s-free-clk", },
  101. { .fw_name = "boot_clk",
  102. .name = "boot_clk", },
  103. };
  104. static const struct clk_parent_data emac_mux[] = {
  105. { .fw_name = "emaca_free_clk",
  106. .name = "emaca_free_clk", },
  107. { .fw_name = "emacb_free_clk",
  108. .name = "emacb_free_clk", },
  109. };
  110. static const struct clk_parent_data noc_mux[] = {
  111. { .fw_name = "noc_free_clk",
  112. .name = "noc_free_clk", },
  113. { .fw_name = "boot_clk",
  114. .name = "boot_clk", },
  115. };
  116. static const struct clk_parent_data mpu_free_mux[] = {
  117. { .fw_name = "main_mpu_base_clk",
  118. .name = "main_mpu_base_clk", },
  119. { .fw_name = "peri_mpu_base_clk",
  120. .name = "peri_mpu_base_clk", },
  121. { .fw_name = "osc1",
  122. .name = "osc1", },
  123. { .fw_name = "cb-intosc-hs-div2-clk",
  124. .name = "cb-intosc-hs-div2-clk", },
  125. { .fw_name = "f2s-free-clk",
  126. .name = "f2s-free-clk", },
  127. };
  128. static const struct clk_parent_data sdmmc_mux[] = {
  129. { .fw_name = "sdmmc_free_clk",
  130. .name = "sdmmc_free_clk", },
  131. { .fw_name = "boot_clk",
  132. .name = "boot_clk", },
  133. };
  134. static const struct clk_parent_data s2f_user1_mux[] = {
  135. { .fw_name = "s2f_user1_free_clk",
  136. .name = "s2f_user1_free_clk", },
  137. { .fw_name = "boot_clk",
  138. .name = "boot_clk", },
  139. };
  140. static const struct clk_parent_data psi_mux[] = {
  141. { .fw_name = "psi_ref_free_clk",
  142. .name = "psi_ref_free_clk", },
  143. { .fw_name = "boot_clk",
  144. .name = "boot_clk", },
  145. };
  146. static const struct clk_parent_data gpio_db_mux[] = {
  147. { .fw_name = "gpio_db_free_clk",
  148. .name = "gpio_db_free_clk", },
  149. { .fw_name = "boot_clk",
  150. .name = "boot_clk", },
  151. };
  152. static const struct clk_parent_data emac_ptp_mux[] = {
  153. { .fw_name = "emac_ptp_free_clk",
  154. .name = "emac_ptp_free_clk", },
  155. { .fw_name = "boot_clk",
  156. .name = "boot_clk", },
  157. };
  158. /* clocks in AO (always on) controller */
  159. static const struct stratix10_pll_clock s10_pll_clks[] = {
  160. { STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
  161. 0x0},
  162. { STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
  163. 0, 0x74},
  164. { STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
  165. 0, 0xe4},
  166. };
  167. static const struct stratix10_perip_c_clock s10_main_perip_c_clks[] = {
  168. { STRATIX10_MAIN_MPU_BASE_CLK, "main_mpu_base_clk", "main_pll", NULL, 1, 0, 0x84},
  169. { STRATIX10_MAIN_NOC_BASE_CLK, "main_noc_base_clk", "main_pll", NULL, 1, 0, 0x88},
  170. { STRATIX10_PERI_MPU_BASE_CLK, "peri_mpu_base_clk", "periph_pll", NULL, 1, 0,
  171. 0xF4},
  172. { STRATIX10_PERI_NOC_BASE_CLK, "peri_noc_base_clk", "periph_pll", NULL, 1, 0,
  173. 0xF8},
  174. };
  175. static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
  176. { STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
  177. 0, 0x48, 0, 0, 0},
  178. { STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
  179. 0, 0x4C, 0, 0x3C, 1},
  180. { STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0,
  181. 0x50, 0, 0, 0},
  182. { STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0,
  183. 0x54, 0, 0, 0},
  184. { STRATIX10_MAIN_EMAC_PTP_CLK, "main_emac_ptp_clk", "main_noc_base_clk", NULL, 1, 0,
  185. 0x58, 0, 0, 0},
  186. { STRATIX10_MAIN_GPIO_DB_CLK, "main_gpio_db_clk", "main_noc_base_clk", NULL, 1, 0,
  187. 0x5C, 0, 0, 0},
  188. { STRATIX10_MAIN_SDMMC_CLK, "main_sdmmc_clk", "main_noc_base_clk", NULL, 1, 0,
  189. 0x60, 0, 0, 0},
  190. { STRATIX10_MAIN_S2F_USR0_CLK, "main_s2f_usr0_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
  191. 0, 0x64, 0, 0, 0},
  192. { STRATIX10_MAIN_S2F_USR1_CLK, "main_s2f_usr1_clk", "main_noc_base_clk", NULL, 1, 0,
  193. 0x68, 0, 0, 0},
  194. { STRATIX10_MAIN_PSI_REF_CLK, "main_psi_ref_clk", "main_noc_base_clk", NULL, 1, 0,
  195. 0x6C, 0, 0, 0},
  196. { STRATIX10_PERI_EMACA_CLK, "peri_emaca_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
  197. 0, 0xBC, 0, 0, 0},
  198. { STRATIX10_PERI_EMACB_CLK, "peri_emacb_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
  199. 0, 0xC0, 0, 0, 0},
  200. { STRATIX10_PERI_EMAC_PTP_CLK, "peri_emac_ptp_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
  201. 0, 0xC4, 0, 0, 0},
  202. { STRATIX10_PERI_GPIO_DB_CLK, "peri_gpio_db_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
  203. 0, 0xC8, 0, 0, 0},
  204. { STRATIX10_PERI_SDMMC_CLK, "peri_sdmmc_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
  205. 0, 0xCC, 0, 0, 0},
  206. { STRATIX10_PERI_S2F_USR0_CLK, "peri_s2f_usr0_clk", "peri_noc_base_clk", NULL, 1, 0,
  207. 0xD0, 0, 0, 0},
  208. { STRATIX10_PERI_S2F_USR1_CLK, "peri_s2f_usr1_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
  209. 0, 0xD4, 0, 0, 0},
  210. { STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0,
  211. 0xD8, 0, 0, 0},
  212. { STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
  213. 0, 4, 0x3C, 1},
  214. { STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
  215. 0, 0, 2, 0xB0, 0},
  216. { STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
  217. 0, 0, 2, 0xB0, 1},
  218. { STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
  219. ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 2, 0xB0, 2},
  220. { STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
  221. ARRAY_SIZE(gpio_db_free_mux), 0, 0, 0, 0xB0, 3},
  222. { STRATIX10_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
  223. ARRAY_SIZE(sdmmc_free_mux), 0, 0, 0, 0xB0, 4},
  224. { STRATIX10_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
  225. ARRAY_SIZE(s2f_usr1_free_mux), 0, 0, 0, 0xB0, 5},
  226. { STRATIX10_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
  227. ARRAY_SIZE(psi_ref_free_mux), 0, 0, 0, 0xB0, 6},
  228. };
  229. static const struct stratix10_gate_clock s10_gate_clks[] = {
  230. { STRATIX10_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x30,
  231. 0, 0, 0, 0, 0x3C, 0, 0},
  232. { STRATIX10_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x30,
  233. 0, 0, 0, 0, 0, 0, 4},
  234. { STRATIX10_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x30,
  235. 0, 0, 0, 0, 0, 0, 2},
  236. { STRATIX10_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
  237. 1, 0x70, 0, 2, 0x3C, 1, 0},
  238. { STRATIX10_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
  239. 2, 0x70, 8, 2, 0x3C, 1, 0},
  240. { STRATIX10_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x30,
  241. 3, 0x70, 16, 2, 0x3C, 1, 0},
  242. { STRATIX10_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
  243. 4, 0x70, 24, 2, 0x3C, 1, 0},
  244. { STRATIX10_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
  245. 4, 0x70, 26, 2, 0x3C, 1, 0},
  246. { STRATIX10_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x30,
  247. 4, 0x70, 28, 1, 0, 0, 0},
  248. { STRATIX10_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
  249. 5, 0, 0, 0, 0x3C, 1, 0},
  250. { STRATIX10_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x30,
  251. 6, 0, 0, 0, 0, 0, 0},
  252. { STRATIX10_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
  253. 0, 0, 0, 0, 0xDC, 26, 0},
  254. { STRATIX10_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
  255. 1, 0, 0, 0, 0xDC, 27, 0},
  256. { STRATIX10_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
  257. 2, 0, 0, 0, 0xDC, 28, 0},
  258. { STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, ARRAY_SIZE(emac_ptp_mux), 0, 0xA4,
  259. 3, 0, 0, 0, 0xB0, 2, 0},
  260. { STRATIX10_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, ARRAY_SIZE(gpio_db_mux), 0, 0xA4,
  261. 4, 0xE0, 0, 16, 0xB0, 3, 0},
  262. { STRATIX10_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0xA4,
  263. 5, 0, 0, 0, 0xB0, 4, 4},
  264. { STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0xA4,
  265. 6, 0, 0, 0, 0xB0, 5, 0},
  266. { STRATIX10_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0xA4,
  267. 7, 0, 0, 0, 0xB0, 6, 0},
  268. { STRATIX10_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
  269. 8, 0, 0, 0, 0, 0, 0},
  270. { STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
  271. 9, 0, 0, 0, 0, 0, 0},
  272. { STRATIX10_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
  273. 10, 0, 0, 0, 0, 0, 0},
  274. { STRATIX10_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
  275. 10, 0, 0, 0, 0, 0, 4},
  276. { STRATIX10_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
  277. 10, 0, 0, 0, 0, 0, 4},
  278. };
  279. static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
  280. int nums, struct stratix10_clock_data *data)
  281. {
  282. struct clk *clk;
  283. void __iomem *base = data->base;
  284. int i;
  285. for (i = 0; i < nums; i++) {
  286. clk = s10_register_periph(&clks[i], base);
  287. if (IS_ERR(clk)) {
  288. pr_err("%s: failed to register clock %s\n",
  289. __func__, clks[i].name);
  290. continue;
  291. }
  292. data->clk_data.clks[clks[i].id] = clk;
  293. }
  294. return 0;
  295. }
  296. static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
  297. int nums, struct stratix10_clock_data *data)
  298. {
  299. struct clk *clk;
  300. void __iomem *base = data->base;
  301. int i;
  302. for (i = 0; i < nums; i++) {
  303. clk = s10_register_cnt_periph(&clks[i], base);
  304. if (IS_ERR(clk)) {
  305. pr_err("%s: failed to register clock %s\n",
  306. __func__, clks[i].name);
  307. continue;
  308. }
  309. data->clk_data.clks[clks[i].id] = clk;
  310. }
  311. return 0;
  312. }
  313. static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
  314. int nums, struct stratix10_clock_data *data)
  315. {
  316. struct clk *clk;
  317. void __iomem *base = data->base;
  318. int i;
  319. for (i = 0; i < nums; i++) {
  320. clk = s10_register_gate(&clks[i], base);
  321. if (IS_ERR(clk)) {
  322. pr_err("%s: failed to register clock %s\n",
  323. __func__, clks[i].name);
  324. continue;
  325. }
  326. data->clk_data.clks[clks[i].id] = clk;
  327. }
  328. return 0;
  329. }
  330. static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
  331. int nums, struct stratix10_clock_data *data)
  332. {
  333. struct clk *clk;
  334. void __iomem *base = data->base;
  335. int i;
  336. for (i = 0; i < nums; i++) {
  337. clk = s10_register_pll(&clks[i], base);
  338. if (IS_ERR(clk)) {
  339. pr_err("%s: failed to register clock %s\n",
  340. __func__, clks[i].name);
  341. continue;
  342. }
  343. data->clk_data.clks[clks[i].id] = clk;
  344. }
  345. return 0;
  346. }
  347. static struct stratix10_clock_data *__socfpga_s10_clk_init(struct platform_device *pdev,
  348. int nr_clks)
  349. {
  350. struct device_node *np = pdev->dev.of_node;
  351. struct device *dev = &pdev->dev;
  352. struct stratix10_clock_data *clk_data;
  353. struct clk **clk_table;
  354. struct resource *res;
  355. void __iomem *base;
  356. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  357. base = devm_ioremap_resource(dev, res);
  358. if (IS_ERR(base)) {
  359. pr_err("%s: failed to map clock registers\n", __func__);
  360. return ERR_CAST(base);
  361. }
  362. clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
  363. if (!clk_data)
  364. return ERR_PTR(-ENOMEM);
  365. clk_data->base = base;
  366. clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
  367. if (!clk_table)
  368. return ERR_PTR(-ENOMEM);
  369. clk_data->clk_data.clks = clk_table;
  370. clk_data->clk_data.clk_num = nr_clks;
  371. of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
  372. return clk_data;
  373. }
  374. static int s10_clkmgr_init(struct platform_device *pdev)
  375. {
  376. struct stratix10_clock_data *clk_data;
  377. clk_data = __socfpga_s10_clk_init(pdev, STRATIX10_NUM_CLKS);
  378. if (IS_ERR(clk_data))
  379. return PTR_ERR(clk_data);
  380. s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
  381. s10_clk_register_c_perip(s10_main_perip_c_clks,
  382. ARRAY_SIZE(s10_main_perip_c_clks), clk_data);
  383. s10_clk_register_cnt_perip(s10_main_perip_cnt_clks,
  384. ARRAY_SIZE(s10_main_perip_cnt_clks),
  385. clk_data);
  386. s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks),
  387. clk_data);
  388. return 0;
  389. }
  390. static int s10_clkmgr_probe(struct platform_device *pdev)
  391. {
  392. return s10_clkmgr_init(pdev);
  393. }
  394. static const struct of_device_id stratix10_clkmgr_match_table[] = {
  395. { .compatible = "intel,stratix10-clkmgr",
  396. .data = s10_clkmgr_init },
  397. { }
  398. };
  399. static struct platform_driver stratix10_clkmgr_driver = {
  400. .probe = s10_clkmgr_probe,
  401. .driver = {
  402. .name = "stratix10-clkmgr",
  403. .suppress_bind_attrs = true,
  404. .of_match_table = stratix10_clkmgr_match_table,
  405. },
  406. };
  407. static int __init s10_clk_init(void)
  408. {
  409. return platform_driver_register(&stratix10_clkmgr_driver);
  410. }
  411. core_initcall(s10_clk_init);