clk-pll.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2011-2012 Calxeda, Inc.
  4. * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
  5. *
  6. * Based from clk-highbank.c
  7. */
  8. #include <linux/slab.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/io.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include "clk.h"
  14. /* Clock bypass bits */
  15. #define MAINPLL_BYPASS (1<<0)
  16. #define SDRAMPLL_BYPASS (1<<1)
  17. #define SDRAMPLL_SRC_BYPASS (1<<2)
  18. #define PERPLL_BYPASS (1<<3)
  19. #define PERPLL_SRC_BYPASS (1<<4)
  20. #define SOCFPGA_PLL_BG_PWRDWN 0
  21. #define SOCFPGA_PLL_EXT_ENA 1
  22. #define SOCFPGA_PLL_PWR_DOWN 2
  23. #define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8
  24. #define SOCFPGA_PLL_DIVF_SHIFT 3
  25. #define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
  26. #define SOCFPGA_PLL_DIVQ_SHIFT 16
  27. #define CLK_MGR_PLL_CLK_SRC_SHIFT 22
  28. #define CLK_MGR_PLL_CLK_SRC_MASK 0x3
  29. #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
  30. void __iomem *clk_mgr_base_addr;
  31. static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
  32. unsigned long parent_rate)
  33. {
  34. struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
  35. unsigned long divf, divq, reg;
  36. unsigned long long vco_freq;
  37. unsigned long bypass;
  38. reg = readl(socfpgaclk->hw.reg);
  39. bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
  40. if (bypass & MAINPLL_BYPASS)
  41. return parent_rate;
  42. divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
  43. divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
  44. vco_freq = (unsigned long long)parent_rate * (divf + 1);
  45. do_div(vco_freq, (1 + divq));
  46. return (unsigned long)vco_freq;
  47. }
  48. static u8 clk_pll_get_parent(struct clk_hw *hwclk)
  49. {
  50. u32 pll_src;
  51. struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
  52. pll_src = readl(socfpgaclk->hw.reg);
  53. return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
  54. CLK_MGR_PLL_CLK_SRC_MASK;
  55. }
  56. static const struct clk_ops clk_pll_ops = {
  57. .recalc_rate = clk_pll_recalc_rate,
  58. .get_parent = clk_pll_get_parent,
  59. };
  60. static __init struct clk *__socfpga_pll_init(struct device_node *node,
  61. const struct clk_ops *ops)
  62. {
  63. u32 reg;
  64. struct clk *clk;
  65. struct socfpga_pll *pll_clk;
  66. const char *clk_name = node->name;
  67. const char *parent_name[SOCFPGA_MAX_PARENTS];
  68. struct clk_init_data init;
  69. struct device_node *clkmgr_np;
  70. int rc;
  71. of_property_read_u32(node, "reg", &reg);
  72. pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
  73. if (WARN_ON(!pll_clk))
  74. return NULL;
  75. clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
  76. clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
  77. of_node_put(clkmgr_np);
  78. BUG_ON(!clk_mgr_base_addr);
  79. pll_clk->hw.reg = clk_mgr_base_addr + reg;
  80. of_property_read_string(node, "clock-output-names", &clk_name);
  81. init.name = clk_name;
  82. init.ops = ops;
  83. init.flags = 0;
  84. init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
  85. init.parent_names = parent_name;
  86. pll_clk->hw.hw.init = &init;
  87. pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
  88. clk = clk_register(NULL, &pll_clk->hw.hw);
  89. if (WARN_ON(IS_ERR(clk))) {
  90. kfree(pll_clk);
  91. return NULL;
  92. }
  93. rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
  94. return clk;
  95. }
  96. void __init socfpga_pll_init(struct device_node *node)
  97. {
  98. __socfpga_pll_init(node, &clk_pll_ops);
  99. }