clk-pll-s10.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017, Intel Corporation
  4. */
  5. #include <linux/slab.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/io.h>
  8. #include "stratix10-clk.h"
  9. #include "clk.h"
  10. /* Clock Manager offsets */
  11. #define CLK_MGR_PLL_CLK_SRC_SHIFT 16
  12. #define CLK_MGR_PLL_CLK_SRC_MASK 0x3
  13. /* PLL Clock enable bits */
  14. #define SOCFPGA_PLL_POWER 0
  15. #define SOCFPGA_PLL_RESET_MASK 0x2
  16. #define SOCFPGA_PLL_REFDIV_MASK 0x00003F00
  17. #define SOCFPGA_PLL_REFDIV_SHIFT 8
  18. #define SOCFPGA_PLL_AREFDIV_MASK 0x00000F00
  19. #define SOCFPGA_PLL_DREFDIV_MASK 0x00003000
  20. #define SOCFPGA_PLL_DREFDIV_SHIFT 12
  21. #define SOCFPGA_PLL_MDIV_MASK 0xFF000000
  22. #define SOCFPGA_PLL_MDIV_SHIFT 24
  23. #define SOCFPGA_AGILEX_PLL_MDIV_MASK 0x000003FF
  24. #define SWCTRLBTCLKSEL_MASK 0x200
  25. #define SWCTRLBTCLKSEL_SHIFT 9
  26. #define SOCFPGA_BOOT_CLK "boot_clk"
  27. #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
  28. static unsigned long agilex_clk_pll_recalc_rate(struct clk_hw *hwclk,
  29. unsigned long parent_rate)
  30. {
  31. struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
  32. unsigned long arefdiv, reg, mdiv;
  33. unsigned long long vco_freq;
  34. /* read VCO1 reg for numerator and denominator */
  35. reg = readl(socfpgaclk->hw.reg);
  36. arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
  37. vco_freq = (unsigned long long)parent_rate / arefdiv;
  38. /* Read mdiv and fdiv from the fdbck register */
  39. reg = readl(socfpgaclk->hw.reg + 0x24);
  40. mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK;
  41. vco_freq = (unsigned long long)vco_freq * mdiv;
  42. return (unsigned long)vco_freq;
  43. }
  44. static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
  45. unsigned long parent_rate)
  46. {
  47. struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
  48. unsigned long mdiv;
  49. unsigned long refdiv;
  50. unsigned long reg;
  51. unsigned long long vco_freq;
  52. /* read VCO1 reg for numerator and denominator */
  53. reg = readl(socfpgaclk->hw.reg);
  54. refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
  55. vco_freq = parent_rate;
  56. do_div(vco_freq, refdiv);
  57. /* Read mdiv and fdiv from the fdbck register */
  58. reg = readl(socfpgaclk->hw.reg + 0x4);
  59. mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
  60. vco_freq = (unsigned long long)vco_freq * (mdiv + 6);
  61. return (unsigned long)vco_freq;
  62. }
  63. static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
  64. unsigned long parent_rate)
  65. {
  66. struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
  67. u32 div = 1;
  68. div = ((readl(socfpgaclk->hw.reg) &
  69. SWCTRLBTCLKSEL_MASK) >>
  70. SWCTRLBTCLKSEL_SHIFT);
  71. div += 1;
  72. return parent_rate /= div;
  73. }
  74. static u8 clk_pll_get_parent(struct clk_hw *hwclk)
  75. {
  76. struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
  77. u32 pll_src;
  78. pll_src = readl(socfpgaclk->hw.reg);
  79. return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
  80. CLK_MGR_PLL_CLK_SRC_MASK;
  81. }
  82. static u8 clk_boot_get_parent(struct clk_hw *hwclk)
  83. {
  84. struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
  85. u32 pll_src;
  86. pll_src = readl(socfpgaclk->hw.reg);
  87. return (pll_src >> SWCTRLBTCLKSEL_SHIFT) &
  88. SWCTRLBTCLKSEL_MASK;
  89. }
  90. static int clk_pll_prepare(struct clk_hw *hwclk)
  91. {
  92. struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
  93. u32 reg;
  94. /* Bring PLL out of reset */
  95. reg = readl(socfpgaclk->hw.reg);
  96. reg |= SOCFPGA_PLL_RESET_MASK;
  97. writel(reg, socfpgaclk->hw.reg);
  98. return 0;
  99. }
  100. static const struct clk_ops agilex_clk_pll_ops = {
  101. .recalc_rate = agilex_clk_pll_recalc_rate,
  102. .get_parent = clk_pll_get_parent,
  103. .prepare = clk_pll_prepare,
  104. };
  105. static const struct clk_ops clk_pll_ops = {
  106. .recalc_rate = clk_pll_recalc_rate,
  107. .get_parent = clk_pll_get_parent,
  108. .prepare = clk_pll_prepare,
  109. };
  110. static const struct clk_ops clk_boot_ops = {
  111. .recalc_rate = clk_boot_clk_recalc_rate,
  112. .get_parent = clk_boot_get_parent,
  113. .prepare = clk_pll_prepare,
  114. };
  115. struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
  116. void __iomem *reg)
  117. {
  118. struct clk *clk;
  119. struct socfpga_pll *pll_clk;
  120. struct clk_init_data init;
  121. const char *name = clks->name;
  122. pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
  123. if (WARN_ON(!pll_clk))
  124. return NULL;
  125. pll_clk->hw.reg = reg + clks->offset;
  126. if (streq(name, SOCFPGA_BOOT_CLK))
  127. init.ops = &clk_boot_ops;
  128. else
  129. init.ops = &clk_pll_ops;
  130. init.name = name;
  131. init.flags = clks->flags;
  132. init.num_parents = clks->num_parents;
  133. init.parent_names = NULL;
  134. init.parent_data = clks->parent_data;
  135. pll_clk->hw.hw.init = &init;
  136. pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
  137. clk = clk_register(NULL, &pll_clk->hw.hw);
  138. if (WARN_ON(IS_ERR(clk))) {
  139. kfree(pll_clk);
  140. return NULL;
  141. }
  142. return clk;
  143. }
  144. struct clk *agilex_register_pll(const struct stratix10_pll_clock *clks,
  145. void __iomem *reg)
  146. {
  147. struct clk *clk;
  148. struct socfpga_pll *pll_clk;
  149. struct clk_init_data init;
  150. const char *name = clks->name;
  151. pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
  152. if (WARN_ON(!pll_clk))
  153. return NULL;
  154. pll_clk->hw.reg = reg + clks->offset;
  155. if (streq(name, SOCFPGA_BOOT_CLK))
  156. init.ops = &clk_boot_ops;
  157. else
  158. init.ops = &agilex_clk_pll_ops;
  159. init.name = name;
  160. init.flags = clks->flags;
  161. init.num_parents = clks->num_parents;
  162. init.parent_names = NULL;
  163. init.parent_data = clks->parent_data;
  164. pll_clk->hw.hw.init = &init;
  165. pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
  166. clk = clk_register(NULL, &pll_clk->hw.hw);
  167. if (WARN_ON(IS_ERR(clk))) {
  168. kfree(pll_clk);
  169. return NULL;
  170. }
  171. return clk;
  172. }