clk-gate-s10.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017, Intel Corporation
  4. */
  5. #include <linux/clk-provider.h>
  6. #include <linux/io.h>
  7. #include <linux/slab.h>
  8. #include "stratix10-clk.h"
  9. #include "clk.h"
  10. #define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk"
  11. #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
  12. static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
  13. unsigned long parent_rate)
  14. {
  15. struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
  16. u32 div = 1, val;
  17. if (socfpgaclk->fixed_div) {
  18. div = socfpgaclk->fixed_div;
  19. } else if (socfpgaclk->div_reg) {
  20. val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
  21. val &= GENMASK(socfpgaclk->width - 1, 0);
  22. div = (1 << val);
  23. }
  24. return parent_rate / div;
  25. }
  26. static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
  27. unsigned long parent_rate)
  28. {
  29. struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
  30. u32 div = 1, val;
  31. val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
  32. val &= GENMASK(socfpgaclk->width - 1, 0);
  33. div = (1 << val);
  34. div = div ? 4 : 1;
  35. return parent_rate / div;
  36. }
  37. static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
  38. {
  39. struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
  40. u32 mask;
  41. u8 parent = 0;
  42. if (socfpgaclk->bypass_reg) {
  43. mask = (0x1 << socfpgaclk->bypass_shift);
  44. parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
  45. socfpgaclk->bypass_shift);
  46. }
  47. return parent;
  48. }
  49. static struct clk_ops gateclk_ops = {
  50. .recalc_rate = socfpga_gate_clk_recalc_rate,
  51. .get_parent = socfpga_gate_get_parent,
  52. };
  53. static const struct clk_ops dbgclk_ops = {
  54. .recalc_rate = socfpga_dbg_clk_recalc_rate,
  55. .get_parent = socfpga_gate_get_parent,
  56. };
  57. struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
  58. {
  59. struct clk *clk;
  60. struct socfpga_gate_clk *socfpga_clk;
  61. struct clk_init_data init;
  62. const char *parent_name = clks->parent_name;
  63. socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
  64. if (!socfpga_clk)
  65. return NULL;
  66. socfpga_clk->hw.reg = regbase + clks->gate_reg;
  67. socfpga_clk->hw.bit_idx = clks->gate_idx;
  68. gateclk_ops.enable = clk_gate_ops.enable;
  69. gateclk_ops.disable = clk_gate_ops.disable;
  70. socfpga_clk->fixed_div = clks->fixed_div;
  71. if (clks->div_reg)
  72. socfpga_clk->div_reg = regbase + clks->div_reg;
  73. else
  74. socfpga_clk->div_reg = NULL;
  75. socfpga_clk->width = clks->div_width;
  76. socfpga_clk->shift = clks->div_offset;
  77. if (clks->bypass_reg)
  78. socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
  79. else
  80. socfpga_clk->bypass_reg = NULL;
  81. socfpga_clk->bypass_shift = clks->bypass_shift;
  82. if (streq(clks->name, "cs_pdbg_clk"))
  83. init.ops = &dbgclk_ops;
  84. else
  85. init.ops = &gateclk_ops;
  86. init.name = clks->name;
  87. init.flags = clks->flags;
  88. init.num_parents = clks->num_parents;
  89. init.parent_names = parent_name ? &parent_name : NULL;
  90. if (init.parent_names == NULL)
  91. init.parent_data = clks->parent_data;
  92. socfpga_clk->hw.hw.init = &init;
  93. clk = clk_register(NULL, &socfpga_clk->hw.hw);
  94. if (WARN_ON(IS_ERR(clk))) {
  95. kfree(socfpga_clk);
  96. return NULL;
  97. }
  98. return clk;
  99. }