clk-gate-a10.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Altera Corporation. All rights reserved
  4. */
  5. #include <linux/slab.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/io.h>
  8. #include <linux/mfd/syscon.h>
  9. #include <linux/of.h>
  10. #include <linux/regmap.h>
  11. #include "clk.h"
  12. #define streq(a, b) (strcmp((a), (b)) == 0)
  13. #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
  14. /* SDMMC Group for System Manager defines */
  15. #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x28
  16. static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
  17. unsigned long parent_rate)
  18. {
  19. struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
  20. u32 div = 1, val;
  21. if (socfpgaclk->fixed_div)
  22. div = socfpgaclk->fixed_div;
  23. else if (socfpgaclk->div_reg) {
  24. val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
  25. val &= GENMASK(socfpgaclk->width - 1, 0);
  26. div = (1 << val);
  27. }
  28. return parent_rate / div;
  29. }
  30. static int socfpga_clk_prepare(struct clk_hw *hwclk)
  31. {
  32. struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
  33. int i;
  34. u32 hs_timing;
  35. u32 clk_phase[2];
  36. if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
  37. for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
  38. switch (socfpgaclk->clk_phase[i]) {
  39. case 0:
  40. clk_phase[i] = 0;
  41. break;
  42. case 45:
  43. clk_phase[i] = 1;
  44. break;
  45. case 90:
  46. clk_phase[i] = 2;
  47. break;
  48. case 135:
  49. clk_phase[i] = 3;
  50. break;
  51. case 180:
  52. clk_phase[i] = 4;
  53. break;
  54. case 225:
  55. clk_phase[i] = 5;
  56. break;
  57. case 270:
  58. clk_phase[i] = 6;
  59. break;
  60. case 315:
  61. clk_phase[i] = 7;
  62. break;
  63. default:
  64. clk_phase[i] = 0;
  65. break;
  66. }
  67. }
  68. hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
  69. if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
  70. regmap_write(socfpgaclk->sys_mgr_base_addr,
  71. SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);
  72. else
  73. pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n",
  74. __func__);
  75. }
  76. return 0;
  77. }
  78. static struct clk_ops gateclk_ops = {
  79. .prepare = socfpga_clk_prepare,
  80. .recalc_rate = socfpga_gate_clk_recalc_rate,
  81. };
  82. static void __init __socfpga_gate_init(struct device_node *node,
  83. const struct clk_ops *ops)
  84. {
  85. u32 clk_gate[2];
  86. u32 div_reg[3];
  87. u32 clk_phase[2];
  88. u32 fixed_div;
  89. struct clk *clk;
  90. struct socfpga_gate_clk *socfpga_clk;
  91. const char *clk_name = node->name;
  92. const char *parent_name[SOCFPGA_MAX_PARENTS];
  93. struct clk_init_data init;
  94. int rc;
  95. socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
  96. if (WARN_ON(!socfpga_clk))
  97. return;
  98. rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
  99. if (rc)
  100. clk_gate[0] = 0;
  101. if (clk_gate[0]) {
  102. socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0];
  103. socfpga_clk->hw.bit_idx = clk_gate[1];
  104. gateclk_ops.enable = clk_gate_ops.enable;
  105. gateclk_ops.disable = clk_gate_ops.disable;
  106. }
  107. rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
  108. if (rc)
  109. socfpga_clk->fixed_div = 0;
  110. else
  111. socfpga_clk->fixed_div = fixed_div;
  112. rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
  113. if (!rc) {
  114. socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];
  115. socfpga_clk->shift = div_reg[1];
  116. socfpga_clk->width = div_reg[2];
  117. } else {
  118. socfpga_clk->div_reg = NULL;
  119. }
  120. rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
  121. if (!rc) {
  122. socfpga_clk->clk_phase[0] = clk_phase[0];
  123. socfpga_clk->clk_phase[1] = clk_phase[1];
  124. socfpga_clk->sys_mgr_base_addr =
  125. syscon_regmap_lookup_by_compatible("altr,sys-mgr");
  126. if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) {
  127. pr_err("%s: failed to find altr,sys-mgr regmap!\n",
  128. __func__);
  129. kfree(socfpga_clk);
  130. return;
  131. }
  132. }
  133. of_property_read_string(node, "clock-output-names", &clk_name);
  134. init.name = clk_name;
  135. init.ops = ops;
  136. init.flags = 0;
  137. init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
  138. init.parent_names = parent_name;
  139. socfpga_clk->hw.hw.init = &init;
  140. clk = clk_register(NULL, &socfpga_clk->hw.hw);
  141. if (WARN_ON(IS_ERR(clk))) {
  142. kfree(socfpga_clk);
  143. return;
  144. }
  145. rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
  146. if (WARN_ON(rc))
  147. return;
  148. }
  149. void __init socfpga_a10_gate_init(struct device_node *node)
  150. {
  151. __socfpga_gate_init(node, &gateclk_ops);
  152. }