clk-agilex.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019, Intel Corporation
  4. */
  5. #include <linux/slab.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/of_device.h>
  8. #include <linux/of_address.h>
  9. #include <linux/platform_device.h>
  10. #include <dt-bindings/clock/agilex-clock.h>
  11. #include "stratix10-clk.h"
  12. static const struct clk_parent_data pll_mux[] = {
  13. { .fw_name = "osc1",
  14. .name = "osc1", },
  15. { .fw_name = "cb-intosc-hs-div2-clk",
  16. .name = "cb-intosc-hs-div2-clk", },
  17. { .fw_name = "f2s-free-clk",
  18. .name = "f2s-free-clk", },
  19. };
  20. static const struct clk_parent_data boot_mux[] = {
  21. { .fw_name = "osc1",
  22. .name = "osc1", },
  23. { .fw_name = "cb-intosc-hs-div2-clk",
  24. .name = "cb-intosc-hs-div2-clk", },
  25. };
  26. static const struct clk_parent_data mpu_free_mux[] = {
  27. { .fw_name = "main_pll_c0",
  28. .name = "main_pll_c0", },
  29. { .fw_name = "peri_pll_c0",
  30. .name = "peri_pll_c0", },
  31. { .fw_name = "osc1",
  32. .name = "osc1", },
  33. { .fw_name = "cb-intosc-hs-div2-clk",
  34. .name = "cb-intosc-hs-div2-clk", },
  35. { .fw_name = "f2s-free-clk",
  36. .name = "f2s-free-clk", },
  37. };
  38. static const struct clk_parent_data noc_free_mux[] = {
  39. { .fw_name = "main_pll_c1",
  40. .name = "main_pll_c1", },
  41. { .fw_name = "peri_pll_c1",
  42. .name = "peri_pll_c1", },
  43. { .fw_name = "osc1",
  44. .name = "osc1", },
  45. { .fw_name = "cb-intosc-hs-div2-clk",
  46. .name = "cb-intosc-hs-div2-clk", },
  47. { .fw_name = "f2s-free-clk",
  48. .name = "f2s-free-clk", },
  49. };
  50. static const struct clk_parent_data emaca_free_mux[] = {
  51. { .fw_name = "main_pll_c2",
  52. .name = "main_pll_c2", },
  53. { .fw_name = "peri_pll_c2",
  54. .name = "peri_pll_c2", },
  55. { .fw_name = "osc1",
  56. .name = "osc1", },
  57. { .fw_name = "cb-intosc-hs-div2-clk",
  58. .name = "cb-intosc-hs-div2-clk", },
  59. { .fw_name = "f2s-free-clk",
  60. .name = "f2s-free-clk", },
  61. };
  62. static const struct clk_parent_data emacb_free_mux[] = {
  63. { .fw_name = "main_pll_c3",
  64. .name = "main_pll_c3", },
  65. { .fw_name = "peri_pll_c3",
  66. .name = "peri_pll_c3", },
  67. { .fw_name = "osc1",
  68. .name = "osc1", },
  69. { .fw_name = "cb-intosc-hs-div2-clk",
  70. .name = "cb-intosc-hs-div2-clk", },
  71. { .fw_name = "f2s-free-clk",
  72. .name = "f2s-free-clk", },
  73. };
  74. static const struct clk_parent_data emac_ptp_free_mux[] = {
  75. { .fw_name = "main_pll_c3",
  76. .name = "main_pll_c3", },
  77. { .fw_name = "peri_pll_c3",
  78. .name = "peri_pll_c3", },
  79. { .fw_name = "osc1",
  80. .name = "osc1", },
  81. { .fw_name = "cb-intosc-hs-div2-clk",
  82. .name = "cb-intosc-hs-div2-clk", },
  83. { .fw_name = "f2s-free-clk",
  84. .name = "f2s-free-clk", },
  85. };
  86. static const struct clk_parent_data gpio_db_free_mux[] = {
  87. { .fw_name = "main_pll_c3",
  88. .name = "main_pll_c3", },
  89. { .fw_name = "peri_pll_c3",
  90. .name = "peri_pll_c3", },
  91. { .fw_name = "osc1",
  92. .name = "osc1", },
  93. { .fw_name = "cb-intosc-hs-div2-clk",
  94. .name = "cb-intosc-hs-div2-clk", },
  95. { .fw_name = "f2s-free-clk",
  96. .name = "f2s-free-clk", },
  97. };
  98. static const struct clk_parent_data psi_ref_free_mux[] = {
  99. { .fw_name = "main_pll_c2",
  100. .name = "main_pll_c2", },
  101. { .fw_name = "peri_pll_c2",
  102. .name = "peri_pll_c2", },
  103. { .fw_name = "osc1",
  104. .name = "osc1", },
  105. { .fw_name = "cb-intosc-hs-div2-clk",
  106. .name = "cb-intosc-hs-div2-clk", },
  107. { .fw_name = "f2s-free-clk",
  108. .name = "f2s-free-clk", },
  109. };
  110. static const struct clk_parent_data sdmmc_free_mux[] = {
  111. { .fw_name = "main_pll_c3",
  112. .name = "main_pll_c3", },
  113. { .fw_name = "peri_pll_c3",
  114. .name = "peri_pll_c3", },
  115. { .fw_name = "osc1",
  116. .name = "osc1", },
  117. { .fw_name = "cb-intosc-hs-div2-clk",
  118. .name = "cb-intosc-hs-div2-clk", },
  119. { .fw_name = "f2s-free-clk",
  120. .name = "f2s-free-clk", },
  121. };
  122. static const struct clk_parent_data s2f_usr0_free_mux[] = {
  123. { .fw_name = "main_pll_c2",
  124. .name = "main_pll_c2", },
  125. { .fw_name = "peri_pll_c2",
  126. .name = "peri_pll_c2", },
  127. { .fw_name = "osc1",
  128. .name = "osc1", },
  129. { .fw_name = "cb-intosc-hs-div2-clk",
  130. .name = "cb-intosc-hs-div2-clk", },
  131. { .fw_name = "f2s-free-clk",
  132. .name = "f2s-free-clk", },
  133. };
  134. static const struct clk_parent_data s2f_usr1_free_mux[] = {
  135. { .fw_name = "main_pll_c2",
  136. .name = "main_pll_c2", },
  137. { .fw_name = "peri_pll_c2",
  138. .name = "peri_pll_c2", },
  139. { .fw_name = "osc1",
  140. .name = "osc1", },
  141. { .fw_name = "cb-intosc-hs-div2-clk",
  142. .name = "cb-intosc-hs-div2-clk", },
  143. { .fw_name = "f2s-free-clk",
  144. .name = "f2s-free-clk", },
  145. };
  146. static const struct clk_parent_data mpu_mux[] = {
  147. { .fw_name = "mpu_free_clk",
  148. .name = "mpu_free_clk", },
  149. { .fw_name = "boot_clk",
  150. .name = "boot_clk", },
  151. };
  152. static const struct clk_parent_data emac_mux[] = {
  153. { .fw_name = "emaca_free_clk",
  154. .name = "emaca_free_clk", },
  155. { .fw_name = "emacb_free_clk",
  156. .name = "emacb_free_clk", },
  157. };
  158. static const struct clk_parent_data noc_mux[] = {
  159. { .fw_name = "noc_free_clk",
  160. .name = "noc_free_clk", },
  161. { .fw_name = "boot_clk",
  162. .name = "boot_clk", },
  163. };
  164. static const struct clk_parent_data sdmmc_mux[] = {
  165. { .fw_name = "sdmmc_free_clk",
  166. .name = "sdmmc_free_clk", },
  167. { .fw_name = "boot_clk",
  168. .name = "boot_clk", },
  169. };
  170. static const struct clk_parent_data s2f_user0_mux[] = {
  171. { .fw_name = "s2f_user0_free_clk",
  172. .name = "s2f_user0_free_clk", },
  173. { .fw_name = "boot_clk",
  174. .name = "boot_clk", },
  175. };
  176. static const struct clk_parent_data s2f_user1_mux[] = {
  177. { .fw_name = "s2f_user1_free_clk",
  178. .name = "s2f_user1_free_clk", },
  179. { .fw_name = "boot_clk",
  180. .name = "boot_clk", },
  181. };
  182. static const struct clk_parent_data psi_mux[] = {
  183. { .fw_name = "psi_ref_free_clk",
  184. .name = "psi_ref_free_clk", },
  185. { .fw_name = "boot_clk",
  186. .name = "boot_clk", },
  187. };
  188. static const struct clk_parent_data gpio_db_mux[] = {
  189. { .fw_name = "gpio_db_free_clk",
  190. .name = "gpio_db_free_clk", },
  191. { .fw_name = "boot_clk",
  192. .name = "boot_clk", },
  193. };
  194. static const struct clk_parent_data emac_ptp_mux[] = {
  195. { .fw_name = "emac_ptp_free_clk",
  196. .name = "emac_ptp_free_clk", },
  197. { .fw_name = "boot_clk",
  198. .name = "boot_clk", },
  199. };
  200. /* clocks in AO (always on) controller */
  201. static const struct stratix10_pll_clock agilex_pll_clks[] = {
  202. { AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
  203. 0x0},
  204. { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
  205. 0, 0x48},
  206. { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
  207. 0, 0x9c},
  208. };
  209. static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
  210. { AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
  211. { AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
  212. { AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x64},
  213. { AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x68},
  214. { AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xAC},
  215. { AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xB0},
  216. { AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xB8},
  217. { AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xBC},
  218. };
  219. static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
  220. { AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
  221. 0, 0x3C, 0, 0, 0},
  222. { AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
  223. 0, 0x40, 0, 0, 0},
  224. { AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
  225. 0, 4, 0x30, 1},
  226. { AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
  227. 0, 0xD4, 0, 0x88, 0},
  228. { AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
  229. 0, 0xD8, 0, 0x88, 1},
  230. { AGILEX_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
  231. ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2},
  232. { AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
  233. ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3},
  234. { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
  235. ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0, 0},
  236. { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
  237. ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30, 2},
  238. { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
  239. ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5},
  240. { AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
  241. ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6},
  242. };
  243. static const struct stratix10_gate_clock agilex_gate_clks[] = {
  244. { AGILEX_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x24,
  245. 0, 0, 0, 0, 0x30, 0, 0},
  246. { AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24,
  247. 0, 0, 0, 0, 0, 0, 4},
  248. { AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24,
  249. 0, 0, 0, 0, 0, 0, 2},
  250. { AGILEX_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
  251. 1, 0x44, 0, 2, 0x30, 1, 0},
  252. { AGILEX_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
  253. 2, 0x44, 8, 2, 0x30, 1, 0},
  254. /*
  255. * The l4_sp_clk feeds a 100 MHz clock to various peripherals, one of them
  256. * being the SP timers, thus cannot get gated.
  257. */
  258. { AGILEX_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x24,
  259. 3, 0x44, 16, 2, 0x30, 1, 0},
  260. { AGILEX_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
  261. 4, 0x44, 24, 2, 0x30, 1, 0},
  262. { AGILEX_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
  263. 4, 0x44, 26, 2, 0x30, 1, 0},
  264. { AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24,
  265. 4, 0x44, 28, 1, 0, 0, 0},
  266. { AGILEX_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
  267. 5, 0, 0, 0, 0x30, 1, 0},
  268. { AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
  269. 0, 0, 0, 0, 0x94, 26, 0},
  270. { AGILEX_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
  271. 1, 0, 0, 0, 0x94, 27, 0},
  272. { AGILEX_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
  273. 2, 0, 0, 0, 0x94, 28, 0},
  274. { AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, ARRAY_SIZE(emac_ptp_mux), 0, 0x7C,
  275. 3, 0, 0, 0, 0x88, 2, 0},
  276. { AGILEX_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, ARRAY_SIZE(gpio_db_mux), 0, 0x7C,
  277. 4, 0x98, 0, 16, 0x88, 3, 0},
  278. { AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C,
  279. 5, 0, 0, 0, 0x88, 4, 4},
  280. { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, ARRAY_SIZE(s2f_user0_mux), 0, 0x24,
  281. 6, 0, 0, 0, 0x30, 2, 0},
  282. { AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C,
  283. 6, 0, 0, 0, 0x88, 5, 0},
  284. { AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C,
  285. 7, 0, 0, 0, 0x88, 6, 0},
  286. { AGILEX_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
  287. 8, 0, 0, 0, 0, 0, 0},
  288. { AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
  289. 9, 0, 0, 0, 0, 0, 0},
  290. { AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
  291. 10, 0, 0, 0, 0, 0, 0},
  292. { AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
  293. 10, 0, 0, 0, 0, 0, 4},
  294. { AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
  295. 10, 0, 0, 0, 0, 0, 4},
  296. };
  297. static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
  298. int nums, struct stratix10_clock_data *data)
  299. {
  300. struct clk *clk;
  301. void __iomem *base = data->base;
  302. int i;
  303. for (i = 0; i < nums; i++) {
  304. clk = s10_register_periph(&clks[i], base);
  305. if (IS_ERR(clk)) {
  306. pr_err("%s: failed to register clock %s\n",
  307. __func__, clks[i].name);
  308. continue;
  309. }
  310. data->clk_data.clks[clks[i].id] = clk;
  311. }
  312. return 0;
  313. }
  314. static int agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
  315. int nums, struct stratix10_clock_data *data)
  316. {
  317. struct clk *clk;
  318. void __iomem *base = data->base;
  319. int i;
  320. for (i = 0; i < nums; i++) {
  321. clk = s10_register_cnt_periph(&clks[i], base);
  322. if (IS_ERR(clk)) {
  323. pr_err("%s: failed to register clock %s\n",
  324. __func__, clks[i].name);
  325. continue;
  326. }
  327. data->clk_data.clks[clks[i].id] = clk;
  328. }
  329. return 0;
  330. }
  331. static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks, int nums, struct stratix10_clock_data *data)
  332. {
  333. struct clk *clk;
  334. void __iomem *base = data->base;
  335. int i;
  336. for (i = 0; i < nums; i++) {
  337. clk = s10_register_gate(&clks[i], base);
  338. if (IS_ERR(clk)) {
  339. pr_err("%s: failed to register clock %s\n",
  340. __func__, clks[i].name);
  341. continue;
  342. }
  343. data->clk_data.clks[clks[i].id] = clk;
  344. }
  345. return 0;
  346. }
  347. static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
  348. int nums, struct stratix10_clock_data *data)
  349. {
  350. struct clk *clk;
  351. void __iomem *base = data->base;
  352. int i;
  353. for (i = 0; i < nums; i++) {
  354. clk = agilex_register_pll(&clks[i], base);
  355. if (IS_ERR(clk)) {
  356. pr_err("%s: failed to register clock %s\n",
  357. __func__, clks[i].name);
  358. continue;
  359. }
  360. data->clk_data.clks[clks[i].id] = clk;
  361. }
  362. return 0;
  363. }
  364. static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_device *pdev,
  365. int nr_clks)
  366. {
  367. struct device_node *np = pdev->dev.of_node;
  368. struct device *dev = &pdev->dev;
  369. struct stratix10_clock_data *clk_data;
  370. struct clk **clk_table;
  371. struct resource *res;
  372. void __iomem *base;
  373. int ret;
  374. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  375. base = devm_ioremap_resource(dev, res);
  376. if (IS_ERR(base))
  377. return ERR_CAST(base);
  378. clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
  379. if (!clk_data)
  380. return ERR_PTR(-ENOMEM);
  381. clk_data->base = base;
  382. clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
  383. if (!clk_table)
  384. return ERR_PTR(-ENOMEM);
  385. clk_data->clk_data.clks = clk_table;
  386. clk_data->clk_data.clk_num = nr_clks;
  387. ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
  388. if (ret)
  389. return ERR_PTR(ret);
  390. return clk_data;
  391. }
  392. static int agilex_clkmgr_probe(struct platform_device *pdev)
  393. {
  394. struct stratix10_clock_data *clk_data;
  395. clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
  396. if (IS_ERR(clk_data))
  397. return PTR_ERR(clk_data);
  398. agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
  399. agilex_clk_register_c_perip(agilex_main_perip_c_clks,
  400. ARRAY_SIZE(agilex_main_perip_c_clks), clk_data);
  401. agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
  402. ARRAY_SIZE(agilex_main_perip_cnt_clks),
  403. clk_data);
  404. agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
  405. clk_data);
  406. return 0;
  407. }
  408. static const struct of_device_id agilex_clkmgr_match_table[] = {
  409. { .compatible = "intel,agilex-clkmgr",
  410. .data = agilex_clkmgr_probe },
  411. { }
  412. };
  413. static struct platform_driver agilex_clkmgr_driver = {
  414. .probe = agilex_clkmgr_probe,
  415. .driver = {
  416. .name = "agilex-clkmgr",
  417. .suppress_bind_attrs = true,
  418. .of_match_table = agilex_clkmgr_match_table,
  419. },
  420. };
  421. static int __init agilex_clk_init(void)
  422. {
  423. return platform_driver_register(&agilex_clkmgr_driver);
  424. }
  425. core_initcall(agilex_clk_init);