renesas-cpg-mssr.h 6.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Renesas Clock Pulse Generator / Module Standby and Software Reset
  4. *
  5. * Copyright (C) 2015 Glider bvba
  6. */
  7. #ifndef __CLK_RENESAS_CPG_MSSR_H__
  8. #define __CLK_RENESAS_CPG_MSSR_H__
  9. /*
  10. * Definitions of CPG Core Clocks
  11. *
  12. * These include:
  13. * - Clock outputs exported to DT
  14. * - External input clocks
  15. * - Internal CPG clocks
  16. */
  17. struct cpg_core_clk {
  18. /* Common */
  19. const char *name;
  20. unsigned int id;
  21. unsigned int type;
  22. /* Depending on type */
  23. unsigned int parent; /* Core Clocks only */
  24. unsigned int div;
  25. unsigned int mult;
  26. unsigned int offset;
  27. };
  28. enum clk_types {
  29. /* Generic */
  30. CLK_TYPE_IN, /* External Clock Input */
  31. CLK_TYPE_FF, /* Fixed Factor Clock */
  32. CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
  33. CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
  34. CLK_TYPE_FR, /* Fixed Rate Clock */
  35. /* Custom definitions start here */
  36. CLK_TYPE_CUSTOM,
  37. };
  38. #define DEF_TYPE(_name, _id, _type...) \
  39. { .name = _name, .id = _id, .type = _type }
  40. #define DEF_BASE(_name, _id, _type, _parent...) \
  41. DEF_TYPE(_name, _id, _type, .parent = _parent)
  42. #define DEF_INPUT(_name, _id) \
  43. DEF_TYPE(_name, _id, CLK_TYPE_IN)
  44. #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
  45. DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
  46. #define DEF_DIV6P1(_name, _id, _parent, _offset) \
  47. DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
  48. #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
  49. DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
  50. #define DEF_RATE(_name, _id, _rate) \
  51. DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
  52. /*
  53. * Definitions of Module Clocks
  54. */
  55. struct mssr_mod_clk {
  56. const char *name;
  57. unsigned int id;
  58. unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
  59. };
  60. /* Convert from sparse base-100 to packed index space */
  61. #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
  62. #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
  63. #define DEF_MOD(_name, _mod, _parent...) \
  64. { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
  65. /* Convert from sparse base-10 to packed index space */
  66. #define MOD_CLK_PACK_10(x) ((x / 10) * 32 + (x % 10))
  67. #define MOD_CLK_ID_10(x) (MOD_CLK_BASE + MOD_CLK_PACK_10(x))
  68. #define DEF_MOD_STB(_name, _mod, _parent...) \
  69. { .name = _name, .id = MOD_CLK_ID_10(_mod), .parent = _parent }
  70. struct device_node;
  71. enum clk_reg_layout {
  72. CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
  73. CLK_REG_LAYOUT_RZ_A,
  74. CLK_REG_LAYOUT_RCAR_V3U,
  75. };
  76. /**
  77. * SoC-specific CPG/MSSR Description
  78. *
  79. * @early_core_clks: Array of Early Core Clock definitions
  80. * @num_early_core_clks: Number of entries in early_core_clks[]
  81. * @early_mod_clks: Array of Early Module Clock definitions
  82. * @num_early_mod_clks: Number of entries in early_mod_clks[]
  83. *
  84. * @core_clks: Array of Core Clock definitions
  85. * @num_core_clks: Number of entries in core_clks[]
  86. * @last_dt_core_clk: ID of the last Core Clock exported to DT
  87. * @num_total_core_clks: Total number of Core Clocks (exported + internal)
  88. *
  89. * @mod_clks: Array of Module Clock definitions
  90. * @num_mod_clks: Number of entries in mod_clks[]
  91. * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
  92. *
  93. * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
  94. * should not be disabled without a knowledgeable driver
  95. * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
  96. * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
  97. *
  98. * @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power
  99. * Management, in addition to Module Clocks
  100. * @num_core_pm_clks: Number of entries in core_pm_clks[]
  101. *
  102. * @init: Optional callback to perform SoC-specific initialization
  103. * @cpg_clk_register: Optional callback to handle special Core Clock types
  104. */
  105. struct cpg_mssr_info {
  106. /* Early Clocks */
  107. const struct cpg_core_clk *early_core_clks;
  108. unsigned int num_early_core_clks;
  109. const struct mssr_mod_clk *early_mod_clks;
  110. unsigned int num_early_mod_clks;
  111. /* Core Clocks */
  112. const struct cpg_core_clk *core_clks;
  113. unsigned int num_core_clks;
  114. unsigned int last_dt_core_clk;
  115. unsigned int num_total_core_clks;
  116. enum clk_reg_layout reg_layout;
  117. /* Module Clocks */
  118. const struct mssr_mod_clk *mod_clks;
  119. unsigned int num_mod_clks;
  120. unsigned int num_hw_mod_clks;
  121. /* Critical Module Clocks that should not be disabled */
  122. const unsigned int *crit_mod_clks;
  123. unsigned int num_crit_mod_clks;
  124. /* Core Clocks suitable for PM, in addition to the Module Clocks */
  125. const unsigned int *core_pm_clks;
  126. unsigned int num_core_pm_clks;
  127. /* Callbacks */
  128. int (*init)(struct device *dev);
  129. struct clk *(*cpg_clk_register)(struct device *dev,
  130. const struct cpg_core_clk *core,
  131. const struct cpg_mssr_info *info,
  132. struct clk **clks, void __iomem *base,
  133. struct raw_notifier_head *notifiers);
  134. };
  135. extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
  136. extern const struct cpg_mssr_info r8a7742_cpg_mssr_info;
  137. extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
  138. extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
  139. extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
  140. extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
  141. extern const struct cpg_mssr_info r8a774b1_cpg_mssr_info;
  142. extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;
  143. extern const struct cpg_mssr_info r8a774e1_cpg_mssr_info;
  144. extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
  145. extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
  146. extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
  147. extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
  148. extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
  149. extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
  150. extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
  151. extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
  152. extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
  153. extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
  154. extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
  155. extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
  156. void __init cpg_mssr_early_init(struct device_node *np,
  157. const struct cpg_mssr_info *info);
  158. /*
  159. * Helpers for fixing up clock tables depending on SoC revision
  160. */
  161. struct mssr_mod_reparent {
  162. unsigned int clk, parent;
  163. };
  164. extern void cpg_core_nullify_range(struct cpg_core_clk *core_clks,
  165. unsigned int num_core_clks,
  166. unsigned int first_clk,
  167. unsigned int last_clk);
  168. extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
  169. unsigned int num_mod_clks,
  170. const unsigned int *clks, unsigned int n);
  171. extern void mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
  172. unsigned int num_mod_clks,
  173. const struct mssr_mod_reparent *clks,
  174. unsigned int n);
  175. #endif