renesas-cpg-mssr.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas Clock Pulse Generator / Module Standby and Software Reset
  4. *
  5. * Copyright (C) 2015 Glider bvba
  6. *
  7. * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
  8. *
  9. * Copyright (C) 2013 Ideas On Board SPRL
  10. * Copyright (C) 2015 Renesas Electronics Corp.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/clk/renesas.h>
  15. #include <linux/delay.h>
  16. #include <linux/device.h>
  17. #include <linux/init.h>
  18. #include <linux/io.h>
  19. #include <linux/mod_devicetable.h>
  20. #include <linux/module.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_device.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/pm_clock.h>
  25. #include <linux/pm_domain.h>
  26. #include <linux/psci.h>
  27. #include <linux/reset-controller.h>
  28. #include <linux/slab.h>
  29. #include <dt-bindings/clock/renesas-cpg-mssr.h>
  30. #include "renesas-cpg-mssr.h"
  31. #include "clk-div6.h"
  32. #ifdef DEBUG
  33. #define WARN_DEBUG(x) WARN_ON(x)
  34. #else
  35. #define WARN_DEBUG(x) do { } while (0)
  36. #endif
  37. /*
  38. * Module Standby and Software Reset register offets.
  39. *
  40. * If the registers exist, these are valid for SH-Mobile, R-Mobile,
  41. * R-Car Gen2, R-Car Gen3, and RZ/G1.
  42. * These are NOT valid for R-Car Gen1 and RZ/A1!
  43. */
  44. /*
  45. * Module Stop Status Register offsets
  46. */
  47. static const u16 mstpsr[] = {
  48. 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
  49. 0x9A0, 0x9A4, 0x9A8, 0x9AC,
  50. };
  51. static const u16 mstpsr_for_v3u[] = {
  52. 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
  53. 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
  54. };
  55. /*
  56. * System Module Stop Control Register offsets
  57. */
  58. static const u16 smstpcr[] = {
  59. 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
  60. 0x990, 0x994, 0x998, 0x99C,
  61. };
  62. static const u16 mstpcr_for_v3u[] = {
  63. 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
  64. 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
  65. };
  66. /*
  67. * Standby Control Register offsets (RZ/A)
  68. * Base address is FRQCR register
  69. */
  70. static const u16 stbcr[] = {
  71. 0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
  72. 0x424, 0x428, 0x42C,
  73. };
  74. /*
  75. * Software Reset Register offsets
  76. */
  77. static const u16 srcr[] = {
  78. 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
  79. 0x920, 0x924, 0x928, 0x92C,
  80. };
  81. static const u16 srcr_for_v3u[] = {
  82. 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
  83. 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
  84. };
  85. /* Realtime Module Stop Control Register offsets */
  86. #define RMSTPCR(i) (smstpcr[i] - 0x20)
  87. /* Modem Module Stop Control Register offsets (r8a73a4) */
  88. #define MMSTPCR(i) (smstpcr[i] + 0x20)
  89. /* Software Reset Clearing Register offsets */
  90. static const u16 srstclr[] = {
  91. 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
  92. 0x960, 0x964, 0x968, 0x96C,
  93. };
  94. static const u16 srstclr_for_v3u[] = {
  95. 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
  96. 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
  97. };
  98. /**
  99. * Clock Pulse Generator / Module Standby and Software Reset Private Data
  100. *
  101. * @rcdev: Optional reset controller entity
  102. * @dev: CPG/MSSR device
  103. * @base: CPG/MSSR register block base address
  104. * @reg_layout: CPG/MSSR register layout
  105. * @rmw_lock: protects RMW register accesses
  106. * @np: Device node in DT for this CPG/MSSR module
  107. * @num_core_clks: Number of Core Clocks in clks[]
  108. * @num_mod_clks: Number of Module Clocks in clks[]
  109. * @last_dt_core_clk: ID of the last Core Clock exported to DT
  110. * @notifiers: Notifier chain to save/restore clock state for system resume
  111. * @status_regs: Pointer to status registers array
  112. * @control_regs: Pointer to control registers array
  113. * @reset_regs: Pointer to reset registers array
  114. * @reset_clear_regs: Pointer to reset clearing registers array
  115. * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
  116. * @smstpcr_saved[].val: Saved values of SMSTPCR[]
  117. * @clks: Array containing all Core and Module Clocks
  118. */
  119. struct cpg_mssr_priv {
  120. #ifdef CONFIG_RESET_CONTROLLER
  121. struct reset_controller_dev rcdev;
  122. #endif
  123. struct device *dev;
  124. void __iomem *base;
  125. enum clk_reg_layout reg_layout;
  126. spinlock_t rmw_lock;
  127. struct device_node *np;
  128. unsigned int num_core_clks;
  129. unsigned int num_mod_clks;
  130. unsigned int last_dt_core_clk;
  131. struct raw_notifier_head notifiers;
  132. const u16 *status_regs;
  133. const u16 *control_regs;
  134. const u16 *reset_regs;
  135. const u16 *reset_clear_regs;
  136. struct {
  137. u32 mask;
  138. u32 val;
  139. } smstpcr_saved[ARRAY_SIZE(mstpsr_for_v3u)];
  140. struct clk *clks[];
  141. };
  142. static struct cpg_mssr_priv *cpg_mssr_priv;
  143. /**
  144. * struct mstp_clock - MSTP gating clock
  145. * @hw: handle between common and hardware-specific interfaces
  146. * @index: MSTP clock number
  147. * @priv: CPG/MSSR private data
  148. */
  149. struct mstp_clock {
  150. struct clk_hw hw;
  151. u32 index;
  152. struct cpg_mssr_priv *priv;
  153. };
  154. #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
  155. static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
  156. {
  157. struct mstp_clock *clock = to_mstp_clock(hw);
  158. struct cpg_mssr_priv *priv = clock->priv;
  159. unsigned int reg = clock->index / 32;
  160. unsigned int bit = clock->index % 32;
  161. struct device *dev = priv->dev;
  162. u32 bitmask = BIT(bit);
  163. unsigned long flags;
  164. unsigned int i;
  165. u32 value;
  166. dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
  167. enable ? "ON" : "OFF");
  168. spin_lock_irqsave(&priv->rmw_lock, flags);
  169. if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
  170. value = readb(priv->base + priv->control_regs[reg]);
  171. if (enable)
  172. value &= ~bitmask;
  173. else
  174. value |= bitmask;
  175. writeb(value, priv->base + priv->control_regs[reg]);
  176. /* dummy read to ensure write has completed */
  177. readb(priv->base + priv->control_regs[reg]);
  178. barrier_data(priv->base + priv->control_regs[reg]);
  179. } else {
  180. value = readl(priv->base + priv->control_regs[reg]);
  181. if (enable)
  182. value &= ~bitmask;
  183. else
  184. value |= bitmask;
  185. writel(value, priv->base + priv->control_regs[reg]);
  186. }
  187. spin_unlock_irqrestore(&priv->rmw_lock, flags);
  188. if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
  189. return 0;
  190. for (i = 1000; i > 0; --i) {
  191. if (!(readl(priv->base + priv->status_regs[reg]) & bitmask))
  192. break;
  193. cpu_relax();
  194. }
  195. if (!i) {
  196. dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
  197. priv->base + priv->control_regs[reg], bit);
  198. return -ETIMEDOUT;
  199. }
  200. return 0;
  201. }
  202. static int cpg_mstp_clock_enable(struct clk_hw *hw)
  203. {
  204. return cpg_mstp_clock_endisable(hw, true);
  205. }
  206. static void cpg_mstp_clock_disable(struct clk_hw *hw)
  207. {
  208. cpg_mstp_clock_endisable(hw, false);
  209. }
  210. static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
  211. {
  212. struct mstp_clock *clock = to_mstp_clock(hw);
  213. struct cpg_mssr_priv *priv = clock->priv;
  214. u32 value;
  215. if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
  216. value = readb(priv->base + priv->control_regs[clock->index / 32]);
  217. else
  218. value = readl(priv->base + priv->status_regs[clock->index / 32]);
  219. return !(value & BIT(clock->index % 32));
  220. }
  221. static const struct clk_ops cpg_mstp_clock_ops = {
  222. .enable = cpg_mstp_clock_enable,
  223. .disable = cpg_mstp_clock_disable,
  224. .is_enabled = cpg_mstp_clock_is_enabled,
  225. };
  226. static
  227. struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
  228. void *data)
  229. {
  230. unsigned int clkidx = clkspec->args[1];
  231. struct cpg_mssr_priv *priv = data;
  232. struct device *dev = priv->dev;
  233. unsigned int idx;
  234. const char *type;
  235. struct clk *clk;
  236. int range_check;
  237. switch (clkspec->args[0]) {
  238. case CPG_CORE:
  239. type = "core";
  240. if (clkidx > priv->last_dt_core_clk) {
  241. dev_err(dev, "Invalid %s clock index %u\n", type,
  242. clkidx);
  243. return ERR_PTR(-EINVAL);
  244. }
  245. clk = priv->clks[clkidx];
  246. break;
  247. case CPG_MOD:
  248. type = "module";
  249. if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
  250. idx = MOD_CLK_PACK_10(clkidx);
  251. range_check = 7 - (clkidx % 10);
  252. } else {
  253. idx = MOD_CLK_PACK(clkidx);
  254. range_check = 31 - (clkidx % 100);
  255. }
  256. if (range_check < 0 || idx >= priv->num_mod_clks) {
  257. dev_err(dev, "Invalid %s clock index %u\n", type,
  258. clkidx);
  259. return ERR_PTR(-EINVAL);
  260. }
  261. clk = priv->clks[priv->num_core_clks + idx];
  262. break;
  263. default:
  264. dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
  265. return ERR_PTR(-EINVAL);
  266. }
  267. if (IS_ERR(clk))
  268. dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
  269. PTR_ERR(clk));
  270. else
  271. dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
  272. clkspec->args[0], clkspec->args[1], clk,
  273. clk_get_rate(clk));
  274. return clk;
  275. }
  276. static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
  277. const struct cpg_mssr_info *info,
  278. struct cpg_mssr_priv *priv)
  279. {
  280. struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
  281. struct device *dev = priv->dev;
  282. unsigned int id = core->id, div = core->div;
  283. const char *parent_name;
  284. WARN_DEBUG(id >= priv->num_core_clks);
  285. WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
  286. if (!core->name) {
  287. /* Skip NULLified clock */
  288. return;
  289. }
  290. switch (core->type) {
  291. case CLK_TYPE_IN:
  292. clk = of_clk_get_by_name(priv->np, core->name);
  293. break;
  294. case CLK_TYPE_FF:
  295. case CLK_TYPE_DIV6P1:
  296. case CLK_TYPE_DIV6_RO:
  297. WARN_DEBUG(core->parent >= priv->num_core_clks);
  298. parent = priv->clks[core->parent];
  299. if (IS_ERR(parent)) {
  300. clk = parent;
  301. goto fail;
  302. }
  303. parent_name = __clk_get_name(parent);
  304. if (core->type == CLK_TYPE_DIV6_RO)
  305. /* Multiply with the DIV6 register value */
  306. div *= (readl(priv->base + core->offset) & 0x3f) + 1;
  307. if (core->type == CLK_TYPE_DIV6P1) {
  308. clk = cpg_div6_register(core->name, 1, &parent_name,
  309. priv->base + core->offset,
  310. &priv->notifiers);
  311. } else {
  312. clk = clk_register_fixed_factor(NULL, core->name,
  313. parent_name, 0,
  314. core->mult, div);
  315. }
  316. break;
  317. case CLK_TYPE_FR:
  318. clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
  319. core->mult);
  320. break;
  321. default:
  322. if (info->cpg_clk_register)
  323. clk = info->cpg_clk_register(dev, core, info,
  324. priv->clks, priv->base,
  325. &priv->notifiers);
  326. else
  327. dev_err(dev, "%s has unsupported core clock type %u\n",
  328. core->name, core->type);
  329. break;
  330. }
  331. if (IS_ERR_OR_NULL(clk))
  332. goto fail;
  333. dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
  334. priv->clks[id] = clk;
  335. return;
  336. fail:
  337. dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
  338. core->name, PTR_ERR(clk));
  339. }
  340. static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
  341. const struct cpg_mssr_info *info,
  342. struct cpg_mssr_priv *priv)
  343. {
  344. struct mstp_clock *clock = NULL;
  345. struct device *dev = priv->dev;
  346. unsigned int id = mod->id;
  347. struct clk_init_data init;
  348. struct clk *parent, *clk;
  349. const char *parent_name;
  350. unsigned int i;
  351. WARN_DEBUG(id < priv->num_core_clks);
  352. WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
  353. WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
  354. WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
  355. if (!mod->name) {
  356. /* Skip NULLified clock */
  357. return;
  358. }
  359. parent = priv->clks[mod->parent];
  360. if (IS_ERR(parent)) {
  361. clk = parent;
  362. goto fail;
  363. }
  364. clock = kzalloc(sizeof(*clock), GFP_KERNEL);
  365. if (!clock) {
  366. clk = ERR_PTR(-ENOMEM);
  367. goto fail;
  368. }
  369. init.name = mod->name;
  370. init.ops = &cpg_mstp_clock_ops;
  371. init.flags = CLK_SET_RATE_PARENT;
  372. parent_name = __clk_get_name(parent);
  373. init.parent_names = &parent_name;
  374. init.num_parents = 1;
  375. clock->index = id - priv->num_core_clks;
  376. clock->priv = priv;
  377. clock->hw.init = &init;
  378. for (i = 0; i < info->num_crit_mod_clks; i++)
  379. if (id == info->crit_mod_clks[i] &&
  380. cpg_mstp_clock_is_enabled(&clock->hw)) {
  381. dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
  382. mod->name);
  383. init.flags |= CLK_IS_CRITICAL;
  384. break;
  385. }
  386. clk = clk_register(NULL, &clock->hw);
  387. if (IS_ERR(clk))
  388. goto fail;
  389. dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
  390. priv->clks[id] = clk;
  391. priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
  392. return;
  393. fail:
  394. dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
  395. mod->name, PTR_ERR(clk));
  396. kfree(clock);
  397. }
  398. struct cpg_mssr_clk_domain {
  399. struct generic_pm_domain genpd;
  400. unsigned int num_core_pm_clks;
  401. unsigned int core_pm_clks[];
  402. };
  403. static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
  404. static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
  405. struct cpg_mssr_clk_domain *pd)
  406. {
  407. unsigned int i;
  408. if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
  409. return false;
  410. switch (clkspec->args[0]) {
  411. case CPG_CORE:
  412. for (i = 0; i < pd->num_core_pm_clks; i++)
  413. if (clkspec->args[1] == pd->core_pm_clks[i])
  414. return true;
  415. return false;
  416. case CPG_MOD:
  417. return true;
  418. default:
  419. return false;
  420. }
  421. }
  422. int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
  423. {
  424. struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
  425. struct device_node *np = dev->of_node;
  426. struct of_phandle_args clkspec;
  427. struct clk *clk;
  428. int i = 0;
  429. int error;
  430. if (!pd) {
  431. dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
  432. return -EPROBE_DEFER;
  433. }
  434. while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
  435. &clkspec)) {
  436. if (cpg_mssr_is_pm_clk(&clkspec, pd))
  437. goto found;
  438. of_node_put(clkspec.np);
  439. i++;
  440. }
  441. return 0;
  442. found:
  443. clk = of_clk_get_from_provider(&clkspec);
  444. of_node_put(clkspec.np);
  445. if (IS_ERR(clk))
  446. return PTR_ERR(clk);
  447. error = pm_clk_create(dev);
  448. if (error)
  449. goto fail_put;
  450. error = pm_clk_add_clk(dev, clk);
  451. if (error)
  452. goto fail_destroy;
  453. return 0;
  454. fail_destroy:
  455. pm_clk_destroy(dev);
  456. fail_put:
  457. clk_put(clk);
  458. return error;
  459. }
  460. void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
  461. {
  462. if (!pm_clk_no_clocks(dev))
  463. pm_clk_destroy(dev);
  464. }
  465. static int __init cpg_mssr_add_clk_domain(struct device *dev,
  466. const unsigned int *core_pm_clks,
  467. unsigned int num_core_pm_clks)
  468. {
  469. struct device_node *np = dev->of_node;
  470. struct generic_pm_domain *genpd;
  471. struct cpg_mssr_clk_domain *pd;
  472. size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
  473. pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
  474. if (!pd)
  475. return -ENOMEM;
  476. pd->num_core_pm_clks = num_core_pm_clks;
  477. memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
  478. genpd = &pd->genpd;
  479. genpd->name = np->name;
  480. genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
  481. GENPD_FLAG_ACTIVE_WAKEUP;
  482. genpd->attach_dev = cpg_mssr_attach_dev;
  483. genpd->detach_dev = cpg_mssr_detach_dev;
  484. pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
  485. cpg_mssr_clk_domain = pd;
  486. of_genpd_add_provider_simple(np, genpd);
  487. return 0;
  488. }
  489. #ifdef CONFIG_RESET_CONTROLLER
  490. #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev)
  491. static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
  492. unsigned long id)
  493. {
  494. struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
  495. unsigned int reg = id / 32;
  496. unsigned int bit = id % 32;
  497. u32 bitmask = BIT(bit);
  498. dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
  499. /* Reset module */
  500. writel(bitmask, priv->base + priv->reset_regs[reg]);
  501. /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
  502. udelay(35);
  503. /* Release module from reset state */
  504. writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
  505. return 0;
  506. }
  507. static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
  508. {
  509. struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
  510. unsigned int reg = id / 32;
  511. unsigned int bit = id % 32;
  512. u32 bitmask = BIT(bit);
  513. dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
  514. writel(bitmask, priv->base + priv->reset_regs[reg]);
  515. return 0;
  516. }
  517. static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
  518. unsigned long id)
  519. {
  520. struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
  521. unsigned int reg = id / 32;
  522. unsigned int bit = id % 32;
  523. u32 bitmask = BIT(bit);
  524. dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
  525. writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
  526. return 0;
  527. }
  528. static int cpg_mssr_status(struct reset_controller_dev *rcdev,
  529. unsigned long id)
  530. {
  531. struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
  532. unsigned int reg = id / 32;
  533. unsigned int bit = id % 32;
  534. u32 bitmask = BIT(bit);
  535. return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
  536. }
  537. static const struct reset_control_ops cpg_mssr_reset_ops = {
  538. .reset = cpg_mssr_reset,
  539. .assert = cpg_mssr_assert,
  540. .deassert = cpg_mssr_deassert,
  541. .status = cpg_mssr_status,
  542. };
  543. static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
  544. const struct of_phandle_args *reset_spec)
  545. {
  546. struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
  547. unsigned int unpacked = reset_spec->args[0];
  548. unsigned int idx = MOD_CLK_PACK(unpacked);
  549. if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
  550. dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
  551. return -EINVAL;
  552. }
  553. return idx;
  554. }
  555. static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
  556. {
  557. priv->rcdev.ops = &cpg_mssr_reset_ops;
  558. priv->rcdev.of_node = priv->dev->of_node;
  559. priv->rcdev.of_reset_n_cells = 1;
  560. priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
  561. priv->rcdev.nr_resets = priv->num_mod_clks;
  562. return devm_reset_controller_register(priv->dev, &priv->rcdev);
  563. }
  564. #else /* !CONFIG_RESET_CONTROLLER */
  565. static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
  566. {
  567. return 0;
  568. }
  569. #endif /* !CONFIG_RESET_CONTROLLER */
  570. static const struct of_device_id cpg_mssr_match[] = {
  571. #ifdef CONFIG_CLK_R7S9210
  572. {
  573. .compatible = "renesas,r7s9210-cpg-mssr",
  574. .data = &r7s9210_cpg_mssr_info,
  575. },
  576. #endif
  577. #ifdef CONFIG_CLK_R8A7742
  578. {
  579. .compatible = "renesas,r8a7742-cpg-mssr",
  580. .data = &r8a7742_cpg_mssr_info,
  581. },
  582. #endif
  583. #ifdef CONFIG_CLK_R8A7743
  584. {
  585. .compatible = "renesas,r8a7743-cpg-mssr",
  586. .data = &r8a7743_cpg_mssr_info,
  587. },
  588. /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
  589. {
  590. .compatible = "renesas,r8a7744-cpg-mssr",
  591. .data = &r8a7743_cpg_mssr_info,
  592. },
  593. #endif
  594. #ifdef CONFIG_CLK_R8A7745
  595. {
  596. .compatible = "renesas,r8a7745-cpg-mssr",
  597. .data = &r8a7745_cpg_mssr_info,
  598. },
  599. #endif
  600. #ifdef CONFIG_CLK_R8A77470
  601. {
  602. .compatible = "renesas,r8a77470-cpg-mssr",
  603. .data = &r8a77470_cpg_mssr_info,
  604. },
  605. #endif
  606. #ifdef CONFIG_CLK_R8A774A1
  607. {
  608. .compatible = "renesas,r8a774a1-cpg-mssr",
  609. .data = &r8a774a1_cpg_mssr_info,
  610. },
  611. #endif
  612. #ifdef CONFIG_CLK_R8A774B1
  613. {
  614. .compatible = "renesas,r8a774b1-cpg-mssr",
  615. .data = &r8a774b1_cpg_mssr_info,
  616. },
  617. #endif
  618. #ifdef CONFIG_CLK_R8A774C0
  619. {
  620. .compatible = "renesas,r8a774c0-cpg-mssr",
  621. .data = &r8a774c0_cpg_mssr_info,
  622. },
  623. #endif
  624. #ifdef CONFIG_CLK_R8A774E1
  625. {
  626. .compatible = "renesas,r8a774e1-cpg-mssr",
  627. .data = &r8a774e1_cpg_mssr_info,
  628. },
  629. #endif
  630. #ifdef CONFIG_CLK_R8A7790
  631. {
  632. .compatible = "renesas,r8a7790-cpg-mssr",
  633. .data = &r8a7790_cpg_mssr_info,
  634. },
  635. #endif
  636. #ifdef CONFIG_CLK_R8A7791
  637. {
  638. .compatible = "renesas,r8a7791-cpg-mssr",
  639. .data = &r8a7791_cpg_mssr_info,
  640. },
  641. /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
  642. {
  643. .compatible = "renesas,r8a7793-cpg-mssr",
  644. .data = &r8a7791_cpg_mssr_info,
  645. },
  646. #endif
  647. #ifdef CONFIG_CLK_R8A7792
  648. {
  649. .compatible = "renesas,r8a7792-cpg-mssr",
  650. .data = &r8a7792_cpg_mssr_info,
  651. },
  652. #endif
  653. #ifdef CONFIG_CLK_R8A7794
  654. {
  655. .compatible = "renesas,r8a7794-cpg-mssr",
  656. .data = &r8a7794_cpg_mssr_info,
  657. },
  658. #endif
  659. #ifdef CONFIG_CLK_R8A7795
  660. {
  661. .compatible = "renesas,r8a7795-cpg-mssr",
  662. .data = &r8a7795_cpg_mssr_info,
  663. },
  664. #endif
  665. #ifdef CONFIG_CLK_R8A77960
  666. {
  667. .compatible = "renesas,r8a7796-cpg-mssr",
  668. .data = &r8a7796_cpg_mssr_info,
  669. },
  670. #endif
  671. #ifdef CONFIG_CLK_R8A77961
  672. {
  673. .compatible = "renesas,r8a77961-cpg-mssr",
  674. .data = &r8a7796_cpg_mssr_info,
  675. },
  676. #endif
  677. #ifdef CONFIG_CLK_R8A77965
  678. {
  679. .compatible = "renesas,r8a77965-cpg-mssr",
  680. .data = &r8a77965_cpg_mssr_info,
  681. },
  682. #endif
  683. #ifdef CONFIG_CLK_R8A77970
  684. {
  685. .compatible = "renesas,r8a77970-cpg-mssr",
  686. .data = &r8a77970_cpg_mssr_info,
  687. },
  688. #endif
  689. #ifdef CONFIG_CLK_R8A77980
  690. {
  691. .compatible = "renesas,r8a77980-cpg-mssr",
  692. .data = &r8a77980_cpg_mssr_info,
  693. },
  694. #endif
  695. #ifdef CONFIG_CLK_R8A77990
  696. {
  697. .compatible = "renesas,r8a77990-cpg-mssr",
  698. .data = &r8a77990_cpg_mssr_info,
  699. },
  700. #endif
  701. #ifdef CONFIG_CLK_R8A77995
  702. {
  703. .compatible = "renesas,r8a77995-cpg-mssr",
  704. .data = &r8a77995_cpg_mssr_info,
  705. },
  706. #endif
  707. #ifdef CONFIG_CLK_R8A779A0
  708. {
  709. .compatible = "renesas,r8a779a0-cpg-mssr",
  710. .data = &r8a779a0_cpg_mssr_info,
  711. },
  712. #endif
  713. { /* sentinel */ }
  714. };
  715. static void cpg_mssr_del_clk_provider(void *data)
  716. {
  717. of_clk_del_provider(data);
  718. }
  719. #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
  720. static int cpg_mssr_suspend_noirq(struct device *dev)
  721. {
  722. struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
  723. unsigned int reg;
  724. /* This is the best we can do to check for the presence of PSCI */
  725. if (!psci_ops.cpu_suspend)
  726. return 0;
  727. /* Save module registers with bits under our control */
  728. for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
  729. if (priv->smstpcr_saved[reg].mask)
  730. priv->smstpcr_saved[reg].val =
  731. priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
  732. readb(priv->base + priv->control_regs[reg]) :
  733. readl(priv->base + priv->control_regs[reg]);
  734. }
  735. /* Save core clocks */
  736. raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
  737. return 0;
  738. }
  739. static int cpg_mssr_resume_noirq(struct device *dev)
  740. {
  741. struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
  742. unsigned int reg, i;
  743. u32 mask, oldval, newval;
  744. /* This is the best we can do to check for the presence of PSCI */
  745. if (!psci_ops.cpu_suspend)
  746. return 0;
  747. /* Restore core clocks */
  748. raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
  749. /* Restore module clocks */
  750. for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
  751. mask = priv->smstpcr_saved[reg].mask;
  752. if (!mask)
  753. continue;
  754. if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
  755. oldval = readb(priv->base + priv->control_regs[reg]);
  756. else
  757. oldval = readl(priv->base + priv->control_regs[reg]);
  758. newval = oldval & ~mask;
  759. newval |= priv->smstpcr_saved[reg].val & mask;
  760. if (newval == oldval)
  761. continue;
  762. if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
  763. writeb(newval, priv->base + priv->control_regs[reg]);
  764. /* dummy read to ensure write has completed */
  765. readb(priv->base + priv->control_regs[reg]);
  766. barrier_data(priv->base + priv->control_regs[reg]);
  767. continue;
  768. } else
  769. writel(newval, priv->base + priv->control_regs[reg]);
  770. /* Wait until enabled clocks are really enabled */
  771. mask &= ~priv->smstpcr_saved[reg].val;
  772. if (!mask)
  773. continue;
  774. for (i = 1000; i > 0; --i) {
  775. oldval = readl(priv->base + priv->status_regs[reg]);
  776. if (!(oldval & mask))
  777. break;
  778. cpu_relax();
  779. }
  780. if (!i)
  781. dev_warn(dev, "Failed to enable %s%u[0x%x]\n",
  782. priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
  783. "STB" : "SMSTP", reg, oldval & mask);
  784. }
  785. return 0;
  786. }
  787. static const struct dev_pm_ops cpg_mssr_pm = {
  788. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
  789. cpg_mssr_resume_noirq)
  790. };
  791. #define DEV_PM_OPS &cpg_mssr_pm
  792. #else
  793. #define DEV_PM_OPS NULL
  794. #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
  795. static int __init cpg_mssr_common_init(struct device *dev,
  796. struct device_node *np,
  797. const struct cpg_mssr_info *info)
  798. {
  799. struct cpg_mssr_priv *priv;
  800. unsigned int nclks, i;
  801. int error;
  802. if (info->init) {
  803. error = info->init(dev);
  804. if (error)
  805. return error;
  806. }
  807. nclks = info->num_total_core_clks + info->num_hw_mod_clks;
  808. priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL);
  809. if (!priv)
  810. return -ENOMEM;
  811. priv->np = np;
  812. priv->dev = dev;
  813. spin_lock_init(&priv->rmw_lock);
  814. priv->base = of_iomap(np, 0);
  815. if (!priv->base) {
  816. error = -ENOMEM;
  817. goto out_err;
  818. }
  819. cpg_mssr_priv = priv;
  820. priv->num_core_clks = info->num_total_core_clks;
  821. priv->num_mod_clks = info->num_hw_mod_clks;
  822. priv->last_dt_core_clk = info->last_dt_core_clk;
  823. RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
  824. priv->reg_layout = info->reg_layout;
  825. if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
  826. priv->status_regs = mstpsr;
  827. priv->control_regs = smstpcr;
  828. priv->reset_regs = srcr;
  829. priv->reset_clear_regs = srstclr;
  830. } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
  831. priv->control_regs = stbcr;
  832. } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
  833. priv->status_regs = mstpsr_for_v3u;
  834. priv->control_regs = mstpcr_for_v3u;
  835. priv->reset_regs = srcr_for_v3u;
  836. priv->reset_clear_regs = srstclr_for_v3u;
  837. } else {
  838. error = -EINVAL;
  839. goto out_err;
  840. }
  841. for (i = 0; i < nclks; i++)
  842. priv->clks[i] = ERR_PTR(-ENOENT);
  843. error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
  844. if (error)
  845. goto out_err;
  846. return 0;
  847. out_err:
  848. if (priv->base)
  849. iounmap(priv->base);
  850. kfree(priv);
  851. return error;
  852. }
  853. void __init cpg_mssr_early_init(struct device_node *np,
  854. const struct cpg_mssr_info *info)
  855. {
  856. int error;
  857. int i;
  858. error = cpg_mssr_common_init(NULL, np, info);
  859. if (error)
  860. return;
  861. for (i = 0; i < info->num_early_core_clks; i++)
  862. cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
  863. cpg_mssr_priv);
  864. for (i = 0; i < info->num_early_mod_clks; i++)
  865. cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
  866. cpg_mssr_priv);
  867. }
  868. static int __init cpg_mssr_probe(struct platform_device *pdev)
  869. {
  870. struct device *dev = &pdev->dev;
  871. struct device_node *np = dev->of_node;
  872. const struct cpg_mssr_info *info;
  873. struct cpg_mssr_priv *priv;
  874. unsigned int i;
  875. int error;
  876. info = of_device_get_match_data(dev);
  877. if (!cpg_mssr_priv) {
  878. error = cpg_mssr_common_init(dev, dev->of_node, info);
  879. if (error)
  880. return error;
  881. }
  882. priv = cpg_mssr_priv;
  883. priv->dev = dev;
  884. dev_set_drvdata(dev, priv);
  885. for (i = 0; i < info->num_core_clks; i++)
  886. cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
  887. for (i = 0; i < info->num_mod_clks; i++)
  888. cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
  889. error = devm_add_action_or_reset(dev,
  890. cpg_mssr_del_clk_provider,
  891. np);
  892. if (error)
  893. return error;
  894. error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
  895. info->num_core_pm_clks);
  896. if (error)
  897. return error;
  898. /* Reset Controller not supported for Standby Control SoCs */
  899. if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
  900. return 0;
  901. error = cpg_mssr_reset_controller_register(priv);
  902. if (error)
  903. return error;
  904. return 0;
  905. }
  906. static struct platform_driver cpg_mssr_driver = {
  907. .driver = {
  908. .name = "renesas-cpg-mssr",
  909. .of_match_table = cpg_mssr_match,
  910. .pm = DEV_PM_OPS,
  911. },
  912. };
  913. static int __init cpg_mssr_init(void)
  914. {
  915. return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
  916. }
  917. subsys_initcall(cpg_mssr_init);
  918. void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,
  919. unsigned int num_core_clks,
  920. unsigned int first_clk,
  921. unsigned int last_clk)
  922. {
  923. unsigned int i;
  924. for (i = 0; i < num_core_clks; i++)
  925. if (core_clks[i].id >= first_clk &&
  926. core_clks[i].id <= last_clk)
  927. core_clks[i].name = NULL;
  928. }
  929. void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
  930. unsigned int num_mod_clks,
  931. const unsigned int *clks, unsigned int n)
  932. {
  933. unsigned int i, j;
  934. for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
  935. if (mod_clks[i].id == clks[j]) {
  936. mod_clks[i].name = NULL;
  937. j++;
  938. }
  939. }
  940. void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
  941. unsigned int num_mod_clks,
  942. const struct mssr_mod_reparent *clks,
  943. unsigned int n)
  944. {
  945. unsigned int i, j;
  946. for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
  947. if (mod_clks[i].id == clks[j].clk) {
  948. mod_clks[i].parent = clks[j].parent;
  949. j++;
  950. }
  951. }
  952. MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
  953. MODULE_LICENSE("GPL v2");