rcar-gen3-cpg.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * R-Car Gen3 Clock Pulse Generator
  4. *
  5. * Copyright (C) 2015-2018 Glider bvba
  6. * Copyright (C) 2018 Renesas Electronics Corp.
  7. *
  8. */
  9. #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
  10. #define __CLK_RENESAS_RCAR_GEN3_CPG_H__
  11. enum rcar_gen3_clk_types {
  12. CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
  13. CLK_TYPE_GEN3_PLL0,
  14. CLK_TYPE_GEN3_PLL1,
  15. CLK_TYPE_GEN3_PLL2,
  16. CLK_TYPE_GEN3_PLL3,
  17. CLK_TYPE_GEN3_PLL4,
  18. CLK_TYPE_GEN3_SD,
  19. CLK_TYPE_GEN3_R,
  20. CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
  21. CLK_TYPE_GEN3_Z,
  22. CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
  23. CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
  24. CLK_TYPE_GEN3_RPCSRC,
  25. CLK_TYPE_GEN3_RPC,
  26. CLK_TYPE_GEN3_RPCD2,
  27. /* SoC specific definitions start here */
  28. CLK_TYPE_GEN3_SOC_BASE,
  29. };
  30. #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
  31. DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
  32. #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
  33. DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
  34. (_parent0) << 16 | (_parent1), \
  35. .div = (_div0) << 16 | (_div1), .offset = _md)
  36. #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
  37. _div_clean) \
  38. DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
  39. _parent_clean, _div_clean)
  40. #define DEF_GEN3_OSC(_name, _id, _parent, _div) \
  41. DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
  42. #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
  43. DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
  44. (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
  45. #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
  46. DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
  47. struct rcar_gen3_cpg_pll_config {
  48. u8 extal_div;
  49. u8 pll1_mult;
  50. u8 pll1_div;
  51. u8 pll3_mult;
  52. u8 pll3_div;
  53. u8 osc_prediv;
  54. };
  55. #define CPG_RPCCKCR 0x238
  56. #define CPG_RCKCR 0x240
  57. struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
  58. const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
  59. struct clk **clks, void __iomem *base,
  60. struct raw_notifier_head *notifiers);
  61. int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
  62. unsigned int clk_extalr, u32 mode);
  63. #endif