rcar-gen3-cpg.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R-Car Gen3 Clock Pulse Generator
  4. *
  5. * Copyright (C) 2015-2018 Glider bvba
  6. * Copyright (C) 2019 Renesas Electronics Corp.
  7. *
  8. * Based on clk-rcar-gen3.c
  9. *
  10. * Copyright (C) 2015 Renesas Electronics Corp.
  11. */
  12. #include <linux/bug.h>
  13. #include <linux/bitfield.h>
  14. #include <linux/clk.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/device.h>
  17. #include <linux/err.h>
  18. #include <linux/init.h>
  19. #include <linux/io.h>
  20. #include <linux/pm.h>
  21. #include <linux/slab.h>
  22. #include <linux/sys_soc.h>
  23. #include "renesas-cpg-mssr.h"
  24. #include "rcar-gen3-cpg.h"
  25. #define CPG_PLL0CR 0x00d8
  26. #define CPG_PLL2CR 0x002c
  27. #define CPG_PLL4CR 0x01f4
  28. #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
  29. static spinlock_t cpg_lock;
  30. static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
  31. {
  32. unsigned long flags;
  33. u32 val;
  34. spin_lock_irqsave(&cpg_lock, flags);
  35. val = readl(reg);
  36. val &= ~clear;
  37. val |= set;
  38. writel(val, reg);
  39. spin_unlock_irqrestore(&cpg_lock, flags);
  40. };
  41. struct cpg_simple_notifier {
  42. struct notifier_block nb;
  43. void __iomem *reg;
  44. u32 saved;
  45. };
  46. static int cpg_simple_notifier_call(struct notifier_block *nb,
  47. unsigned long action, void *data)
  48. {
  49. struct cpg_simple_notifier *csn =
  50. container_of(nb, struct cpg_simple_notifier, nb);
  51. switch (action) {
  52. case PM_EVENT_SUSPEND:
  53. csn->saved = readl(csn->reg);
  54. return NOTIFY_OK;
  55. case PM_EVENT_RESUME:
  56. writel(csn->saved, csn->reg);
  57. return NOTIFY_OK;
  58. }
  59. return NOTIFY_DONE;
  60. }
  61. static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
  62. struct cpg_simple_notifier *csn)
  63. {
  64. csn->nb.notifier_call = cpg_simple_notifier_call;
  65. raw_notifier_chain_register(notifiers, &csn->nb);
  66. }
  67. /*
  68. * Z Clock & Z2 Clock
  69. *
  70. * Traits of this clock:
  71. * prepare - clk_prepare only ensures that parents are prepared
  72. * enable - clk_enable only ensures that parents are enabled
  73. * rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
  74. * parent - fixed parent. No clk_set_parent support
  75. */
  76. #define CPG_FRQCRB 0x00000004
  77. #define CPG_FRQCRB_KICK BIT(31)
  78. #define CPG_FRQCRC 0x000000e0
  79. struct cpg_z_clk {
  80. struct clk_hw hw;
  81. void __iomem *reg;
  82. void __iomem *kick_reg;
  83. unsigned long mask;
  84. unsigned int fixed_div;
  85. };
  86. #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
  87. static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
  88. unsigned long parent_rate)
  89. {
  90. struct cpg_z_clk *zclk = to_z_clk(hw);
  91. unsigned int mult;
  92. u32 val;
  93. val = readl(zclk->reg) & zclk->mask;
  94. mult = 32 - (val >> __ffs(zclk->mask));
  95. return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
  96. 32 * zclk->fixed_div);
  97. }
  98. static int cpg_z_clk_determine_rate(struct clk_hw *hw,
  99. struct clk_rate_request *req)
  100. {
  101. struct cpg_z_clk *zclk = to_z_clk(hw);
  102. unsigned int min_mult, max_mult, mult;
  103. unsigned long prate;
  104. prate = req->best_parent_rate / zclk->fixed_div;
  105. min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
  106. max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
  107. if (max_mult < min_mult)
  108. return -EINVAL;
  109. mult = div64_ul(req->rate * 32ULL, prate);
  110. mult = clamp(mult, min_mult, max_mult);
  111. req->rate = div_u64((u64)prate * mult, 32);
  112. return 0;
  113. }
  114. static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  115. unsigned long parent_rate)
  116. {
  117. struct cpg_z_clk *zclk = to_z_clk(hw);
  118. unsigned int mult;
  119. unsigned int i;
  120. mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
  121. parent_rate);
  122. mult = clamp(mult, 1U, 32U);
  123. if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
  124. return -EBUSY;
  125. cpg_reg_modify(zclk->reg, zclk->mask,
  126. ((32 - mult) << __ffs(zclk->mask)) & zclk->mask);
  127. /*
  128. * Set KICK bit in FRQCRB to update hardware setting and wait for
  129. * clock change completion.
  130. */
  131. cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
  132. /*
  133. * Note: There is no HW information about the worst case latency.
  134. *
  135. * Using experimental measurements, it seems that no more than
  136. * ~10 iterations are needed, independently of the CPU rate.
  137. * Since this value might be dependent of external xtal rate, pll1
  138. * rate or even the other emulation clocks rate, use 1000 as a
  139. * "super" safe value.
  140. */
  141. for (i = 1000; i; i--) {
  142. if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
  143. return 0;
  144. cpu_relax();
  145. }
  146. return -ETIMEDOUT;
  147. }
  148. static const struct clk_ops cpg_z_clk_ops = {
  149. .recalc_rate = cpg_z_clk_recalc_rate,
  150. .determine_rate = cpg_z_clk_determine_rate,
  151. .set_rate = cpg_z_clk_set_rate,
  152. };
  153. static struct clk * __init cpg_z_clk_register(const char *name,
  154. const char *parent_name,
  155. void __iomem *reg,
  156. unsigned int div,
  157. unsigned int offset)
  158. {
  159. struct clk_init_data init;
  160. struct cpg_z_clk *zclk;
  161. struct clk *clk;
  162. zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
  163. if (!zclk)
  164. return ERR_PTR(-ENOMEM);
  165. init.name = name;
  166. init.ops = &cpg_z_clk_ops;
  167. init.flags = 0;
  168. init.parent_names = &parent_name;
  169. init.num_parents = 1;
  170. zclk->reg = reg + CPG_FRQCRC;
  171. zclk->kick_reg = reg + CPG_FRQCRB;
  172. zclk->hw.init = &init;
  173. zclk->mask = GENMASK(offset + 4, offset);
  174. zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
  175. clk = clk_register(NULL, &zclk->hw);
  176. if (IS_ERR(clk))
  177. kfree(zclk);
  178. return clk;
  179. }
  180. /*
  181. * SDn Clock
  182. */
  183. #define CPG_SD_STP_HCK BIT(9)
  184. #define CPG_SD_STP_CK BIT(8)
  185. #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
  186. #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
  187. #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
  188. { \
  189. .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
  190. ((stp_ck) ? CPG_SD_STP_CK : 0) | \
  191. ((sd_srcfc) << 2) | \
  192. ((sd_fc) << 0), \
  193. .div = (sd_div), \
  194. }
  195. struct sd_div_table {
  196. u32 val;
  197. unsigned int div;
  198. };
  199. struct sd_clock {
  200. struct clk_hw hw;
  201. const struct sd_div_table *div_table;
  202. struct cpg_simple_notifier csn;
  203. unsigned int div_num;
  204. unsigned int cur_div_idx;
  205. };
  206. /* SDn divider
  207. * sd_srcfc sd_fc div
  208. * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
  209. *-------------------------------------------------------------------
  210. * 0 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
  211. * 0 0 1 (2) 1 (4) 8 : SDR50
  212. * 1 0 2 (4) 1 (4) 16 : HS / SDR25
  213. * 1 0 3 (8) 1 (4) 32 : NS / SDR12
  214. * 1 0 4 (16) 1 (4) 64
  215. * 0 0 0 (1) 0 (2) 2
  216. * 0 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
  217. * 1 0 2 (4) 0 (2) 8
  218. * 1 0 3 (8) 0 (2) 16
  219. * 1 0 4 (16) 0 (2) 32
  220. *
  221. * NOTE: There is a quirk option to ignore the first row of the dividers
  222. * table when searching for suitable settings. This is because HS400 on
  223. * early ES versions of H3 and M3-W requires a specific setting to work.
  224. */
  225. static const struct sd_div_table cpg_sd_div_table[] = {
  226. /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
  227. CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
  228. CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
  229. CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
  230. CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
  231. CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
  232. CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
  233. CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
  234. CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
  235. CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
  236. CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
  237. };
  238. #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
  239. static int cpg_sd_clock_enable(struct clk_hw *hw)
  240. {
  241. struct sd_clock *clock = to_sd_clock(hw);
  242. cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK,
  243. clock->div_table[clock->cur_div_idx].val &
  244. CPG_SD_STP_MASK);
  245. return 0;
  246. }
  247. static void cpg_sd_clock_disable(struct clk_hw *hw)
  248. {
  249. struct sd_clock *clock = to_sd_clock(hw);
  250. cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK);
  251. }
  252. static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
  253. {
  254. struct sd_clock *clock = to_sd_clock(hw);
  255. return !(readl(clock->csn.reg) & CPG_SD_STP_MASK);
  256. }
  257. static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
  258. unsigned long parent_rate)
  259. {
  260. struct sd_clock *clock = to_sd_clock(hw);
  261. return DIV_ROUND_CLOSEST(parent_rate,
  262. clock->div_table[clock->cur_div_idx].div);
  263. }
  264. static int cpg_sd_clock_determine_rate(struct clk_hw *hw,
  265. struct clk_rate_request *req)
  266. {
  267. unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX;
  268. struct sd_clock *clock = to_sd_clock(hw);
  269. unsigned long calc_rate, diff;
  270. unsigned int i;
  271. for (i = 0; i < clock->div_num; i++) {
  272. calc_rate = DIV_ROUND_CLOSEST(req->best_parent_rate,
  273. clock->div_table[i].div);
  274. if (calc_rate < req->min_rate || calc_rate > req->max_rate)
  275. continue;
  276. diff = calc_rate > req->rate ? calc_rate - req->rate
  277. : req->rate - calc_rate;
  278. if (diff < diff_min) {
  279. best_rate = calc_rate;
  280. diff_min = diff;
  281. }
  282. }
  283. if (best_rate == ULONG_MAX)
  284. return -EINVAL;
  285. req->rate = best_rate;
  286. return 0;
  287. }
  288. static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
  289. unsigned long parent_rate)
  290. {
  291. struct sd_clock *clock = to_sd_clock(hw);
  292. unsigned int i;
  293. for (i = 0; i < clock->div_num; i++)
  294. if (rate == DIV_ROUND_CLOSEST(parent_rate,
  295. clock->div_table[i].div))
  296. break;
  297. if (i >= clock->div_num)
  298. return -EINVAL;
  299. clock->cur_div_idx = i;
  300. cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK,
  301. clock->div_table[i].val &
  302. (CPG_SD_STP_MASK | CPG_SD_FC_MASK));
  303. return 0;
  304. }
  305. static const struct clk_ops cpg_sd_clock_ops = {
  306. .enable = cpg_sd_clock_enable,
  307. .disable = cpg_sd_clock_disable,
  308. .is_enabled = cpg_sd_clock_is_enabled,
  309. .recalc_rate = cpg_sd_clock_recalc_rate,
  310. .determine_rate = cpg_sd_clock_determine_rate,
  311. .set_rate = cpg_sd_clock_set_rate,
  312. };
  313. static u32 cpg_quirks __initdata;
  314. #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
  315. #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
  316. #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
  317. static struct clk * __init cpg_sd_clk_register(const char *name,
  318. void __iomem *base, unsigned int offset, const char *parent_name,
  319. struct raw_notifier_head *notifiers)
  320. {
  321. struct clk_init_data init;
  322. struct sd_clock *clock;
  323. struct clk *clk;
  324. u32 val;
  325. clock = kzalloc(sizeof(*clock), GFP_KERNEL);
  326. if (!clock)
  327. return ERR_PTR(-ENOMEM);
  328. init.name = name;
  329. init.ops = &cpg_sd_clock_ops;
  330. init.flags = CLK_SET_RATE_PARENT;
  331. init.parent_names = &parent_name;
  332. init.num_parents = 1;
  333. clock->csn.reg = base + offset;
  334. clock->hw.init = &init;
  335. clock->div_table = cpg_sd_div_table;
  336. clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
  337. if (cpg_quirks & SD_SKIP_FIRST) {
  338. clock->div_table++;
  339. clock->div_num--;
  340. }
  341. val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK;
  342. val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
  343. writel(val, clock->csn.reg);
  344. clk = clk_register(NULL, &clock->hw);
  345. if (IS_ERR(clk))
  346. goto free_clock;
  347. cpg_simple_notifier_register(notifiers, &clock->csn);
  348. return clk;
  349. free_clock:
  350. kfree(clock);
  351. return clk;
  352. }
  353. struct rpc_clock {
  354. struct clk_divider div;
  355. struct clk_gate gate;
  356. /*
  357. * One notifier covers both RPC and RPCD2 clocks as they are both
  358. * controlled by the same RPCCKCR register...
  359. */
  360. struct cpg_simple_notifier csn;
  361. };
  362. static const struct clk_div_table cpg_rpcsrc_div_table[] = {
  363. { 2, 5 }, { 3, 6 }, { 0, 0 },
  364. };
  365. static const struct clk_div_table cpg_rpc_div_table[] = {
  366. { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
  367. };
  368. static struct clk * __init cpg_rpc_clk_register(const char *name,
  369. void __iomem *base, const char *parent_name,
  370. struct raw_notifier_head *notifiers)
  371. {
  372. struct rpc_clock *rpc;
  373. struct clk *clk;
  374. rpc = kzalloc(sizeof(*rpc), GFP_KERNEL);
  375. if (!rpc)
  376. return ERR_PTR(-ENOMEM);
  377. rpc->div.reg = base + CPG_RPCCKCR;
  378. rpc->div.width = 3;
  379. rpc->div.table = cpg_rpc_div_table;
  380. rpc->div.lock = &cpg_lock;
  381. rpc->gate.reg = base + CPG_RPCCKCR;
  382. rpc->gate.bit_idx = 8;
  383. rpc->gate.flags = CLK_GATE_SET_TO_DISABLE;
  384. rpc->gate.lock = &cpg_lock;
  385. rpc->csn.reg = base + CPG_RPCCKCR;
  386. clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
  387. &rpc->div.hw, &clk_divider_ops,
  388. &rpc->gate.hw, &clk_gate_ops,
  389. CLK_SET_RATE_PARENT);
  390. if (IS_ERR(clk)) {
  391. kfree(rpc);
  392. return clk;
  393. }
  394. cpg_simple_notifier_register(notifiers, &rpc->csn);
  395. return clk;
  396. }
  397. struct rpcd2_clock {
  398. struct clk_fixed_factor fixed;
  399. struct clk_gate gate;
  400. };
  401. static struct clk * __init cpg_rpcd2_clk_register(const char *name,
  402. void __iomem *base,
  403. const char *parent_name)
  404. {
  405. struct rpcd2_clock *rpcd2;
  406. struct clk *clk;
  407. rpcd2 = kzalloc(sizeof(*rpcd2), GFP_KERNEL);
  408. if (!rpcd2)
  409. return ERR_PTR(-ENOMEM);
  410. rpcd2->fixed.mult = 1;
  411. rpcd2->fixed.div = 2;
  412. rpcd2->gate.reg = base + CPG_RPCCKCR;
  413. rpcd2->gate.bit_idx = 9;
  414. rpcd2->gate.flags = CLK_GATE_SET_TO_DISABLE;
  415. rpcd2->gate.lock = &cpg_lock;
  416. clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
  417. &rpcd2->fixed.hw, &clk_fixed_factor_ops,
  418. &rpcd2->gate.hw, &clk_gate_ops,
  419. CLK_SET_RATE_PARENT);
  420. if (IS_ERR(clk))
  421. kfree(rpcd2);
  422. return clk;
  423. }
  424. static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
  425. static unsigned int cpg_clk_extalr __initdata;
  426. static u32 cpg_mode __initdata;
  427. static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
  428. {
  429. .soc_id = "r8a7795", .revision = "ES1.0",
  430. .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST),
  431. },
  432. {
  433. .soc_id = "r8a7795", .revision = "ES1.*",
  434. .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
  435. },
  436. {
  437. .soc_id = "r8a7795", .revision = "ES2.0",
  438. .data = (void *)SD_SKIP_FIRST,
  439. },
  440. {
  441. .soc_id = "r8a7796", .revision = "ES1.0",
  442. .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
  443. },
  444. {
  445. .soc_id = "r8a7796", .revision = "ES1.1",
  446. .data = (void *)SD_SKIP_FIRST,
  447. },
  448. { /* sentinel */ }
  449. };
  450. struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
  451. const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
  452. struct clk **clks, void __iomem *base,
  453. struct raw_notifier_head *notifiers)
  454. {
  455. const struct clk *parent;
  456. unsigned int mult = 1;
  457. unsigned int div = 1;
  458. u32 value;
  459. parent = clks[core->parent & 0xffff]; /* some types use high bits */
  460. if (IS_ERR(parent))
  461. return ERR_CAST(parent);
  462. switch (core->type) {
  463. case CLK_TYPE_GEN3_MAIN:
  464. div = cpg_pll_config->extal_div;
  465. break;
  466. case CLK_TYPE_GEN3_PLL0:
  467. /*
  468. * PLL0 is a configurable multiplier clock. Register it as a
  469. * fixed factor clock for now as there's no generic multiplier
  470. * clock implementation and we currently have no need to change
  471. * the multiplier value.
  472. */
  473. value = readl(base + CPG_PLL0CR);
  474. mult = (((value >> 24) & 0x7f) + 1) * 2;
  475. if (cpg_quirks & PLL_ERRATA)
  476. mult *= 2;
  477. break;
  478. case CLK_TYPE_GEN3_PLL1:
  479. mult = cpg_pll_config->pll1_mult;
  480. div = cpg_pll_config->pll1_div;
  481. break;
  482. case CLK_TYPE_GEN3_PLL2:
  483. /*
  484. * PLL2 is a configurable multiplier clock. Register it as a
  485. * fixed factor clock for now as there's no generic multiplier
  486. * clock implementation and we currently have no need to change
  487. * the multiplier value.
  488. */
  489. value = readl(base + CPG_PLL2CR);
  490. mult = (((value >> 24) & 0x7f) + 1) * 2;
  491. if (cpg_quirks & PLL_ERRATA)
  492. mult *= 2;
  493. break;
  494. case CLK_TYPE_GEN3_PLL3:
  495. mult = cpg_pll_config->pll3_mult;
  496. div = cpg_pll_config->pll3_div;
  497. break;
  498. case CLK_TYPE_GEN3_PLL4:
  499. /*
  500. * PLL4 is a configurable multiplier clock. Register it as a
  501. * fixed factor clock for now as there's no generic multiplier
  502. * clock implementation and we currently have no need to change
  503. * the multiplier value.
  504. */
  505. value = readl(base + CPG_PLL4CR);
  506. mult = (((value >> 24) & 0x7f) + 1) * 2;
  507. if (cpg_quirks & PLL_ERRATA)
  508. mult *= 2;
  509. break;
  510. case CLK_TYPE_GEN3_SD:
  511. return cpg_sd_clk_register(core->name, base, core->offset,
  512. __clk_get_name(parent), notifiers);
  513. case CLK_TYPE_GEN3_R:
  514. if (cpg_quirks & RCKCR_CKSEL) {
  515. struct cpg_simple_notifier *csn;
  516. csn = kzalloc(sizeof(*csn), GFP_KERNEL);
  517. if (!csn)
  518. return ERR_PTR(-ENOMEM);
  519. csn->reg = base + CPG_RCKCR;
  520. /*
  521. * RINT is default.
  522. * Only if EXTALR is populated, we switch to it.
  523. */
  524. value = readl(csn->reg) & 0x3f;
  525. if (clk_get_rate(clks[cpg_clk_extalr])) {
  526. parent = clks[cpg_clk_extalr];
  527. value |= CPG_RCKCR_CKSEL;
  528. }
  529. writel(value, csn->reg);
  530. cpg_simple_notifier_register(notifiers, csn);
  531. break;
  532. }
  533. /* Select parent clock of RCLK by MD28 */
  534. if (cpg_mode & BIT(28))
  535. parent = clks[cpg_clk_extalr];
  536. break;
  537. case CLK_TYPE_GEN3_MDSEL:
  538. /*
  539. * Clock selectable between two parents and two fixed dividers
  540. * using a mode pin
  541. */
  542. if (cpg_mode & BIT(core->offset)) {
  543. div = core->div & 0xffff;
  544. } else {
  545. parent = clks[core->parent >> 16];
  546. if (IS_ERR(parent))
  547. return ERR_CAST(parent);
  548. div = core->div >> 16;
  549. }
  550. mult = 1;
  551. break;
  552. case CLK_TYPE_GEN3_Z:
  553. return cpg_z_clk_register(core->name, __clk_get_name(parent),
  554. base, core->div, core->offset);
  555. case CLK_TYPE_GEN3_OSC:
  556. /*
  557. * Clock combining OSC EXTAL predivider and a fixed divider
  558. */
  559. div = cpg_pll_config->osc_prediv * core->div;
  560. break;
  561. case CLK_TYPE_GEN3_RCKSEL:
  562. /*
  563. * Clock selectable between two parents and two fixed dividers
  564. * using RCKCR.CKSEL
  565. */
  566. if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
  567. div = core->div & 0xffff;
  568. } else {
  569. parent = clks[core->parent >> 16];
  570. if (IS_ERR(parent))
  571. return ERR_CAST(parent);
  572. div = core->div >> 16;
  573. }
  574. break;
  575. case CLK_TYPE_GEN3_RPCSRC:
  576. return clk_register_divider_table(NULL, core->name,
  577. __clk_get_name(parent), 0,
  578. base + CPG_RPCCKCR, 3, 2, 0,
  579. cpg_rpcsrc_div_table,
  580. &cpg_lock);
  581. case CLK_TYPE_GEN3_RPC:
  582. return cpg_rpc_clk_register(core->name, base,
  583. __clk_get_name(parent), notifiers);
  584. case CLK_TYPE_GEN3_RPCD2:
  585. return cpg_rpcd2_clk_register(core->name, base,
  586. __clk_get_name(parent));
  587. default:
  588. return ERR_PTR(-EINVAL);
  589. }
  590. return clk_register_fixed_factor(NULL, core->name,
  591. __clk_get_name(parent), 0, mult, div);
  592. }
  593. int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
  594. unsigned int clk_extalr, u32 mode)
  595. {
  596. const struct soc_device_attribute *attr;
  597. cpg_pll_config = config;
  598. cpg_clk_extalr = clk_extalr;
  599. cpg_mode = mode;
  600. attr = soc_device_match(cpg_quirks_match);
  601. if (attr)
  602. cpg_quirks = (uintptr_t)attr->data;
  603. pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
  604. spin_lock_init(&cpg_lock);
  605. return 0;
  606. }