rcar-gen2-cpg.h 966 B

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * R-Car Gen2 Clock Pulse Generator
  4. *
  5. * Copyright (C) 2016 Cogent Embedded Inc.
  6. */
  7. #ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
  8. #define __CLK_RENESAS_RCAR_GEN2_CPG_H__
  9. enum rcar_gen2_clk_types {
  10. CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM,
  11. CLK_TYPE_GEN2_PLL0,
  12. CLK_TYPE_GEN2_PLL1,
  13. CLK_TYPE_GEN2_PLL3,
  14. CLK_TYPE_GEN2_Z,
  15. CLK_TYPE_GEN2_LB,
  16. CLK_TYPE_GEN2_ADSP,
  17. CLK_TYPE_GEN2_SDH,
  18. CLK_TYPE_GEN2_SD0,
  19. CLK_TYPE_GEN2_SD1,
  20. CLK_TYPE_GEN2_QSPI,
  21. CLK_TYPE_GEN2_RCAN,
  22. };
  23. struct rcar_gen2_cpg_pll_config {
  24. u8 extal_div;
  25. u8 pll1_mult;
  26. u8 pll3_mult;
  27. u8 pll0_mult; /* leave as zero if PLL0CR exists */
  28. };
  29. struct clk *rcar_gen2_cpg_clk_register(struct device *dev,
  30. const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
  31. struct clk **clks, void __iomem *base,
  32. struct raw_notifier_head *notifiers);
  33. int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
  34. unsigned int pll0_div, u32 mode);
  35. #endif