rcar-gen2-cpg.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R-Car Gen2 Clock Pulse Generator
  4. *
  5. * Copyright (C) 2016 Cogent Embedded Inc.
  6. */
  7. #include <linux/bug.h>
  8. #include <linux/clk.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/device.h>
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/slab.h>
  15. #include <linux/sys_soc.h>
  16. #include "renesas-cpg-mssr.h"
  17. #include "rcar-gen2-cpg.h"
  18. #define CPG_FRQCRB 0x0004
  19. #define CPG_FRQCRB_KICK BIT(31)
  20. #define CPG_SDCKCR 0x0074
  21. #define CPG_PLL0CR 0x00d8
  22. #define CPG_PLL0CR_STC_SHIFT 24
  23. #define CPG_PLL0CR_STC_MASK (0x7f << CPG_PLL0CR_STC_SHIFT)
  24. #define CPG_FRQCRC 0x00e0
  25. #define CPG_FRQCRC_ZFC_SHIFT 8
  26. #define CPG_FRQCRC_ZFC_MASK (0x1f << CPG_FRQCRC_ZFC_SHIFT)
  27. #define CPG_ADSPCKCR 0x025c
  28. #define CPG_RCANCKCR 0x0270
  29. static spinlock_t cpg_lock;
  30. /*
  31. * Z Clock
  32. *
  33. * Traits of this clock:
  34. * prepare - clk_prepare only ensures that parents are prepared
  35. * enable - clk_enable only ensures that parents are enabled
  36. * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
  37. * parent - fixed parent. No clk_set_parent support
  38. */
  39. struct cpg_z_clk {
  40. struct clk_hw hw;
  41. void __iomem *reg;
  42. void __iomem *kick_reg;
  43. };
  44. #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
  45. static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
  46. unsigned long parent_rate)
  47. {
  48. struct cpg_z_clk *zclk = to_z_clk(hw);
  49. unsigned int mult;
  50. unsigned int val;
  51. val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;
  52. mult = 32 - val;
  53. return div_u64((u64)parent_rate * mult, 32);
  54. }
  55. static int cpg_z_clk_determine_rate(struct clk_hw *hw,
  56. struct clk_rate_request *req)
  57. {
  58. unsigned long prate = req->best_parent_rate;
  59. unsigned int min_mult, max_mult, mult;
  60. min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
  61. max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
  62. if (max_mult < min_mult)
  63. return -EINVAL;
  64. mult = div64_ul(req->rate * 32ULL, prate);
  65. mult = clamp(mult, min_mult, max_mult);
  66. req->rate = div_u64((u64)prate * mult, 32);
  67. return 0;
  68. }
  69. static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  70. unsigned long parent_rate)
  71. {
  72. struct cpg_z_clk *zclk = to_z_clk(hw);
  73. unsigned int mult;
  74. u32 val, kick;
  75. unsigned int i;
  76. mult = div64_ul(rate * 32ULL, parent_rate);
  77. mult = clamp(mult, 1U, 32U);
  78. if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
  79. return -EBUSY;
  80. val = readl(zclk->reg);
  81. val &= ~CPG_FRQCRC_ZFC_MASK;
  82. val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
  83. writel(val, zclk->reg);
  84. /*
  85. * Set KICK bit in FRQCRB to update hardware setting and wait for
  86. * clock change completion.
  87. */
  88. kick = readl(zclk->kick_reg);
  89. kick |= CPG_FRQCRB_KICK;
  90. writel(kick, zclk->kick_reg);
  91. /*
  92. * Note: There is no HW information about the worst case latency.
  93. *
  94. * Using experimental measurements, it seems that no more than
  95. * ~10 iterations are needed, independently of the CPU rate.
  96. * Since this value might be dependent on external xtal rate, pll1
  97. * rate or even the other emulation clocks rate, use 1000 as a
  98. * "super" safe value.
  99. */
  100. for (i = 1000; i; i--) {
  101. if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
  102. return 0;
  103. cpu_relax();
  104. }
  105. return -ETIMEDOUT;
  106. }
  107. static const struct clk_ops cpg_z_clk_ops = {
  108. .recalc_rate = cpg_z_clk_recalc_rate,
  109. .determine_rate = cpg_z_clk_determine_rate,
  110. .set_rate = cpg_z_clk_set_rate,
  111. };
  112. static struct clk * __init cpg_z_clk_register(const char *name,
  113. const char *parent_name,
  114. void __iomem *base)
  115. {
  116. struct clk_init_data init;
  117. struct cpg_z_clk *zclk;
  118. struct clk *clk;
  119. zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
  120. if (!zclk)
  121. return ERR_PTR(-ENOMEM);
  122. init.name = name;
  123. init.ops = &cpg_z_clk_ops;
  124. init.flags = 0;
  125. init.parent_names = &parent_name;
  126. init.num_parents = 1;
  127. zclk->reg = base + CPG_FRQCRC;
  128. zclk->kick_reg = base + CPG_FRQCRB;
  129. zclk->hw.init = &init;
  130. clk = clk_register(NULL, &zclk->hw);
  131. if (IS_ERR(clk))
  132. kfree(zclk);
  133. return clk;
  134. }
  135. static struct clk * __init cpg_rcan_clk_register(const char *name,
  136. const char *parent_name,
  137. void __iomem *base)
  138. {
  139. struct clk_fixed_factor *fixed;
  140. struct clk_gate *gate;
  141. struct clk *clk;
  142. fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
  143. if (!fixed)
  144. return ERR_PTR(-ENOMEM);
  145. fixed->mult = 1;
  146. fixed->div = 6;
  147. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  148. if (!gate) {
  149. kfree(fixed);
  150. return ERR_PTR(-ENOMEM);
  151. }
  152. gate->reg = base + CPG_RCANCKCR;
  153. gate->bit_idx = 8;
  154. gate->flags = CLK_GATE_SET_TO_DISABLE;
  155. gate->lock = &cpg_lock;
  156. clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
  157. &fixed->hw, &clk_fixed_factor_ops,
  158. &gate->hw, &clk_gate_ops, 0);
  159. if (IS_ERR(clk)) {
  160. kfree(gate);
  161. kfree(fixed);
  162. }
  163. return clk;
  164. }
  165. /* ADSP divisors */
  166. static const struct clk_div_table cpg_adsp_div_table[] = {
  167. { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 },
  168. { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
  169. { 10, 36 }, { 11, 48 }, { 0, 0 },
  170. };
  171. static struct clk * __init cpg_adsp_clk_register(const char *name,
  172. const char *parent_name,
  173. void __iomem *base)
  174. {
  175. struct clk_divider *div;
  176. struct clk_gate *gate;
  177. struct clk *clk;
  178. div = kzalloc(sizeof(*div), GFP_KERNEL);
  179. if (!div)
  180. return ERR_PTR(-ENOMEM);
  181. div->reg = base + CPG_ADSPCKCR;
  182. div->width = 4;
  183. div->table = cpg_adsp_div_table;
  184. div->lock = &cpg_lock;
  185. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  186. if (!gate) {
  187. kfree(div);
  188. return ERR_PTR(-ENOMEM);
  189. }
  190. gate->reg = base + CPG_ADSPCKCR;
  191. gate->bit_idx = 8;
  192. gate->flags = CLK_GATE_SET_TO_DISABLE;
  193. gate->lock = &cpg_lock;
  194. clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
  195. &div->hw, &clk_divider_ops,
  196. &gate->hw, &clk_gate_ops, 0);
  197. if (IS_ERR(clk)) {
  198. kfree(gate);
  199. kfree(div);
  200. }
  201. return clk;
  202. }
  203. /* SDHI divisors */
  204. static const struct clk_div_table cpg_sdh_div_table[] = {
  205. { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
  206. { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
  207. { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
  208. };
  209. static const struct clk_div_table cpg_sd01_div_table[] = {
  210. { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
  211. { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
  212. { 0, 0 },
  213. };
  214. static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
  215. static unsigned int cpg_pll0_div __initdata;
  216. static u32 cpg_mode __initdata;
  217. static u32 cpg_quirks __initdata;
  218. #define SD_SKIP_FIRST BIT(0) /* Skip first clock in SD table */
  219. static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
  220. {
  221. .soc_id = "r8a77470",
  222. .data = (void *)SD_SKIP_FIRST,
  223. },
  224. { /* sentinel */ }
  225. };
  226. struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
  227. const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
  228. struct clk **clks, void __iomem *base,
  229. struct raw_notifier_head *notifiers)
  230. {
  231. const struct clk_div_table *table = NULL;
  232. const struct clk *parent;
  233. const char *parent_name;
  234. unsigned int mult = 1;
  235. unsigned int div = 1;
  236. unsigned int shift;
  237. parent = clks[core->parent];
  238. if (IS_ERR(parent))
  239. return ERR_CAST(parent);
  240. parent_name = __clk_get_name(parent);
  241. switch (core->type) {
  242. /* R-Car Gen2 */
  243. case CLK_TYPE_GEN2_MAIN:
  244. div = cpg_pll_config->extal_div;
  245. break;
  246. case CLK_TYPE_GEN2_PLL0:
  247. /*
  248. * PLL0 is a configurable multiplier clock except on R-Car
  249. * V2H/E2. Register the PLL0 clock as a fixed factor clock for
  250. * now as there's no generic multiplier clock implementation and
  251. * we currently have no need to change the multiplier value.
  252. */
  253. mult = cpg_pll_config->pll0_mult;
  254. div = cpg_pll0_div;
  255. if (!mult) {
  256. u32 pll0cr = readl(base + CPG_PLL0CR);
  257. mult = (((pll0cr & CPG_PLL0CR_STC_MASK) >>
  258. CPG_PLL0CR_STC_SHIFT) + 1) * 2;
  259. }
  260. break;
  261. case CLK_TYPE_GEN2_PLL1:
  262. mult = cpg_pll_config->pll1_mult / 2;
  263. break;
  264. case CLK_TYPE_GEN2_PLL3:
  265. mult = cpg_pll_config->pll3_mult;
  266. break;
  267. case CLK_TYPE_GEN2_Z:
  268. return cpg_z_clk_register(core->name, parent_name, base);
  269. case CLK_TYPE_GEN2_LB:
  270. div = cpg_mode & BIT(18) ? 36 : 24;
  271. break;
  272. case CLK_TYPE_GEN2_ADSP:
  273. return cpg_adsp_clk_register(core->name, parent_name, base);
  274. case CLK_TYPE_GEN2_SDH:
  275. table = cpg_sdh_div_table;
  276. shift = 8;
  277. break;
  278. case CLK_TYPE_GEN2_SD0:
  279. table = cpg_sd01_div_table;
  280. if (cpg_quirks & SD_SKIP_FIRST)
  281. table++;
  282. shift = 4;
  283. break;
  284. case CLK_TYPE_GEN2_SD1:
  285. table = cpg_sd01_div_table;
  286. if (cpg_quirks & SD_SKIP_FIRST)
  287. table++;
  288. shift = 0;
  289. break;
  290. case CLK_TYPE_GEN2_QSPI:
  291. div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) ?
  292. 8 : 10;
  293. break;
  294. case CLK_TYPE_GEN2_RCAN:
  295. return cpg_rcan_clk_register(core->name, parent_name, base);
  296. default:
  297. return ERR_PTR(-EINVAL);
  298. }
  299. if (!table)
  300. return clk_register_fixed_factor(NULL, core->name, parent_name,
  301. 0, mult, div);
  302. else
  303. return clk_register_divider_table(NULL, core->name,
  304. parent_name, 0,
  305. base + CPG_SDCKCR, shift, 4,
  306. 0, table, &cpg_lock);
  307. }
  308. int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
  309. unsigned int pll0_div, u32 mode)
  310. {
  311. const struct soc_device_attribute *attr;
  312. cpg_pll_config = config;
  313. cpg_pll0_div = pll0_div;
  314. cpg_mode = mode;
  315. attr = soc_device_match(cpg_quirks_match);
  316. if (attr)
  317. cpg_quirks = (uintptr_t)attr->data;
  318. pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
  319. spin_lock_init(&cpg_lock);
  320. return 0;
  321. }