r9a06g032-clocks.c 33 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R9A06G032 clock driver
  4. *
  5. * Copyright (C) 2018 Renesas Electronics Europe Limited
  6. *
  7. * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/delay.h>
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/kernel.h>
  15. #include <linux/math64.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/pm_clock.h>
  20. #include <linux/pm_domain.h>
  21. #include <linux/slab.h>
  22. #include <linux/spinlock.h>
  23. #include <dt-bindings/clock/r9a06g032-sysctrl.h>
  24. struct r9a06g032_gate {
  25. u16 gate, reset, ready, midle,
  26. scon, mirack, mistat;
  27. };
  28. /* This is used to describe a clock for instantiation */
  29. struct r9a06g032_clkdesc {
  30. const char *name;
  31. uint32_t managed: 1;
  32. uint32_t type: 3;
  33. uint32_t index: 8;
  34. uint32_t source : 8; /* source index + 1 (0 == none) */
  35. /* these are used to populate the bitsel struct */
  36. union {
  37. struct r9a06g032_gate gate;
  38. /* for dividers */
  39. struct {
  40. unsigned int div_min : 10, div_max : 10, reg: 10;
  41. u16 div_table[4];
  42. };
  43. /* For fixed-factor ones */
  44. struct {
  45. u16 div, mul;
  46. };
  47. unsigned int factor;
  48. unsigned int frequency;
  49. /* for dual gate */
  50. struct {
  51. uint16_t group : 1, index: 3;
  52. u16 sel, g1, r1, g2, r2;
  53. } dual;
  54. };
  55. };
  56. #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
  57. { .gate = _clk, .reset = _rst, \
  58. .ready = _rdy, .midle = _midle, \
  59. .scon = _scon, .mirack = _mirack, .mistat = _mistat }
  60. #define D_GATE(_idx, _n, _src, ...) \
  61. { .type = K_GATE, .index = R9A06G032_##_idx, \
  62. .source = 1 + R9A06G032_##_src, .name = _n, \
  63. .gate = I_GATE(__VA_ARGS__) }
  64. #define D_MODULE(_idx, _n, _src, ...) \
  65. { .type = K_GATE, .index = R9A06G032_##_idx, \
  66. .source = 1 + R9A06G032_##_src, .name = _n, \
  67. .managed = 1, .gate = I_GATE(__VA_ARGS__) }
  68. #define D_ROOT(_idx, _n, _mul, _div) \
  69. { .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \
  70. .div = _div, .mul = _mul }
  71. #define D_FFC(_idx, _n, _src, _div) \
  72. { .type = K_FFC, .index = R9A06G032_##_idx, \
  73. .source = 1 + R9A06G032_##_src, .name = _n, \
  74. .div = _div, .mul = 1}
  75. #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \
  76. { .type = K_DIV, .index = R9A06G032_##_idx, \
  77. .source = 1 + R9A06G032_##_src, .name = _n, \
  78. .reg = _reg, .div_min = _min, .div_max = _max, \
  79. .div_table = { __VA_ARGS__ } }
  80. #define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
  81. { .type = K_DUALGATE, .index = R9A06G032_##_idx, \
  82. .source = 1 + R9A06G032_##_src, .name = _n, \
  83. .dual = { .group = _g, .index = _gi, \
  84. .g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
  85. enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
  86. /* Internal clock IDs */
  87. #define R9A06G032_CLKOUT 0
  88. #define R9A06G032_CLKOUT_D10 2
  89. #define R9A06G032_CLKOUT_D16 3
  90. #define R9A06G032_CLKOUT_D160 4
  91. #define R9A06G032_CLKOUT_D1OR2 5
  92. #define R9A06G032_CLKOUT_D20 6
  93. #define R9A06G032_CLKOUT_D40 7
  94. #define R9A06G032_CLKOUT_D5 8
  95. #define R9A06G032_CLKOUT_D8 9
  96. #define R9A06G032_DIV_ADC 10
  97. #define R9A06G032_DIV_I2C 11
  98. #define R9A06G032_DIV_NAND 12
  99. #define R9A06G032_DIV_P1_PG 13
  100. #define R9A06G032_DIV_P2_PG 14
  101. #define R9A06G032_DIV_P3_PG 15
  102. #define R9A06G032_DIV_P4_PG 16
  103. #define R9A06G032_DIV_P5_PG 17
  104. #define R9A06G032_DIV_P6_PG 18
  105. #define R9A06G032_DIV_QSPI0 19
  106. #define R9A06G032_DIV_QSPI1 20
  107. #define R9A06G032_DIV_REF_SYNC 21
  108. #define R9A06G032_DIV_SDIO0 22
  109. #define R9A06G032_DIV_SDIO1 23
  110. #define R9A06G032_DIV_SWITCH 24
  111. #define R9A06G032_DIV_UART 25
  112. #define R9A06G032_DIV_MOTOR 64
  113. #define R9A06G032_CLK_DDRPHY_PLLCLK_D4 78
  114. #define R9A06G032_CLK_ECAT100_D4 79
  115. #define R9A06G032_CLK_HSR100_D2 80
  116. #define R9A06G032_CLK_REF_SYNC_D4 81
  117. #define R9A06G032_CLK_REF_SYNC_D8 82
  118. #define R9A06G032_CLK_SERCOS100_D2 83
  119. #define R9A06G032_DIV_CA7 84
  120. #define R9A06G032_UART_GROUP_012 154
  121. #define R9A06G032_UART_GROUP_34567 155
  122. #define R9A06G032_CLOCK_COUNT (R9A06G032_UART_GROUP_34567 + 1)
  123. static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
  124. D_ROOT(CLKOUT, "clkout", 25, 1),
  125. D_ROOT(CLK_PLL_USB, "clk_pll_usb", 12, 10),
  126. D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10),
  127. D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16),
  128. D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160),
  129. D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
  130. D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20),
  131. D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40),
  132. D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5),
  133. D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8),
  134. D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250),
  135. D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16),
  136. D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32),
  137. D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200),
  138. D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128),
  139. D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128),
  140. D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128),
  141. D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40),
  142. D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64),
  143. D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7),
  144. D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7),
  145. D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16),
  146. D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128),
  147. D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128),
  148. D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40),
  149. D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128),
  150. D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0),
  151. D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0),
  152. D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0),
  153. D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0),
  154. D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0),
  155. D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0),
  156. D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, 0x405, 0, 0, 0, 0, 0, 0),
  157. D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, 0x483, 0, 0, 0, 0, 0, 0),
  158. D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, 0x1e6, 0x1e7, 0, 0, 0, 0, 0),
  159. D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, 0x1e8, 0x1e9, 0, 0, 0, 0, 0),
  160. D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, 0x342, 0, 0, 0, 0, 0, 0),
  161. D_GATE(CLK_NAND, "clk_nand", DIV_NAND, 0x284, 0x285, 0, 0, 0, 0, 0),
  162. D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, 0x774, 0x775, 0, 0, 0, 0, 0),
  163. D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, 0x862, 0x863, 0, 0, 0, 0, 0),
  164. D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, 0x864, 0x865, 0, 0, 0, 0, 0),
  165. D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, 0x866, 0x867, 0, 0, 0, 0, 0),
  166. D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, 0x824, 0x825, 0, 0, 0, 0, 0),
  167. D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, 0x826, 0x827, 0, 0, 0, 0, 0),
  168. D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, 0x8a0, 0x8a1, 0x8a2, 0, 0xb60, 0, 0),
  169. D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0),
  170. D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0),
  171. D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0),
  172. D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0),
  173. D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0),
  174. D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0),
  175. D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0),
  176. D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, 0x341, 0, 0, 0, 0, 0, 0),
  177. D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, 0x64, 0, 0, 0, 0, 0, 0),
  178. D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, 0x644, 0, 0, 0, 0, 0, 0),
  179. D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, 0x425, 0, 0, 0, 0, 0, 0),
  180. D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, 0x860, 0x861, 0, 0, 0, 0, 0),
  181. D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, 0x7e0, 0x7e1, 0, 0, 0, 0, 0),
  182. D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, 0x7e2, 0x7e3, 0, 0, 0, 0, 0),
  183. D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, 0x7e4, 0x7e5, 0, 0, 0, 0, 0),
  184. D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, 0x7e6, 0x7e7, 0, 0, 0, 0, 0),
  185. D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, 0x820, 0x821, 0, 0, 0, 0, 0),
  186. D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, 0x822, 0x823, 0, 0, 0, 0, 0),
  187. D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, 0x982, 0x983, 0, 0, 0, 0, 0),
  188. D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
  189. D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441),
  190. D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0),
  191. D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461),
  192. D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0),
  193. D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0),
  194. D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0),
  195. D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0),
  196. D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0),
  197. D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103),
  198. D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101),
  199. D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0),
  200. D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, 0x78c, 0x78d, 0, 0x78e, 0, 0xb04, 0xb05),
  201. D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, 0x789, 0x78a, 0x78b, 0, 0xb03, 0, 0),
  202. D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4),
  203. D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4),
  204. D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2),
  205. D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4),
  206. D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8),
  207. D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2),
  208. D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
  209. D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0),
  210. D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0),
  211. D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0),
  212. D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0),
  213. D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0),
  214. D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0),
  215. D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0),
  216. D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),
  217. D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, 0xba0, 0xba1, 0, 0xba2, 0, 0xbc0, 0xbc1),
  218. D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, 0x323, 0x324, 0, 0, 0, 0, 0),
  219. D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, 0x403, 0x404, 0, 0, 0, 0, 0),
  220. D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, 0x484, 0x485, 0, 0, 0, 0, 0),
  221. D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, 0xc60, 0xc61, 0, 0, 0, 0, 0),
  222. D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, 0x424, 0x423, 0, 0, 0, 0, 0),
  223. D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0),
  224. D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0),
  225. D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0),
  226. D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141),
  227. D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1),
  228. D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2),
  229. D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5),
  230. D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2),
  231. D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2),
  232. D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0),
  233. D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0),
  234. D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0),
  235. D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1),
  236. D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0),
  237. D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0),
  238. D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0),
  239. D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0),
  240. D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182),
  241. D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2),
  242. D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25),
  243. D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0),
  244. D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0),
  245. D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0),
  246. D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0),
  247. D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302),
  248. D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2),
  249. D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0),
  250. D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0, 0, 0, 0, 0, 0),
  251. D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82),
  252. D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662),
  253. D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0),
  254. D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0),
  255. D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0),
  256. D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0),
  257. D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0),
  258. D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0),
  259. D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0),
  260. D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0),
  261. D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0),
  262. D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0),
  263. D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0),
  264. D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0),
  265. D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0),
  266. D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0),
  267. D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0),
  268. D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0),
  269. D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0),
  270. /*
  271. * These are not hardware clocks, but are needed to handle the special
  272. * case where we have a 'selector bit' that doesn't just change the
  273. * parent for a clock, but also the gate it's suposed to use.
  274. */
  275. {
  276. .index = R9A06G032_UART_GROUP_012,
  277. .name = "uart_group_012",
  278. .type = K_BITSEL,
  279. .source = 1 + R9A06G032_DIV_UART,
  280. /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
  281. .dual.sel = ((0xec / 4) << 5) | 24,
  282. .dual.group = 0,
  283. },
  284. {
  285. .index = R9A06G032_UART_GROUP_34567,
  286. .name = "uart_group_34567",
  287. .type = K_BITSEL,
  288. .source = 1 + R9A06G032_DIV_P2_PG,
  289. /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
  290. .dual.sel = ((0x34 / 4) << 5) | 30,
  291. .dual.group = 1,
  292. },
  293. D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
  294. D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
  295. D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
  296. D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763),
  297. D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767),
  298. D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b),
  299. D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f),
  300. D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773),
  301. };
  302. struct r9a06g032_priv {
  303. struct clk_onecell_data data;
  304. spinlock_t lock; /* protects concurent access to gates */
  305. void __iomem *reg;
  306. };
  307. /* register/bit pairs are encoded as an uint16_t */
  308. static void
  309. clk_rdesc_set(struct r9a06g032_priv *clocks,
  310. u16 one, unsigned int on)
  311. {
  312. u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
  313. u32 val = readl(reg);
  314. val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f));
  315. writel(val, reg);
  316. }
  317. static int
  318. clk_rdesc_get(struct r9a06g032_priv *clocks,
  319. uint16_t one)
  320. {
  321. u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
  322. u32 val = readl(reg);
  323. return !!(val & (1U << (one & 0x1f)));
  324. }
  325. /*
  326. * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's
  327. * clock gate framework as the gates on the R9A06G032 have a special enabling
  328. * sequence, therefore we use this little proxy.
  329. */
  330. struct r9a06g032_clk_gate {
  331. struct clk_hw hw;
  332. struct r9a06g032_priv *clocks;
  333. u16 index;
  334. struct r9a06g032_gate gate;
  335. };
  336. #define to_r9a06g032_gate(_hw) container_of(_hw, struct r9a06g032_clk_gate, hw)
  337. static int create_add_module_clock(struct of_phandle_args *clkspec,
  338. struct device *dev)
  339. {
  340. struct clk *clk;
  341. int error;
  342. clk = of_clk_get_from_provider(clkspec);
  343. if (IS_ERR(clk))
  344. return PTR_ERR(clk);
  345. error = pm_clk_create(dev);
  346. if (error) {
  347. clk_put(clk);
  348. return error;
  349. }
  350. error = pm_clk_add_clk(dev, clk);
  351. if (error) {
  352. pm_clk_destroy(dev);
  353. clk_put(clk);
  354. }
  355. return error;
  356. }
  357. static int r9a06g032_attach_dev(struct generic_pm_domain *pd,
  358. struct device *dev)
  359. {
  360. struct device_node *np = dev->of_node;
  361. struct of_phandle_args clkspec;
  362. int i = 0;
  363. int error;
  364. int index;
  365. while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
  366. &clkspec)) {
  367. if (clkspec.np != pd->dev.of_node)
  368. continue;
  369. index = clkspec.args[0];
  370. if (index < R9A06G032_CLOCK_COUNT &&
  371. r9a06g032_clocks[index].managed) {
  372. error = create_add_module_clock(&clkspec, dev);
  373. of_node_put(clkspec.np);
  374. if (error)
  375. return error;
  376. }
  377. i++;
  378. }
  379. return 0;
  380. }
  381. static void r9a06g032_detach_dev(struct generic_pm_domain *unused, struct device *dev)
  382. {
  383. if (!pm_clk_no_clocks(dev))
  384. pm_clk_destroy(dev);
  385. }
  386. static int r9a06g032_add_clk_domain(struct device *dev)
  387. {
  388. struct device_node *np = dev->of_node;
  389. struct generic_pm_domain *pd;
  390. pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
  391. if (!pd)
  392. return -ENOMEM;
  393. pd->name = np->name;
  394. pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
  395. GENPD_FLAG_ACTIVE_WAKEUP;
  396. pd->attach_dev = r9a06g032_attach_dev;
  397. pd->detach_dev = r9a06g032_detach_dev;
  398. pm_genpd_init(pd, &pm_domain_always_on_gov, false);
  399. of_genpd_add_provider_simple(np, pd);
  400. return 0;
  401. }
  402. static void
  403. r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks,
  404. struct r9a06g032_gate *g, int on)
  405. {
  406. unsigned long flags;
  407. WARN_ON(!g->gate);
  408. spin_lock_irqsave(&clocks->lock, flags);
  409. clk_rdesc_set(clocks, g->gate, on);
  410. /* De-assert reset */
  411. if (g->reset)
  412. clk_rdesc_set(clocks, g->reset, 1);
  413. spin_unlock_irqrestore(&clocks->lock, flags);
  414. /* Hardware manual recommends 5us delay after enabling clock & reset */
  415. udelay(5);
  416. /* If the peripheral is memory mapped (i.e. an AXI slave), there is an
  417. * associated SLVRDY bit in the System Controller that needs to be set
  418. * so that the FlexWAY bus fabric passes on the read/write requests.
  419. */
  420. if (g->ready || g->midle) {
  421. spin_lock_irqsave(&clocks->lock, flags);
  422. if (g->ready)
  423. clk_rdesc_set(clocks, g->ready, on);
  424. /* Clear 'Master Idle Request' bit */
  425. if (g->midle)
  426. clk_rdesc_set(clocks, g->midle, !on);
  427. spin_unlock_irqrestore(&clocks->lock, flags);
  428. }
  429. /* Note: We don't wait for FlexWAY Socket Connection signal */
  430. }
  431. static int r9a06g032_clk_gate_enable(struct clk_hw *hw)
  432. {
  433. struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
  434. r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);
  435. return 0;
  436. }
  437. static void r9a06g032_clk_gate_disable(struct clk_hw *hw)
  438. {
  439. struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
  440. r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);
  441. }
  442. static int r9a06g032_clk_gate_is_enabled(struct clk_hw *hw)
  443. {
  444. struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
  445. /* if clock is in reset, the gate might be on, and still not 'be' on */
  446. if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset))
  447. return 0;
  448. return clk_rdesc_get(g->clocks, g->gate.gate);
  449. }
  450. static const struct clk_ops r9a06g032_clk_gate_ops = {
  451. .enable = r9a06g032_clk_gate_enable,
  452. .disable = r9a06g032_clk_gate_disable,
  453. .is_enabled = r9a06g032_clk_gate_is_enabled,
  454. };
  455. static struct clk *
  456. r9a06g032_register_gate(struct r9a06g032_priv *clocks,
  457. const char *parent_name,
  458. const struct r9a06g032_clkdesc *desc)
  459. {
  460. struct clk *clk;
  461. struct r9a06g032_clk_gate *g;
  462. struct clk_init_data init;
  463. g = kzalloc(sizeof(*g), GFP_KERNEL);
  464. if (!g)
  465. return NULL;
  466. init.name = desc->name;
  467. init.ops = &r9a06g032_clk_gate_ops;
  468. init.flags = CLK_SET_RATE_PARENT;
  469. init.parent_names = parent_name ? &parent_name : NULL;
  470. init.num_parents = parent_name ? 1 : 0;
  471. g->clocks = clocks;
  472. g->index = desc->index;
  473. g->gate = desc->gate;
  474. g->hw.init = &init;
  475. /*
  476. * important here, some clocks are already in use by the CM3, we
  477. * have to assume they are not Linux's to play with and try to disable
  478. * at the end of the boot!
  479. */
  480. if (r9a06g032_clk_gate_is_enabled(&g->hw)) {
  481. init.flags |= CLK_IS_CRITICAL;
  482. pr_debug("%s was enabled, making read-only\n", desc->name);
  483. }
  484. clk = clk_register(NULL, &g->hw);
  485. if (IS_ERR(clk)) {
  486. kfree(g);
  487. return NULL;
  488. }
  489. return clk;
  490. }
  491. struct r9a06g032_clk_div {
  492. struct clk_hw hw;
  493. struct r9a06g032_priv *clocks;
  494. u16 index;
  495. u16 reg;
  496. u16 min, max;
  497. u8 table_size;
  498. u16 table[8]; /* we know there are no more than 8 */
  499. };
  500. #define to_r9a06g032_div(_hw) \
  501. container_of(_hw, struct r9a06g032_clk_div, hw)
  502. static unsigned long
  503. r9a06g032_div_recalc_rate(struct clk_hw *hw,
  504. unsigned long parent_rate)
  505. {
  506. struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
  507. u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
  508. u32 div = readl(reg);
  509. if (div < clk->min)
  510. div = clk->min;
  511. else if (div > clk->max)
  512. div = clk->max;
  513. return DIV_ROUND_UP(parent_rate, div);
  514. }
  515. /*
  516. * Attempts to find a value that is in range of min,max,
  517. * and if a table of set dividers was specified for this
  518. * register, try to find the fixed divider that is the closest
  519. * to the target frequency
  520. */
  521. static long
  522. r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk,
  523. unsigned long rate, unsigned long prate)
  524. {
  525. /* + 1 to cope with rates that have the remainder dropped */
  526. u32 div = DIV_ROUND_UP(prate, rate + 1);
  527. int i;
  528. if (div <= clk->min)
  529. return clk->min;
  530. if (div >= clk->max)
  531. return clk->max;
  532. for (i = 0; clk->table_size && i < clk->table_size - 1; i++) {
  533. if (div >= clk->table[i] && div <= clk->table[i + 1]) {
  534. unsigned long m = rate -
  535. DIV_ROUND_UP(prate, clk->table[i]);
  536. unsigned long p =
  537. DIV_ROUND_UP(prate, clk->table[i + 1]) -
  538. rate;
  539. /*
  540. * select the divider that generates
  541. * the value closest to the ideal frequency
  542. */
  543. div = p >= m ? clk->table[i] : clk->table[i + 1];
  544. return div;
  545. }
  546. }
  547. return div;
  548. }
  549. static long
  550. r9a06g032_div_round_rate(struct clk_hw *hw,
  551. unsigned long rate, unsigned long *prate)
  552. {
  553. struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
  554. u32 div = DIV_ROUND_UP(*prate, rate);
  555. pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__,
  556. hw->clk, rate, *prate, div);
  557. pr_devel(" min %d (%ld) max %d (%ld)\n",
  558. clk->min, DIV_ROUND_UP(*prate, clk->min),
  559. clk->max, DIV_ROUND_UP(*prate, clk->max));
  560. div = r9a06g032_div_clamp_div(clk, rate, *prate);
  561. /*
  562. * this is a hack. Currently the serial driver asks for a clock rate
  563. * that is 16 times the baud rate -- and that is wildly outside the
  564. * range of the UART divider, somehow there is no provision for that
  565. * case of 'let the divider as is if outside range'.
  566. * The serial driver *shouldn't* play with these clocks anyway, there's
  567. * several uarts attached to this divider, and changing this impacts
  568. * everyone.
  569. */
  570. if (clk->index == R9A06G032_DIV_UART ||
  571. clk->index == R9A06G032_DIV_P2_PG) {
  572. pr_devel("%s div uart hack!\n", __func__);
  573. return clk_get_rate(hw->clk);
  574. }
  575. pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,
  576. *prate, div, DIV_ROUND_UP(*prate, div));
  577. return DIV_ROUND_UP(*prate, div);
  578. }
  579. static int
  580. r9a06g032_div_set_rate(struct clk_hw *hw,
  581. unsigned long rate, unsigned long parent_rate)
  582. {
  583. struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
  584. /* + 1 to cope with rates that have the remainder dropped */
  585. u32 div = DIV_ROUND_UP(parent_rate, rate + 1);
  586. u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
  587. pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk,
  588. rate, parent_rate, div);
  589. /*
  590. * Need to write the bit 31 with the divider value to
  591. * latch it. Technically we should wait until it has been
  592. * cleared too.
  593. * TODO: Find whether this callback is sleepable, in case
  594. * the hardware /does/ require some sort of spinloop here.
  595. */
  596. writel(div | BIT(31), reg);
  597. return 0;
  598. }
  599. static const struct clk_ops r9a06g032_clk_div_ops = {
  600. .recalc_rate = r9a06g032_div_recalc_rate,
  601. .round_rate = r9a06g032_div_round_rate,
  602. .set_rate = r9a06g032_div_set_rate,
  603. };
  604. static struct clk *
  605. r9a06g032_register_div(struct r9a06g032_priv *clocks,
  606. const char *parent_name,
  607. const struct r9a06g032_clkdesc *desc)
  608. {
  609. struct r9a06g032_clk_div *div;
  610. struct clk *clk;
  611. struct clk_init_data init;
  612. unsigned int i;
  613. div = kzalloc(sizeof(*div), GFP_KERNEL);
  614. if (!div)
  615. return NULL;
  616. init.name = desc->name;
  617. init.ops = &r9a06g032_clk_div_ops;
  618. init.flags = CLK_SET_RATE_PARENT;
  619. init.parent_names = parent_name ? &parent_name : NULL;
  620. init.num_parents = parent_name ? 1 : 0;
  621. div->clocks = clocks;
  622. div->index = desc->index;
  623. div->reg = desc->reg;
  624. div->hw.init = &init;
  625. div->min = desc->div_min;
  626. div->max = desc->div_max;
  627. /* populate (optional) divider table fixed values */
  628. for (i = 0; i < ARRAY_SIZE(div->table) &&
  629. i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) {
  630. div->table[div->table_size++] = desc->div_table[i];
  631. }
  632. clk = clk_register(NULL, &div->hw);
  633. if (IS_ERR(clk)) {
  634. kfree(div);
  635. return NULL;
  636. }
  637. return clk;
  638. }
  639. /*
  640. * This clock provider handles the case of the R9A06G032 where you have
  641. * peripherals that have two potential clock source and two gates, one for
  642. * each of the clock source - the used clock source (for all sub clocks)
  643. * is selected by a single bit.
  644. * That single bit affects all sub-clocks, and therefore needs to change the
  645. * active gate (and turn the others off) and force a recalculation of the rates.
  646. *
  647. * This implements two clock providers, one 'bitselect' that
  648. * handles the switch between both parents, and another 'dualgate'
  649. * that knows which gate to poke at, depending on the parent's bit position.
  650. */
  651. struct r9a06g032_clk_bitsel {
  652. struct clk_hw hw;
  653. struct r9a06g032_priv *clocks;
  654. u16 index;
  655. u16 selector; /* selector register + bit */
  656. };
  657. #define to_clk_bitselect(_hw) \
  658. container_of(_hw, struct r9a06g032_clk_bitsel, hw)
  659. static u8 r9a06g032_clk_mux_get_parent(struct clk_hw *hw)
  660. {
  661. struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw);
  662. return clk_rdesc_get(set->clocks, set->selector);
  663. }
  664. static int r9a06g032_clk_mux_set_parent(struct clk_hw *hw, u8 index)
  665. {
  666. struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw);
  667. /* a single bit in the register selects one of two parent clocks */
  668. clk_rdesc_set(set->clocks, set->selector, !!index);
  669. return 0;
  670. }
  671. static const struct clk_ops clk_bitselect_ops = {
  672. .get_parent = r9a06g032_clk_mux_get_parent,
  673. .set_parent = r9a06g032_clk_mux_set_parent,
  674. };
  675. static struct clk *
  676. r9a06g032_register_bitsel(struct r9a06g032_priv *clocks,
  677. const char *parent_name,
  678. const struct r9a06g032_clkdesc *desc)
  679. {
  680. struct clk *clk;
  681. struct r9a06g032_clk_bitsel *g;
  682. struct clk_init_data init;
  683. const char *names[2];
  684. /* allocate the gate */
  685. g = kzalloc(sizeof(*g), GFP_KERNEL);
  686. if (!g)
  687. return NULL;
  688. names[0] = parent_name;
  689. names[1] = "clk_pll_usb";
  690. init.name = desc->name;
  691. init.ops = &clk_bitselect_ops;
  692. init.flags = CLK_SET_RATE_PARENT;
  693. init.parent_names = names;
  694. init.num_parents = 2;
  695. g->clocks = clocks;
  696. g->index = desc->index;
  697. g->selector = desc->dual.sel;
  698. g->hw.init = &init;
  699. clk = clk_register(NULL, &g->hw);
  700. if (IS_ERR(clk)) {
  701. kfree(g);
  702. return NULL;
  703. }
  704. return clk;
  705. }
  706. struct r9a06g032_clk_dualgate {
  707. struct clk_hw hw;
  708. struct r9a06g032_priv *clocks;
  709. u16 index;
  710. u16 selector; /* selector register + bit */
  711. struct r9a06g032_gate gate[2];
  712. };
  713. #define to_clk_dualgate(_hw) \
  714. container_of(_hw, struct r9a06g032_clk_dualgate, hw)
  715. static int
  716. r9a06g032_clk_dualgate_setenable(struct r9a06g032_clk_dualgate *g, int enable)
  717. {
  718. u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
  719. /* we always turn off the 'other' gate, regardless */
  720. r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);
  721. r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);
  722. return 0;
  723. }
  724. static int r9a06g032_clk_dualgate_enable(struct clk_hw *hw)
  725. {
  726. struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
  727. r9a06g032_clk_dualgate_setenable(gate, 1);
  728. return 0;
  729. }
  730. static void r9a06g032_clk_dualgate_disable(struct clk_hw *hw)
  731. {
  732. struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
  733. r9a06g032_clk_dualgate_setenable(gate, 0);
  734. }
  735. static int r9a06g032_clk_dualgate_is_enabled(struct clk_hw *hw)
  736. {
  737. struct r9a06g032_clk_dualgate *g = to_clk_dualgate(hw);
  738. u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
  739. return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);
  740. }
  741. static const struct clk_ops r9a06g032_clk_dualgate_ops = {
  742. .enable = r9a06g032_clk_dualgate_enable,
  743. .disable = r9a06g032_clk_dualgate_disable,
  744. .is_enabled = r9a06g032_clk_dualgate_is_enabled,
  745. };
  746. static struct clk *
  747. r9a06g032_register_dualgate(struct r9a06g032_priv *clocks,
  748. const char *parent_name,
  749. const struct r9a06g032_clkdesc *desc,
  750. uint16_t sel)
  751. {
  752. struct r9a06g032_clk_dualgate *g;
  753. struct clk *clk;
  754. struct clk_init_data init;
  755. /* allocate the gate */
  756. g = kzalloc(sizeof(*g), GFP_KERNEL);
  757. if (!g)
  758. return NULL;
  759. g->clocks = clocks;
  760. g->index = desc->index;
  761. g->selector = sel;
  762. g->gate[0].gate = desc->dual.g1;
  763. g->gate[0].reset = desc->dual.r1;
  764. g->gate[1].gate = desc->dual.g2;
  765. g->gate[1].reset = desc->dual.r2;
  766. init.name = desc->name;
  767. init.ops = &r9a06g032_clk_dualgate_ops;
  768. init.flags = CLK_SET_RATE_PARENT;
  769. init.parent_names = &parent_name;
  770. init.num_parents = 1;
  771. g->hw.init = &init;
  772. /*
  773. * important here, some clocks are already in use by the CM3, we
  774. * have to assume they are not Linux's to play with and try to disable
  775. * at the end of the boot!
  776. */
  777. if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) {
  778. init.flags |= CLK_IS_CRITICAL;
  779. pr_debug("%s was enabled, making read-only\n", desc->name);
  780. }
  781. clk = clk_register(NULL, &g->hw);
  782. if (IS_ERR(clk)) {
  783. kfree(g);
  784. return NULL;
  785. }
  786. return clk;
  787. }
  788. static void r9a06g032_clocks_del_clk_provider(void *data)
  789. {
  790. of_clk_del_provider(data);
  791. }
  792. static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
  793. {
  794. struct device *dev = &pdev->dev;
  795. struct device_node *np = dev->of_node;
  796. struct r9a06g032_priv *clocks;
  797. struct clk **clks;
  798. struct clk *mclk;
  799. unsigned int i;
  800. u16 uart_group_sel[2];
  801. int error;
  802. clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL);
  803. clks = devm_kcalloc(dev, R9A06G032_CLOCK_COUNT, sizeof(struct clk *),
  804. GFP_KERNEL);
  805. if (!clocks || !clks)
  806. return -ENOMEM;
  807. spin_lock_init(&clocks->lock);
  808. clocks->data.clks = clks;
  809. clocks->data.clk_num = R9A06G032_CLOCK_COUNT;
  810. mclk = devm_clk_get(dev, "mclk");
  811. if (IS_ERR(mclk))
  812. return PTR_ERR(mclk);
  813. clocks->reg = of_iomap(np, 0);
  814. if (WARN_ON(!clocks->reg))
  815. return -ENOMEM;
  816. for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) {
  817. const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i];
  818. const char *parent_name = d->source ?
  819. __clk_get_name(clocks->data.clks[d->source - 1]) :
  820. __clk_get_name(mclk);
  821. struct clk *clk = NULL;
  822. switch (d->type) {
  823. case K_FFC:
  824. clk = clk_register_fixed_factor(NULL, d->name,
  825. parent_name, 0,
  826. d->mul, d->div);
  827. break;
  828. case K_GATE:
  829. clk = r9a06g032_register_gate(clocks, parent_name, d);
  830. break;
  831. case K_DIV:
  832. clk = r9a06g032_register_div(clocks, parent_name, d);
  833. break;
  834. case K_BITSEL:
  835. /* keep that selector register around */
  836. uart_group_sel[d->dual.group] = d->dual.sel;
  837. clk = r9a06g032_register_bitsel(clocks, parent_name, d);
  838. break;
  839. case K_DUALGATE:
  840. clk = r9a06g032_register_dualgate(clocks, parent_name,
  841. d,
  842. uart_group_sel[d->dual.group]);
  843. break;
  844. }
  845. clocks->data.clks[d->index] = clk;
  846. }
  847. error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data);
  848. if (error)
  849. return error;
  850. error = devm_add_action_or_reset(dev,
  851. r9a06g032_clocks_del_clk_provider, np);
  852. if (error)
  853. return error;
  854. return r9a06g032_add_clk_domain(dev);
  855. }
  856. static const struct of_device_id r9a06g032_match[] = {
  857. { .compatible = "renesas,r9a06g032-sysctrl" },
  858. { }
  859. };
  860. static struct platform_driver r9a06g032_clock_driver = {
  861. .driver = {
  862. .name = "renesas,r9a06g032-sysctrl",
  863. .of_match_table = r9a06g032_match,
  864. },
  865. };
  866. static int __init r9a06g032_clocks_init(void)
  867. {
  868. return platform_driver_probe(&r9a06g032_clock_driver,
  869. r9a06g032_clocks_probe);
  870. }
  871. subsys_initcall(r9a06g032_clocks_init);