r8a779a0-cpg-mssr.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
  4. *
  5. * Copyright (C) 2020 Renesas Electronics Corp.
  6. *
  7. * Based on r8a7795-cpg-mssr.c
  8. *
  9. * Copyright (C) 2015 Glider bvba
  10. * Copyright (C) 2015 Renesas Electronics Corp.
  11. */
  12. #include <linux/bug.h>
  13. #include <linux/bitfield.h>
  14. #include <linux/clk.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/device.h>
  17. #include <linux/err.h>
  18. #include <linux/init.h>
  19. #include <linux/io.h>
  20. #include <linux/kernel.h>
  21. #include <linux/pm.h>
  22. #include <linux/slab.h>
  23. #include <linux/soc/renesas/rcar-rst.h>
  24. #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
  25. #include "renesas-cpg-mssr.h"
  26. enum rcar_r8a779a0_clk_types {
  27. CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,
  28. CLK_TYPE_R8A779A0_PLL1,
  29. CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */
  30. CLK_TYPE_R8A779A0_PLL5,
  31. CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */
  32. CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
  33. };
  34. struct rcar_r8a779a0_cpg_pll_config {
  35. u8 extal_div;
  36. u8 pll1_mult;
  37. u8 pll1_div;
  38. u8 pll5_mult;
  39. u8 pll5_div;
  40. u8 osc_prediv;
  41. };
  42. enum clk_ids {
  43. /* Core Clock Outputs exported to DT */
  44. LAST_DT_CORE_CLK = R8A779A0_CLK_OSC,
  45. /* External Input Clocks */
  46. CLK_EXTAL,
  47. CLK_EXTALR,
  48. /* Internal Core Clocks */
  49. CLK_MAIN,
  50. CLK_PLL1,
  51. CLK_PLL20,
  52. CLK_PLL21,
  53. CLK_PLL30,
  54. CLK_PLL31,
  55. CLK_PLL5,
  56. CLK_PLL1_DIV2,
  57. CLK_PLL20_DIV2,
  58. CLK_PLL21_DIV2,
  59. CLK_PLL30_DIV2,
  60. CLK_PLL31_DIV2,
  61. CLK_PLL5_DIV2,
  62. CLK_PLL5_DIV4,
  63. CLK_S1,
  64. CLK_S3,
  65. CLK_SDSRC,
  66. CLK_RPCSRC,
  67. CLK_OCO,
  68. /* Module Clocks */
  69. MOD_CLK_BASE
  70. };
  71. #define DEF_PLL(_name, _id, _offset) \
  72. DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
  73. .offset = _offset)
  74. #define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
  75. DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \
  76. (_parent0) << 16 | (_parent1), \
  77. .div = (_div0) << 16 | (_div1), .offset = _md)
  78. #define DEF_OSC(_name, _id, _parent, _div) \
  79. DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)
  80. static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
  81. /* External Clock Inputs */
  82. DEF_INPUT("extal", CLK_EXTAL),
  83. DEF_INPUT("extalr", CLK_EXTALR),
  84. /* Internal Core Clocks */
  85. DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
  86. DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
  87. DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
  88. DEF_PLL(".pll20", CLK_PLL20, 0x0834),
  89. DEF_PLL(".pll21", CLK_PLL21, 0x0838),
  90. DEF_PLL(".pll30", CLK_PLL30, 0x083c),
  91. DEF_PLL(".pll31", CLK_PLL31, 0x0840),
  92. DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
  93. DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1),
  94. DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1),
  95. DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1),
  96. DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1),
  97. DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
  98. DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
  99. DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1),
  100. DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
  101. DEF_RATE(".oco", CLK_OCO, 32768),
  102. /* Core Clock Outputs */
  103. DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
  104. DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
  105. DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
  106. DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1),
  107. DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1),
  108. DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1),
  109. DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1),
  110. DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1),
  111. DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1),
  112. DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1),
  113. DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1),
  114. DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1),
  115. DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1),
  116. DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1),
  117. DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1),
  118. DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1),
  119. DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1),
  120. DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1),
  121. DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1),
  122. DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1),
  123. DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
  124. DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
  125. DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
  126. DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
  127. DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
  128. DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
  129. };
  130. static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
  131. DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8),
  132. DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8),
  133. DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
  134. DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8),
  135. };
  136. static spinlock_t cpg_lock;
  137. static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata;
  138. static unsigned int cpg_clk_extalr __initdata;
  139. static u32 cpg_mode __initdata;
  140. struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
  141. const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
  142. struct clk **clks, void __iomem *base,
  143. struct raw_notifier_head *notifiers)
  144. {
  145. const struct clk *parent;
  146. unsigned int mult = 1;
  147. unsigned int div = 1;
  148. u32 value;
  149. parent = clks[core->parent & 0xffff]; /* some types use high bits */
  150. if (IS_ERR(parent))
  151. return ERR_CAST(parent);
  152. switch (core->type) {
  153. case CLK_TYPE_R8A779A0_MAIN:
  154. div = cpg_pll_config->extal_div;
  155. break;
  156. case CLK_TYPE_R8A779A0_PLL1:
  157. mult = cpg_pll_config->pll1_mult;
  158. div = cpg_pll_config->pll1_div;
  159. break;
  160. case CLK_TYPE_R8A779A0_PLL2X_3X:
  161. value = readl(base + core->offset);
  162. mult = (((value >> 24) & 0x7f) + 1) * 2;
  163. break;
  164. case CLK_TYPE_R8A779A0_PLL5:
  165. mult = cpg_pll_config->pll5_mult;
  166. div = cpg_pll_config->pll5_div;
  167. break;
  168. case CLK_TYPE_R8A779A0_MDSEL:
  169. /*
  170. * Clock selectable between two parents and two fixed dividers
  171. * using a mode pin
  172. */
  173. if (cpg_mode & BIT(core->offset)) {
  174. div = core->div & 0xffff;
  175. } else {
  176. parent = clks[core->parent >> 16];
  177. if (IS_ERR(parent))
  178. return ERR_CAST(parent);
  179. div = core->div >> 16;
  180. }
  181. mult = 1;
  182. break;
  183. case CLK_TYPE_R8A779A0_OSC:
  184. /*
  185. * Clock combining OSC EXTAL predivider and a fixed divider
  186. */
  187. div = cpg_pll_config->osc_prediv * core->div;
  188. break;
  189. default:
  190. return ERR_PTR(-EINVAL);
  191. }
  192. return clk_register_fixed_factor(NULL, core->name,
  193. __clk_get_name(parent), 0, mult, div);
  194. }
  195. /*
  196. * CPG Clock Data
  197. */
  198. /*
  199. * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
  200. * 14 13 (MHz) 21 31
  201. * --------------------------------------------------------
  202. * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16
  203. * 0 1 20 x 1 x106 x180 x106 x120 x160 /19
  204. * 1 0 Prohibited setting
  205. * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32
  206. */
  207. #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
  208. (((md) & BIT(13)) >> 13))
  209. static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = {
  210. /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
  211. { 1, 128, 1, 192, 1, 16, },
  212. { 1, 106, 1, 160, 1, 19, },
  213. { 0, 0, 0, 0, 0, 0, },
  214. { 2, 128, 1, 192, 1, 32, },
  215. };
  216. static int __init r8a779a0_cpg_mssr_init(struct device *dev)
  217. {
  218. int error;
  219. error = rcar_rst_read_mode_pins(&cpg_mode);
  220. if (error)
  221. return error;
  222. cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
  223. cpg_clk_extalr = CLK_EXTALR;
  224. spin_lock_init(&cpg_lock);
  225. return 0;
  226. }
  227. const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
  228. /* Core Clocks */
  229. .core_clks = r8a779a0_core_clks,
  230. .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks),
  231. .last_dt_core_clk = LAST_DT_CORE_CLK,
  232. .num_total_core_clks = MOD_CLK_BASE,
  233. /* Module Clocks */
  234. .mod_clks = r8a779a0_mod_clks,
  235. .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
  236. .num_hw_mod_clks = 15 * 32,
  237. /* Callbacks */
  238. .init = r8a779a0_cpg_mssr_init,
  239. .cpg_clk_register = rcar_r8a779a0_cpg_clk_register,
  240. .reg_layout = CLK_REG_LAYOUT_RCAR_V3U,
  241. };