r8a77995-cpg-mssr.c 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a77995 Clock Pulse Generator / Module Standby and Software Reset
  4. *
  5. * Copyright (C) 2017 Glider bvba
  6. *
  7. * Based on r8a7795-cpg-mssr.c
  8. *
  9. * Copyright (C) 2015 Glider bvba
  10. * Copyright (C) 2015 Renesas Electronics Corp.
  11. */
  12. #include <linux/device.h>
  13. #include <linux/init.h>
  14. #include <linux/kernel.h>
  15. #include <linux/soc/renesas/rcar-rst.h>
  16. #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
  17. #include "renesas-cpg-mssr.h"
  18. #include "rcar-gen3-cpg.h"
  19. enum clk_ids {
  20. /* Core Clock Outputs exported to DT */
  21. LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
  22. /* External Input Clocks */
  23. CLK_EXTAL,
  24. /* Internal Core Clocks */
  25. CLK_MAIN,
  26. CLK_PLL0,
  27. CLK_PLL1,
  28. CLK_PLL3,
  29. CLK_PLL0D2,
  30. CLK_PLL0D3,
  31. CLK_PLL0D5,
  32. CLK_PLL1D2,
  33. CLK_PE,
  34. CLK_S0,
  35. CLK_S1,
  36. CLK_S2,
  37. CLK_S3,
  38. CLK_SDSRC,
  39. CLK_RINT,
  40. CLK_OCO,
  41. /* Module Clocks */
  42. MOD_CLK_BASE
  43. };
  44. static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
  45. /* External Clock Inputs */
  46. DEF_INPUT("extal", CLK_EXTAL),
  47. /* Internal Core Clocks */
  48. DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  49. DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  50. DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  51. DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
  52. DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
  53. DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
  54. DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
  55. DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
  56. DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
  57. DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
  58. DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
  59. DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
  60. DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
  61. DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
  62. DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
  63. DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
  64. /* Core Clock Outputs */
  65. DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1),
  66. DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
  67. DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
  68. DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
  69. DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
  70. DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
  71. DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
  72. DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
  73. DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
  74. DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
  75. DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
  76. DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
  77. DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
  78. DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
  79. DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
  80. DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
  81. DEF_FIXED("cr", R8A77995_CLK_CR, CLK_PLL1D2, 2, 1),
  82. DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
  83. DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
  84. DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
  85. DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
  86. DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
  87. DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
  88. DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
  89. DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
  90. DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
  91. DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
  92. DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
  93. };
  94. static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
  95. DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
  96. DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
  97. DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
  98. DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
  99. DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
  100. DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
  101. DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
  102. DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
  103. DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
  104. DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
  105. DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
  106. DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
  107. DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
  108. DEF_MOD("cmt3", 300, R8A77995_CLK_R),
  109. DEF_MOD("cmt2", 301, R8A77995_CLK_R),
  110. DEF_MOD("cmt1", 302, R8A77995_CLK_R),
  111. DEF_MOD("cmt0", 303, R8A77995_CLK_R),
  112. DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
  113. DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
  114. DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
  115. DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
  116. DEF_MOD("rwdt", 402, R8A77995_CLK_R),
  117. DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
  118. DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
  119. DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2),
  120. DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
  121. DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
  122. DEF_MOD("thermal", 522, R8A77995_CLK_CP),
  123. DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
  124. DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
  125. DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
  126. DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
  127. DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
  128. DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
  129. DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
  130. DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
  131. DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
  132. DEF_MOD("cmm1", 710, R8A77995_CLK_S1D1),
  133. DEF_MOD("cmm0", 711, R8A77995_CLK_S1D1),
  134. DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
  135. DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
  136. DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
  137. DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
  138. DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
  139. DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
  140. DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
  141. DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
  142. DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
  143. DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
  144. DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
  145. DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
  146. DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
  147. DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
  148. DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
  149. DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
  150. DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
  151. DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
  152. DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
  153. DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
  154. DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
  155. DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
  156. DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
  157. DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
  158. DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
  159. DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
  160. DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
  161. DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
  162. DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
  163. DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
  164. };
  165. static const unsigned int r8a77995_crit_mod_clks[] __initconst = {
  166. MOD_CLK_ID(402), /* RWDT */
  167. MOD_CLK_ID(408), /* INTC-AP (GIC) */
  168. };
  169. /*
  170. * CPG Clock Data
  171. */
  172. /*
  173. * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
  174. *--------------------------------------------------------------------
  175. * 0 48 x 1 x250/4 x100/3 x100/3
  176. * 1 48 x 1 x250/4 x100/3 x58/3
  177. */
  178. #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
  179. static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
  180. /* EXTAL div PLL1 mult/div PLL3 mult/div */
  181. { 1, 100, 3, 100, 3, },
  182. { 1, 100, 3, 58, 3, },
  183. };
  184. static int __init r8a77995_cpg_mssr_init(struct device *dev)
  185. {
  186. const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
  187. u32 cpg_mode;
  188. int error;
  189. error = rcar_rst_read_mode_pins(&cpg_mode);
  190. if (error)
  191. return error;
  192. cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
  193. return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
  194. }
  195. const struct cpg_mssr_info r8a77995_cpg_mssr_info __initconst = {
  196. /* Core Clocks */
  197. .core_clks = r8a77995_core_clks,
  198. .num_core_clks = ARRAY_SIZE(r8a77995_core_clks),
  199. .last_dt_core_clk = LAST_DT_CORE_CLK,
  200. .num_total_core_clks = MOD_CLK_BASE,
  201. /* Module Clocks */
  202. .mod_clks = r8a77995_mod_clks,
  203. .num_mod_clks = ARRAY_SIZE(r8a77995_mod_clks),
  204. .num_hw_mod_clks = 12 * 32,
  205. /* Critical Module Clocks */
  206. .crit_mod_clks = r8a77995_crit_mod_clks,
  207. .num_crit_mod_clks = ARRAY_SIZE(r8a77995_crit_mod_clks),
  208. /* Callbacks */
  209. .init = r8a77995_cpg_mssr_init,
  210. .cpg_clk_register = rcar_gen3_cpg_clk_register,
  211. };