r8a77970-cpg-mssr.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
  4. *
  5. * Copyright (C) 2017-2018 Cogent Embedded Inc.
  6. *
  7. * Based on r8a7795-cpg-mssr.c
  8. *
  9. * Copyright (C) 2015 Glider bvba
  10. */
  11. #include <linux/clk-provider.h>
  12. #include <linux/device.h>
  13. #include <linux/init.h>
  14. #include <linux/kernel.h>
  15. #include <linux/soc/renesas/rcar-rst.h>
  16. #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
  17. #include "renesas-cpg-mssr.h"
  18. #include "rcar-gen3-cpg.h"
  19. #define CPG_SD0CKCR 0x0074
  20. enum r8a77970_clk_types {
  21. CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
  22. CLK_TYPE_R8A77970_SD0,
  23. };
  24. enum clk_ids {
  25. /* Core Clock Outputs exported to DT */
  26. LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
  27. /* External Input Clocks */
  28. CLK_EXTAL,
  29. CLK_EXTALR,
  30. /* Internal Core Clocks */
  31. CLK_MAIN,
  32. CLK_PLL0,
  33. CLK_PLL1,
  34. CLK_PLL3,
  35. CLK_PLL1_DIV2,
  36. CLK_PLL1_DIV4,
  37. /* Module Clocks */
  38. MOD_CLK_BASE
  39. };
  40. static spinlock_t cpg_lock;
  41. static const struct clk_div_table cpg_sd0h_div_table[] = {
  42. { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
  43. { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
  44. { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
  45. };
  46. static const struct clk_div_table cpg_sd0_div_table[] = {
  47. { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
  48. { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
  49. { 0, 0 },
  50. };
  51. static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
  52. /* External Clock Inputs */
  53. DEF_INPUT("extal", CLK_EXTAL),
  54. DEF_INPUT("extalr", CLK_EXTALR),
  55. /* Internal Core Clocks */
  56. DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  57. DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
  58. DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  59. DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  60. DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
  61. DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
  62. /* Core Clock Outputs */
  63. DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
  64. DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
  65. DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
  66. DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
  67. DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1),
  68. DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1),
  69. DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1),
  70. DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1),
  71. DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
  72. DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
  73. DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
  74. CLK_PLL1_DIV2),
  75. DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
  76. DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1),
  77. DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
  78. DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
  79. DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
  80. DEF_FIXED("cpex", R8A77970_CLK_CPEX, CLK_EXTAL, 2, 1),
  81. DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
  82. DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),
  83. DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
  84. DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1),
  85. DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1),
  86. };
  87. static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
  88. DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
  89. DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
  90. DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
  91. DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2),
  92. DEF_MOD("tmu0", 125, R8A77970_CLK_CP),
  93. DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
  94. DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
  95. DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
  96. DEF_MOD("scif1", 206, R8A77970_CLK_S2D4),
  97. DEF_MOD("scif0", 207, R8A77970_CLK_S2D4),
  98. DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
  99. DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
  100. DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
  101. DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
  102. DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
  103. DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
  104. DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
  105. DEF_MOD("cmt3", 300, R8A77970_CLK_R),
  106. DEF_MOD("cmt2", 301, R8A77970_CLK_R),
  107. DEF_MOD("cmt1", 302, R8A77970_CLK_R),
  108. DEF_MOD("cmt0", 303, R8A77970_CLK_R),
  109. DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
  110. DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
  111. DEF_MOD("rwdt", 402, R8A77970_CLK_R),
  112. DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
  113. DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
  114. DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1),
  115. DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1),
  116. DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1),
  117. DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1),
  118. DEF_MOD("thermal", 522, R8A77970_CLK_CP),
  119. DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
  120. DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
  121. DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
  122. DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
  123. DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
  124. DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
  125. DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
  126. DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
  127. DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
  128. DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
  129. DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
  130. DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
  131. DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
  132. DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
  133. DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
  134. DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
  135. DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
  136. DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
  137. DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC),
  138. DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
  139. DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
  140. DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
  141. DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
  142. DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
  143. };
  144. static const unsigned int r8a77970_crit_mod_clks[] __initconst = {
  145. MOD_CLK_ID(402), /* RWDT */
  146. MOD_CLK_ID(408), /* INTC-AP (GIC) */
  147. };
  148. /*
  149. * CPG Clock Data
  150. */
  151. /*
  152. * MD EXTAL PLL0 PLL1 PLL3
  153. * 14 13 19 (MHz)
  154. *-------------------------------------------------
  155. * 0 0 0 16.66 x 1 x192 x192 x96
  156. * 0 0 1 16.66 x 1 x192 x192 x80
  157. * 0 1 0 20 x 1 x160 x160 x80
  158. * 0 1 1 20 x 1 x160 x160 x66
  159. * 1 0 0 27 / 2 x236 x236 x118
  160. * 1 0 1 27 / 2 x236 x236 x98
  161. * 1 1 0 33.33 / 2 x192 x192 x96
  162. * 1 1 1 33.33 / 2 x192 x192 x80
  163. */
  164. #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
  165. (((md) & BIT(13)) >> 12) | \
  166. (((md) & BIT(19)) >> 19))
  167. static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
  168. /* EXTAL div PLL1 mult/div PLL3 mult/div */
  169. { 1, 192, 1, 96, 1, },
  170. { 1, 192, 1, 80, 1, },
  171. { 1, 160, 1, 80, 1, },
  172. { 1, 160, 1, 66, 1, },
  173. { 2, 236, 1, 118, 1, },
  174. { 2, 236, 1, 98, 1, },
  175. { 2, 192, 1, 96, 1, },
  176. { 2, 192, 1, 80, 1, },
  177. };
  178. static int __init r8a77970_cpg_mssr_init(struct device *dev)
  179. {
  180. const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
  181. u32 cpg_mode;
  182. int error;
  183. error = rcar_rst_read_mode_pins(&cpg_mode);
  184. if (error)
  185. return error;
  186. spin_lock_init(&cpg_lock);
  187. cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
  188. return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
  189. }
  190. static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
  191. const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
  192. struct clk **clks, void __iomem *base,
  193. struct raw_notifier_head *notifiers)
  194. {
  195. const struct clk_div_table *table;
  196. const struct clk *parent;
  197. unsigned int shift;
  198. switch (core->type) {
  199. case CLK_TYPE_R8A77970_SD0H:
  200. table = cpg_sd0h_div_table;
  201. shift = 8;
  202. break;
  203. case CLK_TYPE_R8A77970_SD0:
  204. table = cpg_sd0_div_table;
  205. shift = 4;
  206. break;
  207. default:
  208. return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
  209. notifiers);
  210. }
  211. parent = clks[core->parent];
  212. if (IS_ERR(parent))
  213. return ERR_CAST(parent);
  214. return clk_register_divider_table(NULL, core->name,
  215. __clk_get_name(parent), 0,
  216. base + CPG_SD0CKCR,
  217. shift, 4, 0, table, &cpg_lock);
  218. }
  219. const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
  220. /* Core Clocks */
  221. .core_clks = r8a77970_core_clks,
  222. .num_core_clks = ARRAY_SIZE(r8a77970_core_clks),
  223. .last_dt_core_clk = LAST_DT_CORE_CLK,
  224. .num_total_core_clks = MOD_CLK_BASE,
  225. /* Module Clocks */
  226. .mod_clks = r8a77970_mod_clks,
  227. .num_mod_clks = ARRAY_SIZE(r8a77970_mod_clks),
  228. .num_hw_mod_clks = 12 * 32,
  229. /* Critical Module Clocks */
  230. .crit_mod_clks = r8a77970_crit_mod_clks,
  231. .num_crit_mod_clks = ARRAY_SIZE(r8a77970_crit_mod_clks),
  232. /* Callbacks */
  233. .init = r8a77970_cpg_mssr_init,
  234. .cpg_clk_register = r8a77970_cpg_clk_register,
  235. };