r8a7795-cpg-mssr.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
  4. *
  5. * Copyright (C) 2015 Glider bvba
  6. * Copyright (C) 2018-2019 Renesas Electronics Corp.
  7. *
  8. * Based on clk-rcar-gen3.c
  9. *
  10. * Copyright (C) 2015 Renesas Electronics Corp.
  11. */
  12. #include <linux/device.h>
  13. #include <linux/init.h>
  14. #include <linux/kernel.h>
  15. #include <linux/soc/renesas/rcar-rst.h>
  16. #include <linux/sys_soc.h>
  17. #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
  18. #include "renesas-cpg-mssr.h"
  19. #include "rcar-gen3-cpg.h"
  20. enum clk_ids {
  21. /* Core Clock Outputs exported to DT */
  22. LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,
  23. /* External Input Clocks */
  24. CLK_EXTAL,
  25. CLK_EXTALR,
  26. /* Internal Core Clocks */
  27. CLK_MAIN,
  28. CLK_PLL0,
  29. CLK_PLL1,
  30. CLK_PLL2,
  31. CLK_PLL3,
  32. CLK_PLL4,
  33. CLK_PLL1_DIV2,
  34. CLK_PLL1_DIV4,
  35. CLK_S0,
  36. CLK_S1,
  37. CLK_S2,
  38. CLK_S3,
  39. CLK_SDSRC,
  40. CLK_SSPSRC,
  41. CLK_RPCSRC,
  42. CLK_RINT,
  43. /* Module Clocks */
  44. MOD_CLK_BASE
  45. };
  46. static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
  47. /* External Clock Inputs */
  48. DEF_INPUT("extal", CLK_EXTAL),
  49. DEF_INPUT("extalr", CLK_EXTALR),
  50. /* Internal Core Clocks */
  51. DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  52. DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
  53. DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  54. DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
  55. DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  56. DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
  57. DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
  58. DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
  59. DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
  60. DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
  61. DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
  62. DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
  63. DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
  64. DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
  65. DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
  66. CLK_RPCSRC),
  67. DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
  68. R8A7795_CLK_RPC),
  69. DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
  70. /* Core Clock Outputs */
  71. DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
  72. DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
  73. DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
  74. DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
  75. DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
  76. DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
  77. DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
  78. DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
  79. DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
  80. DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
  81. DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
  82. DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
  83. DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
  84. DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
  85. DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
  86. DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
  87. DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
  88. DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
  89. DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
  90. DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
  91. DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
  92. DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
  93. DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
  94. DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
  95. DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
  96. DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
  97. DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
  98. DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
  99. DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
  100. DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1),
  101. DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
  102. DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
  103. DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
  104. DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
  105. DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
  106. DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
  107. };
  108. static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
  109. DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
  110. DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
  111. DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
  112. DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
  113. DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
  114. DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
  115. DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
  116. DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
  117. DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
  118. DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
  119. DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
  120. DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
  121. DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
  122. DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
  123. DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
  124. DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
  125. DEF_MOD("cmt3", 300, R8A7795_CLK_R),
  126. DEF_MOD("cmt2", 301, R8A7795_CLK_R),
  127. DEF_MOD("cmt1", 302, R8A7795_CLK_R),
  128. DEF_MOD("cmt0", 303, R8A7795_CLK_R),
  129. DEF_MOD("tpu0", 304, R8A7795_CLK_S3D4),
  130. DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
  131. DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
  132. DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
  133. DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
  134. DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
  135. DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
  136. DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
  137. DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
  138. DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
  139. DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
  140. DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
  141. DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
  142. DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
  143. DEF_MOD("rwdt", 402, R8A7795_CLK_R),
  144. DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
  145. DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
  146. DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
  147. DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
  148. DEF_MOD("drif31", 508, R8A7795_CLK_S3D2),
  149. DEF_MOD("drif30", 509, R8A7795_CLK_S3D2),
  150. DEF_MOD("drif21", 510, R8A7795_CLK_S3D2),
  151. DEF_MOD("drif20", 511, R8A7795_CLK_S3D2),
  152. DEF_MOD("drif11", 512, R8A7795_CLK_S3D2),
  153. DEF_MOD("drif10", 513, R8A7795_CLK_S3D2),
  154. DEF_MOD("drif01", 514, R8A7795_CLK_S3D2),
  155. DEF_MOD("drif00", 515, R8A7795_CLK_S3D2),
  156. DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
  157. DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
  158. DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
  159. DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
  160. DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
  161. DEF_MOD("thermal", 522, R8A7795_CLK_CP),
  162. DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
  163. DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
  164. DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
  165. DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
  166. DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
  167. DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
  168. DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
  169. DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
  170. DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
  171. DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
  172. DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
  173. DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
  174. DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
  175. DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
  176. DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
  177. DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
  178. DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
  179. DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
  180. DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
  181. DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
  182. DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
  183. DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
  184. DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
  185. DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
  186. DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
  187. DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
  188. DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2),
  189. DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2),
  190. DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
  191. DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2),
  192. DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2),
  193. DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1),
  194. DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
  195. DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
  196. DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
  197. DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
  198. DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
  199. DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
  200. DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
  201. DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
  202. DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
  203. DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
  204. DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
  205. DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
  206. DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
  207. DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
  208. DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
  209. DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
  210. DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
  211. DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
  212. DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
  213. DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
  214. DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
  215. DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
  216. DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
  217. DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
  218. DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
  219. DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
  220. DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
  221. DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
  222. DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
  223. DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
  224. DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
  225. DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
  226. DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
  227. DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
  228. DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
  229. DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
  230. DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
  231. DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
  232. DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
  233. DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2),
  234. DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
  235. DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
  236. DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
  237. DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
  238. DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
  239. DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
  240. DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
  241. DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
  242. DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
  243. DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
  244. DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
  245. DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
  246. DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
  247. DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
  248. DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
  249. DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
  250. DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
  251. DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
  252. DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
  253. DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
  254. DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
  255. DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
  256. DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
  257. DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
  258. DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
  259. DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
  260. DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
  261. DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
  262. DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
  263. DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
  264. DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
  265. DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
  266. DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
  267. DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
  268. };
  269. static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
  270. MOD_CLK_ID(402), /* RWDT */
  271. MOD_CLK_ID(408), /* INTC-AP (GIC) */
  272. };
  273. /*
  274. * CPG Clock Data
  275. */
  276. /*
  277. * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
  278. * 14 13 19 17 (MHz)
  279. *-------------------------------------------------------------------------
  280. * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
  281. * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
  282. * 0 0 1 0 Prohibited setting
  283. * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
  284. * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
  285. * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
  286. * 0 1 1 0 Prohibited setting
  287. * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
  288. * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
  289. * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
  290. * 1 0 1 0 Prohibited setting
  291. * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
  292. * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
  293. * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
  294. * 1 1 1 0 Prohibited setting
  295. * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
  296. */
  297. #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
  298. (((md) & BIT(13)) >> 11) | \
  299. (((md) & BIT(19)) >> 18) | \
  300. (((md) & BIT(17)) >> 17))
  301. static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
  302. /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
  303. { 1, 192, 1, 192, 1, 16, },
  304. { 1, 192, 1, 128, 1, 16, },
  305. { 0, /* Prohibited setting */ },
  306. { 1, 192, 1, 192, 1, 16, },
  307. { 1, 160, 1, 160, 1, 19, },
  308. { 1, 160, 1, 106, 1, 19, },
  309. { 0, /* Prohibited setting */ },
  310. { 1, 160, 1, 160, 1, 19, },
  311. { 1, 128, 1, 128, 1, 24, },
  312. { 1, 128, 1, 84, 1, 24, },
  313. { 0, /* Prohibited setting */ },
  314. { 1, 128, 1, 128, 1, 24, },
  315. { 2, 192, 1, 192, 1, 32, },
  316. { 2, 192, 1, 128, 1, 32, },
  317. { 0, /* Prohibited setting */ },
  318. { 2, 192, 1, 192, 1, 32, },
  319. };
  320. static const struct soc_device_attribute r8a7795es1[] __initconst = {
  321. { .soc_id = "r8a7795", .revision = "ES1.*" },
  322. { /* sentinel */ }
  323. };
  324. /*
  325. * Fixups for R-Car H3 ES1.x
  326. */
  327. static const unsigned int r8a7795es1_mod_nullify[] __initconst = {
  328. MOD_CLK_ID(326), /* USB-DMAC3-0 */
  329. MOD_CLK_ID(329), /* USB-DMAC3-1 */
  330. MOD_CLK_ID(700), /* EHCI/OHCI3 */
  331. MOD_CLK_ID(705), /* HS-USB-IF3 */
  332. };
  333. static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
  334. { MOD_CLK_ID(118), R8A7795_CLK_S2D1 }, /* FDP1-1 */
  335. { MOD_CLK_ID(119), R8A7795_CLK_S2D1 }, /* FDP1-0 */
  336. { MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */
  337. { MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */
  338. { MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */
  339. { MOD_CLK_ID(408), R8A7795_CLK_S3D1 }, /* INTC-AP */
  340. { MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */
  341. { MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */
  342. { MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */
  343. { MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */
  344. { MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */
  345. { MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */
  346. { MOD_CLK_ID(606), R8A7795_CLK_S2D1 }, /* FCPVB1 */
  347. { MOD_CLK_ID(607), R8A7795_CLK_S2D1 }, /* FCPVB0 */
  348. { MOD_CLK_ID(610), R8A7795_CLK_S2D1 }, /* FCPVI1 */
  349. { MOD_CLK_ID(611), R8A7795_CLK_S2D1 }, /* FCPVI0 */
  350. { MOD_CLK_ID(614), R8A7795_CLK_S2D1 }, /* FCPF1 */
  351. { MOD_CLK_ID(615), R8A7795_CLK_S2D1 }, /* FCPF0 */
  352. { MOD_CLK_ID(619), R8A7795_CLK_S2D1 }, /* FCPCS */
  353. { MOD_CLK_ID(621), R8A7795_CLK_S2D1 }, /* VSPD2 */
  354. { MOD_CLK_ID(622), R8A7795_CLK_S2D1 }, /* VSPD1 */
  355. { MOD_CLK_ID(623), R8A7795_CLK_S2D1 }, /* VSPD0 */
  356. { MOD_CLK_ID(624), R8A7795_CLK_S2D1 }, /* VSPBC */
  357. { MOD_CLK_ID(626), R8A7795_CLK_S2D1 }, /* VSPBD */
  358. { MOD_CLK_ID(630), R8A7795_CLK_S2D1 }, /* VSPI1 */
  359. { MOD_CLK_ID(631), R8A7795_CLK_S2D1 }, /* VSPI0 */
  360. { MOD_CLK_ID(804), R8A7795_CLK_S2D1 }, /* VIN7 */
  361. { MOD_CLK_ID(805), R8A7795_CLK_S2D1 }, /* VIN6 */
  362. { MOD_CLK_ID(806), R8A7795_CLK_S2D1 }, /* VIN5 */
  363. { MOD_CLK_ID(807), R8A7795_CLK_S2D1 }, /* VIN4 */
  364. { MOD_CLK_ID(808), R8A7795_CLK_S2D1 }, /* VIN3 */
  365. { MOD_CLK_ID(809), R8A7795_CLK_S2D1 }, /* VIN2 */
  366. { MOD_CLK_ID(810), R8A7795_CLK_S2D1 }, /* VIN1 */
  367. { MOD_CLK_ID(811), R8A7795_CLK_S2D1 }, /* VIN0 */
  368. { MOD_CLK_ID(812), R8A7795_CLK_S3D2 }, /* EAVB-IF */
  369. { MOD_CLK_ID(820), R8A7795_CLK_S2D1 }, /* IMR3 */
  370. { MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */
  371. { MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */
  372. { MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */
  373. { MOD_CLK_ID(905), R8A7795_CLK_CP }, /* GPIO7 */
  374. { MOD_CLK_ID(906), R8A7795_CLK_CP }, /* GPIO6 */
  375. { MOD_CLK_ID(907), R8A7795_CLK_CP }, /* GPIO5 */
  376. { MOD_CLK_ID(908), R8A7795_CLK_CP }, /* GPIO4 */
  377. { MOD_CLK_ID(909), R8A7795_CLK_CP }, /* GPIO3 */
  378. { MOD_CLK_ID(910), R8A7795_CLK_CP }, /* GPIO2 */
  379. { MOD_CLK_ID(911), R8A7795_CLK_CP }, /* GPIO1 */
  380. { MOD_CLK_ID(912), R8A7795_CLK_CP }, /* GPIO0 */
  381. { MOD_CLK_ID(918), R8A7795_CLK_S3D2 }, /* I2C6 */
  382. { MOD_CLK_ID(919), R8A7795_CLK_S3D2 }, /* I2C5 */
  383. { MOD_CLK_ID(927), R8A7795_CLK_S3D2 }, /* I2C4 */
  384. { MOD_CLK_ID(928), R8A7795_CLK_S3D2 }, /* I2C3 */
  385. };
  386. /*
  387. * Fixups for R-Car H3 ES2.x
  388. */
  389. static const unsigned int r8a7795es2_mod_nullify[] __initconst = {
  390. MOD_CLK_ID(117), /* FDP1-2 */
  391. MOD_CLK_ID(327), /* USB3-IF1 */
  392. MOD_CLK_ID(600), /* FCPVD3 */
  393. MOD_CLK_ID(609), /* FCPVI2 */
  394. MOD_CLK_ID(613), /* FCPF2 */
  395. MOD_CLK_ID(616), /* FCPCI1 */
  396. MOD_CLK_ID(617), /* FCPCI0 */
  397. MOD_CLK_ID(620), /* VSPD3 */
  398. MOD_CLK_ID(629), /* VSPI2 */
  399. MOD_CLK_ID(713), /* CSI21 */
  400. };
  401. static int __init r8a7795_cpg_mssr_init(struct device *dev)
  402. {
  403. const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
  404. u32 cpg_mode;
  405. int error;
  406. error = rcar_rst_read_mode_pins(&cpg_mode);
  407. if (error)
  408. return error;
  409. cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
  410. if (!cpg_pll_config->extal_div) {
  411. dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
  412. return -EINVAL;
  413. }
  414. if (soc_device_match(r8a7795es1)) {
  415. cpg_core_nullify_range(r8a7795_core_clks,
  416. ARRAY_SIZE(r8a7795_core_clks),
  417. R8A7795_CLK_S0D2, R8A7795_CLK_S0D12);
  418. mssr_mod_nullify(r8a7795_mod_clks,
  419. ARRAY_SIZE(r8a7795_mod_clks),
  420. r8a7795es1_mod_nullify,
  421. ARRAY_SIZE(r8a7795es1_mod_nullify));
  422. mssr_mod_reparent(r8a7795_mod_clks,
  423. ARRAY_SIZE(r8a7795_mod_clks),
  424. r8a7795es1_mod_reparent,
  425. ARRAY_SIZE(r8a7795es1_mod_reparent));
  426. } else {
  427. mssr_mod_nullify(r8a7795_mod_clks,
  428. ARRAY_SIZE(r8a7795_mod_clks),
  429. r8a7795es2_mod_nullify,
  430. ARRAY_SIZE(r8a7795es2_mod_nullify));
  431. }
  432. return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
  433. }
  434. const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
  435. /* Core Clocks */
  436. .core_clks = r8a7795_core_clks,
  437. .num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
  438. .last_dt_core_clk = LAST_DT_CORE_CLK,
  439. .num_total_core_clks = MOD_CLK_BASE,
  440. /* Module Clocks */
  441. .mod_clks = r8a7795_mod_clks,
  442. .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
  443. .num_hw_mod_clks = 12 * 32,
  444. /* Critical Module Clocks */
  445. .crit_mod_clks = r8a7795_crit_mod_clks,
  446. .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
  447. /* Callbacks */
  448. .init = r8a7795_cpg_mssr_init,
  449. .cpg_clk_register = rcar_gen3_cpg_clk_register,
  450. };