clk-sh73a0.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * sh73a0 Core CPG Clocks
  4. *
  5. * Copyright (C) 2014 Ulrich Hecht
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/clk/renesas.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include <linux/slab.h>
  15. #include <linux/spinlock.h>
  16. struct sh73a0_cpg {
  17. struct clk_onecell_data data;
  18. spinlock_t lock;
  19. void __iomem *reg;
  20. };
  21. #define CPG_FRQCRA 0x00
  22. #define CPG_FRQCRB 0x04
  23. #define CPG_SD0CKCR 0x74
  24. #define CPG_SD1CKCR 0x78
  25. #define CPG_SD2CKCR 0x7c
  26. #define CPG_PLLECR 0xd0
  27. #define CPG_PLL0CR 0xd8
  28. #define CPG_PLL1CR 0x28
  29. #define CPG_PLL2CR 0x2c
  30. #define CPG_PLL3CR 0xdc
  31. #define CPG_CKSCR 0xc0
  32. #define CPG_DSI0PHYCR 0x6c
  33. #define CPG_DSI1PHYCR 0x70
  34. #define CLK_ENABLE_ON_INIT BIT(0)
  35. struct div4_clk {
  36. const char *name;
  37. const char *parent;
  38. unsigned int reg;
  39. unsigned int shift;
  40. };
  41. static const struct div4_clk div4_clks[] = {
  42. { "zg", "pll0", CPG_FRQCRA, 16 },
  43. { "m3", "pll1", CPG_FRQCRA, 12 },
  44. { "b", "pll1", CPG_FRQCRA, 8 },
  45. { "m1", "pll1", CPG_FRQCRA, 4 },
  46. { "m2", "pll1", CPG_FRQCRA, 0 },
  47. { "zx", "pll1", CPG_FRQCRB, 12 },
  48. { "hp", "pll1", CPG_FRQCRB, 4 },
  49. { NULL, NULL, 0, 0 },
  50. };
  51. static const struct clk_div_table div4_div_table[] = {
  52. { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
  53. { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
  54. { 12, 7 }, { 0, 0 }
  55. };
  56. static const struct clk_div_table z_div_table[] = {
  57. /* ZSEL == 0 */
  58. { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 },
  59. { 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 },
  60. { 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 },
  61. /* ZSEL == 1 */
  62. { 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 },
  63. { 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 }
  64. };
  65. static struct clk * __init
  66. sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
  67. const char *name)
  68. {
  69. const struct clk_div_table *table = NULL;
  70. unsigned int shift, reg, width;
  71. const char *parent_name = NULL;
  72. unsigned int mult = 1;
  73. unsigned int div = 1;
  74. if (!strcmp(name, "main")) {
  75. /* extal1, extal1_div2, extal2, extal2_div2 */
  76. u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
  77. parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
  78. div = (parent_idx & 1) + 1;
  79. } else if (!strncmp(name, "pll", 3)) {
  80. void __iomem *enable_reg = cpg->reg;
  81. u32 enable_bit = name[3] - '0';
  82. parent_name = "main";
  83. switch (enable_bit) {
  84. case 0:
  85. enable_reg += CPG_PLL0CR;
  86. break;
  87. case 1:
  88. enable_reg += CPG_PLL1CR;
  89. break;
  90. case 2:
  91. enable_reg += CPG_PLL2CR;
  92. break;
  93. case 3:
  94. enable_reg += CPG_PLL3CR;
  95. break;
  96. default:
  97. return ERR_PTR(-EINVAL);
  98. }
  99. if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
  100. mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;
  101. /* handle CFG bit for PLL1 and PLL2 */
  102. if (enable_bit == 1 || enable_bit == 2)
  103. if (readl(enable_reg) & BIT(20))
  104. mult *= 2;
  105. }
  106. } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
  107. u32 phy_no = name[3] - '0';
  108. void __iomem *dsi_reg = cpg->reg +
  109. (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);
  110. parent_name = phy_no ? "dsi1pck" : "dsi0pck";
  111. mult = __raw_readl(dsi_reg);
  112. if (!(mult & 0x8000))
  113. mult = 1;
  114. else
  115. mult = (mult & 0x3f) + 1;
  116. } else if (!strcmp(name, "z")) {
  117. parent_name = "pll0";
  118. table = z_div_table;
  119. reg = CPG_FRQCRB;
  120. shift = 24;
  121. width = 5;
  122. } else {
  123. const struct div4_clk *c;
  124. for (c = div4_clks; c->name; c++) {
  125. if (!strcmp(name, c->name)) {
  126. parent_name = c->parent;
  127. table = div4_div_table;
  128. reg = c->reg;
  129. shift = c->shift;
  130. width = 4;
  131. break;
  132. }
  133. }
  134. if (!c->name)
  135. return ERR_PTR(-EINVAL);
  136. }
  137. if (!table) {
  138. return clk_register_fixed_factor(NULL, name, parent_name, 0,
  139. mult, div);
  140. } else {
  141. return clk_register_divider_table(NULL, name, parent_name, 0,
  142. cpg->reg + reg, shift, width, 0,
  143. table, &cpg->lock);
  144. }
  145. }
  146. static void __init sh73a0_cpg_clocks_init(struct device_node *np)
  147. {
  148. struct sh73a0_cpg *cpg;
  149. struct clk **clks;
  150. unsigned int i;
  151. int num_clks;
  152. num_clks = of_property_count_strings(np, "clock-output-names");
  153. if (num_clks < 0) {
  154. pr_err("%s: failed to count clocks\n", __func__);
  155. return;
  156. }
  157. cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
  158. clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
  159. if (cpg == NULL || clks == NULL) {
  160. /* We're leaking memory on purpose, there's no point in cleaning
  161. * up as the system won't boot anyway.
  162. */
  163. return;
  164. }
  165. spin_lock_init(&cpg->lock);
  166. cpg->data.clks = clks;
  167. cpg->data.clk_num = num_clks;
  168. cpg->reg = of_iomap(np, 0);
  169. if (WARN_ON(cpg->reg == NULL))
  170. return;
  171. /* Set SDHI clocks to a known state */
  172. writel(0x108, cpg->reg + CPG_SD0CKCR);
  173. writel(0x108, cpg->reg + CPG_SD1CKCR);
  174. writel(0x108, cpg->reg + CPG_SD2CKCR);
  175. for (i = 0; i < num_clks; ++i) {
  176. const char *name;
  177. struct clk *clk;
  178. of_property_read_string_index(np, "clock-output-names", i,
  179. &name);
  180. clk = sh73a0_cpg_register_clock(np, cpg, name);
  181. if (IS_ERR(clk))
  182. pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
  183. __func__, np, name, PTR_ERR(clk));
  184. else
  185. cpg->data.clks[i] = clk;
  186. }
  187. of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
  188. }
  189. CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks",
  190. sh73a0_cpg_clocks_init);