clk-rz.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * RZ/A1 Core CPG Clocks
  4. *
  5. * Copyright (C) 2013 Ideas On Board SPRL
  6. * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
  7. */
  8. #include <linux/clk-provider.h>
  9. #include <linux/clk/renesas.h>
  10. #include <linux/init.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/slab.h>
  16. struct rz_cpg {
  17. struct clk_onecell_data data;
  18. void __iomem *reg;
  19. };
  20. #define CPG_FRQCR 0x10
  21. #define CPG_FRQCR2 0x14
  22. #define PPR0 0xFCFE3200
  23. #define PIBC0 0xFCFE7000
  24. #define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */
  25. /* -----------------------------------------------------------------------------
  26. * Initialization
  27. */
  28. static u16 __init rz_cpg_read_mode_pins(void)
  29. {
  30. void __iomem *ppr0, *pibc0;
  31. u16 modes;
  32. ppr0 = ioremap(PPR0, 2);
  33. pibc0 = ioremap(PIBC0, 2);
  34. BUG_ON(!ppr0 || !pibc0);
  35. iowrite16(4, pibc0); /* enable input buffer */
  36. modes = ioread16(ppr0);
  37. iounmap(ppr0);
  38. iounmap(pibc0);
  39. return modes;
  40. }
  41. static struct clk * __init
  42. rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
  43. {
  44. u32 val;
  45. unsigned mult;
  46. static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
  47. if (strcmp(name, "pll") == 0) {
  48. unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
  49. const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
  50. mult = cpg_mode ? (32 / 4) : 30;
  51. return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
  52. }
  53. /* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
  54. if (!cpg->reg)
  55. return ERR_PTR(-ENXIO);
  56. /* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
  57. * and the constraint that always g <= i. To get the rz platform started,
  58. * let them run at fixed current speed and implement the details later.
  59. */
  60. if (strcmp(name, "i") == 0)
  61. val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
  62. else if (strcmp(name, "g") == 0)
  63. val = readl(cpg->reg + CPG_FRQCR2) & 3;
  64. else
  65. return ERR_PTR(-EINVAL);
  66. mult = frqcr_tab[val];
  67. return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
  68. }
  69. static void __init rz_cpg_clocks_init(struct device_node *np)
  70. {
  71. struct rz_cpg *cpg;
  72. struct clk **clks;
  73. unsigned i;
  74. int num_clks;
  75. num_clks = of_property_count_strings(np, "clock-output-names");
  76. if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
  77. return;
  78. cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
  79. clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
  80. BUG_ON(!cpg || !clks);
  81. cpg->data.clks = clks;
  82. cpg->data.clk_num = num_clks;
  83. cpg->reg = of_iomap(np, 0);
  84. for (i = 0; i < num_clks; ++i) {
  85. const char *name;
  86. struct clk *clk;
  87. of_property_read_string_index(np, "clock-output-names", i, &name);
  88. clk = rz_cpg_register_clock(np, cpg, name);
  89. if (IS_ERR(clk))
  90. pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
  91. __func__, np, name, PTR_ERR(clk));
  92. else
  93. cpg->data.clks[i] = clk;
  94. }
  95. of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
  96. cpg_mstp_add_clk_domain(np);
  97. }
  98. CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);