clk-r8a7779.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a7779 Core CPG Clocks
  4. *
  5. * Copyright (C) 2013, 2014 Horms Solutions Ltd.
  6. *
  7. * Contact: Simon Horman <horms@verge.net.au>
  8. */
  9. #include <linux/clk-provider.h>
  10. #include <linux/clk/renesas.h>
  11. #include <linux/init.h>
  12. #include <linux/kernel.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/slab.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/soc/renesas/rcar-rst.h>
  18. #include <dt-bindings/clock/r8a7779-clock.h>
  19. #define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1)
  20. struct r8a7779_cpg {
  21. struct clk_onecell_data data;
  22. spinlock_t lock;
  23. void __iomem *reg;
  24. };
  25. /* -----------------------------------------------------------------------------
  26. * CPG Clock Data
  27. */
  28. /*
  29. * MD1 = 1 MD1 = 0
  30. * (PLLA = 1500) (PLLA = 1600)
  31. * (MHz) (MHz)
  32. *------------------------------------------------+--------------------
  33. * clkz 1000 (2/3) 800 (1/2)
  34. * clkzs 250 (1/6) 200 (1/8)
  35. * clki 750 (1/2) 800 (1/2)
  36. * clks 250 (1/6) 200 (1/8)
  37. * clks1 125 (1/12) 100 (1/16)
  38. * clks3 187.5 (1/8) 200 (1/8)
  39. * clks4 93.7 (1/16) 100 (1/16)
  40. * clkp 62.5 (1/24) 50 (1/32)
  41. * clkg 62.5 (1/24) 66.6 (1/24)
  42. * clkb, CLKOUT
  43. * (MD2 = 0) 62.5 (1/24) 66.6 (1/24)
  44. * (MD2 = 1) 41.6 (1/36) 50 (1/32)
  45. */
  46. #define CPG_CLK_CONFIG_INDEX(md) (((md) & (BIT(2)|BIT(1))) >> 1)
  47. struct cpg_clk_config {
  48. unsigned int z_mult;
  49. unsigned int z_div;
  50. unsigned int zs_and_s_div;
  51. unsigned int s1_div;
  52. unsigned int p_div;
  53. unsigned int b_and_out_div;
  54. };
  55. static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
  56. { 1, 2, 8, 16, 32, 24 },
  57. { 2, 3, 6, 12, 24, 24 },
  58. { 1, 2, 8, 16, 32, 32 },
  59. { 2, 3, 6, 12, 24, 36 },
  60. };
  61. /*
  62. * MD PLLA Ratio
  63. * 12 11
  64. *------------------------
  65. * 0 0 x42
  66. * 0 1 x48
  67. * 1 0 x56
  68. * 1 1 x64
  69. */
  70. #define CPG_PLLA_MULT_INDEX(md) (((md) & (BIT(12)|BIT(11))) >> 11)
  71. static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
  72. /* -----------------------------------------------------------------------------
  73. * Initialization
  74. */
  75. static struct clk * __init
  76. r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
  77. const struct cpg_clk_config *config,
  78. unsigned int plla_mult, const char *name)
  79. {
  80. const char *parent_name = "plla";
  81. unsigned int mult = 1;
  82. unsigned int div = 1;
  83. if (!strcmp(name, "plla")) {
  84. parent_name = of_clk_get_parent_name(np, 0);
  85. mult = plla_mult;
  86. } else if (!strcmp(name, "z")) {
  87. div = config->z_div;
  88. mult = config->z_mult;
  89. } else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
  90. div = config->zs_and_s_div;
  91. } else if (!strcmp(name, "s1")) {
  92. div = config->s1_div;
  93. } else if (!strcmp(name, "p")) {
  94. div = config->p_div;
  95. } else if (!strcmp(name, "b") || !strcmp(name, "out")) {
  96. div = config->b_and_out_div;
  97. } else {
  98. return ERR_PTR(-EINVAL);
  99. }
  100. return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
  101. }
  102. static void __init r8a7779_cpg_clocks_init(struct device_node *np)
  103. {
  104. const struct cpg_clk_config *config;
  105. struct r8a7779_cpg *cpg;
  106. struct clk **clks;
  107. unsigned int i, plla_mult;
  108. int num_clks;
  109. u32 mode;
  110. if (rcar_rst_read_mode_pins(&mode))
  111. return;
  112. num_clks = of_property_count_strings(np, "clock-output-names");
  113. if (num_clks < 0) {
  114. pr_err("%s: failed to count clocks\n", __func__);
  115. return;
  116. }
  117. cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
  118. clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL);
  119. if (cpg == NULL || clks == NULL) {
  120. /* We're leaking memory on purpose, there's no point in cleaning
  121. * up as the system won't boot anyway.
  122. */
  123. return;
  124. }
  125. spin_lock_init(&cpg->lock);
  126. cpg->data.clks = clks;
  127. cpg->data.clk_num = num_clks;
  128. config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)];
  129. plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)];
  130. for (i = 0; i < num_clks; ++i) {
  131. const char *name;
  132. struct clk *clk;
  133. of_property_read_string_index(np, "clock-output-names", i,
  134. &name);
  135. clk = r8a7779_cpg_register_clock(np, cpg, config,
  136. plla_mult, name);
  137. if (IS_ERR(clk))
  138. pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
  139. __func__, np, name, PTR_ERR(clk));
  140. else
  141. cpg->data.clks[i] = clk;
  142. }
  143. of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
  144. cpg_mstp_add_clk_domain(np);
  145. }
  146. CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
  147. r8a7779_cpg_clocks_init);