clk-r8a7740.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a7740 Core CPG Clocks
  4. *
  5. * Copyright (C) 2014 Ulrich Hecht
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/clk/renesas.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/slab.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/spinlock.h>
  16. struct r8a7740_cpg {
  17. struct clk_onecell_data data;
  18. spinlock_t lock;
  19. void __iomem *reg;
  20. };
  21. #define CPG_FRQCRA 0x00
  22. #define CPG_FRQCRB 0x04
  23. #define CPG_PLLC2CR 0x2c
  24. #define CPG_USBCKCR 0x8c
  25. #define CPG_FRQCRC 0xe0
  26. #define CLK_ENABLE_ON_INIT BIT(0)
  27. struct div4_clk {
  28. const char *name;
  29. unsigned int reg;
  30. unsigned int shift;
  31. int flags;
  32. };
  33. static struct div4_clk div4_clks[] = {
  34. { "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
  35. { "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
  36. { "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT },
  37. { "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT },
  38. { "hp", CPG_FRQCRB, 4, 0 },
  39. { "hpp", CPG_FRQCRC, 20, 0 },
  40. { "usbp", CPG_FRQCRC, 16, 0 },
  41. { "s", CPG_FRQCRC, 12, 0 },
  42. { "zb", CPG_FRQCRC, 8, 0 },
  43. { "m3", CPG_FRQCRC, 4, 0 },
  44. { "cp", CPG_FRQCRC, 0, 0 },
  45. { NULL, 0, 0, 0 },
  46. };
  47. static const struct clk_div_table div4_div_table[] = {
  48. { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
  49. { 6, 16 }, { 7, 18 }, { 8, 24 }, { 9, 32 }, { 10, 36 }, { 11, 48 },
  50. { 13, 72 }, { 14, 96 }, { 0, 0 }
  51. };
  52. static u32 cpg_mode __initdata;
  53. static struct clk * __init
  54. r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
  55. const char *name)
  56. {
  57. const struct clk_div_table *table = NULL;
  58. const char *parent_name;
  59. unsigned int shift, reg;
  60. unsigned int mult = 1;
  61. unsigned int div = 1;
  62. if (!strcmp(name, "r")) {
  63. switch (cpg_mode & (BIT(2) | BIT(1))) {
  64. case BIT(1) | BIT(2):
  65. /* extal1 */
  66. parent_name = of_clk_get_parent_name(np, 0);
  67. div = 2048;
  68. break;
  69. case BIT(2):
  70. /* extal1 */
  71. parent_name = of_clk_get_parent_name(np, 0);
  72. div = 1024;
  73. break;
  74. default:
  75. /* extalr */
  76. parent_name = of_clk_get_parent_name(np, 2);
  77. break;
  78. }
  79. } else if (!strcmp(name, "system")) {
  80. parent_name = of_clk_get_parent_name(np, 0);
  81. if (cpg_mode & BIT(1))
  82. div = 2;
  83. } else if (!strcmp(name, "pllc0")) {
  84. /* PLLC0/1 are configurable multiplier clocks. Register them as
  85. * fixed factor clocks for now as there's no generic multiplier
  86. * clock implementation and we currently have no need to change
  87. * the multiplier value.
  88. */
  89. u32 value = readl(cpg->reg + CPG_FRQCRC);
  90. parent_name = "system";
  91. mult = ((value >> 24) & 0x7f) + 1;
  92. } else if (!strcmp(name, "pllc1")) {
  93. u32 value = readl(cpg->reg + CPG_FRQCRA);
  94. parent_name = "system";
  95. mult = ((value >> 24) & 0x7f) + 1;
  96. div = 2;
  97. } else if (!strcmp(name, "pllc2")) {
  98. u32 value = readl(cpg->reg + CPG_PLLC2CR);
  99. parent_name = "system";
  100. mult = ((value >> 24) & 0x3f) + 1;
  101. } else if (!strcmp(name, "usb24s")) {
  102. u32 value = readl(cpg->reg + CPG_USBCKCR);
  103. if (value & BIT(7))
  104. /* extal2 */
  105. parent_name = of_clk_get_parent_name(np, 1);
  106. else
  107. parent_name = "system";
  108. if (!(value & BIT(6)))
  109. div = 2;
  110. } else {
  111. struct div4_clk *c;
  112. for (c = div4_clks; c->name; c++) {
  113. if (!strcmp(name, c->name)) {
  114. parent_name = "pllc1";
  115. table = div4_div_table;
  116. reg = c->reg;
  117. shift = c->shift;
  118. break;
  119. }
  120. }
  121. if (!c->name)
  122. return ERR_PTR(-EINVAL);
  123. }
  124. if (!table) {
  125. return clk_register_fixed_factor(NULL, name, parent_name, 0,
  126. mult, div);
  127. } else {
  128. return clk_register_divider_table(NULL, name, parent_name, 0,
  129. cpg->reg + reg, shift, 4, 0,
  130. table, &cpg->lock);
  131. }
  132. }
  133. static void __init r8a7740_cpg_clocks_init(struct device_node *np)
  134. {
  135. struct r8a7740_cpg *cpg;
  136. struct clk **clks;
  137. unsigned int i;
  138. int num_clks;
  139. if (of_property_read_u32(np, "renesas,mode", &cpg_mode))
  140. pr_warn("%s: missing renesas,mode property\n", __func__);
  141. num_clks = of_property_count_strings(np, "clock-output-names");
  142. if (num_clks < 0) {
  143. pr_err("%s: failed to count clocks\n", __func__);
  144. return;
  145. }
  146. cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
  147. clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
  148. if (cpg == NULL || clks == NULL) {
  149. /* We're leaking memory on purpose, there's no point in cleaning
  150. * up as the system won't boot anyway.
  151. */
  152. return;
  153. }
  154. spin_lock_init(&cpg->lock);
  155. cpg->data.clks = clks;
  156. cpg->data.clk_num = num_clks;
  157. cpg->reg = of_iomap(np, 0);
  158. if (WARN_ON(cpg->reg == NULL))
  159. return;
  160. for (i = 0; i < num_clks; ++i) {
  161. const char *name;
  162. struct clk *clk;
  163. of_property_read_string_index(np, "clock-output-names", i,
  164. &name);
  165. clk = r8a7740_cpg_register_clock(np, cpg, name);
  166. if (IS_ERR(clk))
  167. pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
  168. __func__, np, name, PTR_ERR(clk));
  169. else
  170. cpg->data.clks[i] = clk;
  171. }
  172. of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
  173. }
  174. CLK_OF_DECLARE(r8a7740_cpg_clks, "renesas,r8a7740-cpg-clocks",
  175. r8a7740_cpg_clocks_init);