clk-r8a73a4.c 5.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a73a4 Core CPG Clocks
  4. *
  5. * Copyright (C) 2014 Ulrich Hecht
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/clk/renesas.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/slab.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/spinlock.h>
  16. struct r8a73a4_cpg {
  17. struct clk_onecell_data data;
  18. spinlock_t lock;
  19. void __iomem *reg;
  20. };
  21. #define CPG_CKSCR 0xc0
  22. #define CPG_FRQCRA 0x00
  23. #define CPG_FRQCRB 0x04
  24. #define CPG_FRQCRC 0xe0
  25. #define CPG_PLL0CR 0xd8
  26. #define CPG_PLL1CR 0x28
  27. #define CPG_PLL2CR 0x2c
  28. #define CPG_PLL2HCR 0xe4
  29. #define CPG_PLL2SCR 0xf4
  30. #define CLK_ENABLE_ON_INIT BIT(0)
  31. struct div4_clk {
  32. const char *name;
  33. unsigned int reg;
  34. unsigned int shift;
  35. };
  36. static struct div4_clk div4_clks[] = {
  37. { "i", CPG_FRQCRA, 20 },
  38. { "m3", CPG_FRQCRA, 12 },
  39. { "b", CPG_FRQCRA, 8 },
  40. { "m1", CPG_FRQCRA, 4 },
  41. { "m2", CPG_FRQCRA, 0 },
  42. { "zx", CPG_FRQCRB, 12 },
  43. { "zs", CPG_FRQCRB, 8 },
  44. { "hp", CPG_FRQCRB, 4 },
  45. { NULL, 0, 0 },
  46. };
  47. static const struct clk_div_table div4_div_table[] = {
  48. { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
  49. { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
  50. { 12, 10 }, { 0, 0 }
  51. };
  52. static struct clk * __init
  53. r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
  54. const char *name)
  55. {
  56. const struct clk_div_table *table = NULL;
  57. const char *parent_name;
  58. unsigned int shift, reg;
  59. unsigned int mult = 1;
  60. unsigned int div = 1;
  61. if (!strcmp(name, "main")) {
  62. u32 ckscr = readl(cpg->reg + CPG_CKSCR);
  63. switch ((ckscr >> 28) & 3) {
  64. case 0: /* extal1 */
  65. parent_name = of_clk_get_parent_name(np, 0);
  66. break;
  67. case 1: /* extal1 / 2 */
  68. parent_name = of_clk_get_parent_name(np, 0);
  69. div = 2;
  70. break;
  71. case 2: /* extal2 */
  72. parent_name = of_clk_get_parent_name(np, 1);
  73. break;
  74. case 3: /* extal2 / 2 */
  75. parent_name = of_clk_get_parent_name(np, 1);
  76. div = 2;
  77. break;
  78. }
  79. } else if (!strcmp(name, "pll0")) {
  80. /* PLL0/1 are configurable multiplier clocks. Register them as
  81. * fixed factor clocks for now as there's no generic multiplier
  82. * clock implementation and we currently have no need to change
  83. * the multiplier value.
  84. */
  85. u32 value = readl(cpg->reg + CPG_PLL0CR);
  86. parent_name = "main";
  87. mult = ((value >> 24) & 0x7f) + 1;
  88. if (value & BIT(20))
  89. div = 2;
  90. } else if (!strcmp(name, "pll1")) {
  91. u32 value = readl(cpg->reg + CPG_PLL1CR);
  92. parent_name = "main";
  93. /* XXX: enable bit? */
  94. mult = ((value >> 24) & 0x7f) + 1;
  95. if (value & BIT(7))
  96. div = 2;
  97. } else if (!strncmp(name, "pll2", 4)) {
  98. u32 value, cr;
  99. switch (name[4]) {
  100. case 0:
  101. cr = CPG_PLL2CR;
  102. break;
  103. case 's':
  104. cr = CPG_PLL2SCR;
  105. break;
  106. case 'h':
  107. cr = CPG_PLL2HCR;
  108. break;
  109. default:
  110. return ERR_PTR(-EINVAL);
  111. }
  112. value = readl(cpg->reg + cr);
  113. switch ((value >> 5) & 7) {
  114. case 0:
  115. parent_name = "main";
  116. div = 2;
  117. break;
  118. case 1:
  119. parent_name = "extal2";
  120. div = 2;
  121. break;
  122. case 3:
  123. parent_name = "extal2";
  124. div = 4;
  125. break;
  126. case 4:
  127. parent_name = "main";
  128. break;
  129. case 5:
  130. parent_name = "extal2";
  131. break;
  132. default:
  133. pr_warn("%s: unexpected parent of %s\n", __func__,
  134. name);
  135. return ERR_PTR(-EINVAL);
  136. }
  137. /* XXX: enable bit? */
  138. mult = ((value >> 24) & 0x7f) + 1;
  139. } else if (!strcmp(name, "z") || !strcmp(name, "z2")) {
  140. u32 shift = 8;
  141. parent_name = "pll0";
  142. if (name[1] == '2') {
  143. div = 2;
  144. shift = 0;
  145. }
  146. div *= 32;
  147. mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
  148. } else {
  149. struct div4_clk *c;
  150. for (c = div4_clks; c->name; c++) {
  151. if (!strcmp(name, c->name))
  152. break;
  153. }
  154. if (!c->name)
  155. return ERR_PTR(-EINVAL);
  156. parent_name = "pll1";
  157. table = div4_div_table;
  158. reg = c->reg;
  159. shift = c->shift;
  160. }
  161. if (!table) {
  162. return clk_register_fixed_factor(NULL, name, parent_name, 0,
  163. mult, div);
  164. } else {
  165. return clk_register_divider_table(NULL, name, parent_name, 0,
  166. cpg->reg + reg, shift, 4, 0,
  167. table, &cpg->lock);
  168. }
  169. }
  170. static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
  171. {
  172. struct r8a73a4_cpg *cpg;
  173. struct clk **clks;
  174. unsigned int i;
  175. int num_clks;
  176. num_clks = of_property_count_strings(np, "clock-output-names");
  177. if (num_clks < 0) {
  178. pr_err("%s: failed to count clocks\n", __func__);
  179. return;
  180. }
  181. cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
  182. clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
  183. if (cpg == NULL || clks == NULL) {
  184. /* We're leaking memory on purpose, there's no point in cleaning
  185. * up as the system won't boot anyway.
  186. */
  187. return;
  188. }
  189. spin_lock_init(&cpg->lock);
  190. cpg->data.clks = clks;
  191. cpg->data.clk_num = num_clks;
  192. cpg->reg = of_iomap(np, 0);
  193. if (WARN_ON(cpg->reg == NULL))
  194. return;
  195. for (i = 0; i < num_clks; ++i) {
  196. const char *name;
  197. struct clk *clk;
  198. of_property_read_string_index(np, "clock-output-names", i,
  199. &name);
  200. clk = r8a73a4_cpg_register_clock(np, cpg, name);
  201. if (IS_ERR(clk))
  202. pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
  203. __func__, np, name, PTR_ERR(clk));
  204. else
  205. cpg->data.clks[i] = clk;
  206. }
  207. of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
  208. }
  209. CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",
  210. r8a73a4_cpg_clocks_init);