clk-mstp.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R-Car MSTP clocks
  4. *
  5. * Copyright (C) 2013 Ideas On Board SPRL
  6. * Copyright (C) 2015 Glider bvba
  7. *
  8. * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/clkdev.h>
  13. #include <linux/clk/renesas.h>
  14. #include <linux/device.h>
  15. #include <linux/io.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include <linux/pm_clock.h>
  19. #include <linux/pm_domain.h>
  20. #include <linux/spinlock.h>
  21. /*
  22. * MSTP clocks. We can't use standard gate clocks as we need to poll on the
  23. * status register when enabling the clock.
  24. */
  25. #define MSTP_MAX_CLOCKS 32
  26. /**
  27. * struct mstp_clock_group - MSTP gating clocks group
  28. *
  29. * @data: clock specifier translation for clocks in this group
  30. * @smstpcr: module stop control register
  31. * @mstpsr: module stop status register (optional)
  32. * @lock: protects writes to SMSTPCR
  33. * @width_8bit: registers are 8-bit, not 32-bit
  34. * @clks: clocks in this group
  35. */
  36. struct mstp_clock_group {
  37. struct clk_onecell_data data;
  38. void __iomem *smstpcr;
  39. void __iomem *mstpsr;
  40. spinlock_t lock;
  41. bool width_8bit;
  42. struct clk *clks[];
  43. };
  44. /**
  45. * struct mstp_clock - MSTP gating clock
  46. * @hw: handle between common and hardware-specific interfaces
  47. * @bit_index: control bit index
  48. * @group: MSTP clocks group
  49. */
  50. struct mstp_clock {
  51. struct clk_hw hw;
  52. u32 bit_index;
  53. struct mstp_clock_group *group;
  54. };
  55. #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
  56. static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
  57. u32 __iomem *reg)
  58. {
  59. return group->width_8bit ? readb(reg) : readl(reg);
  60. }
  61. static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
  62. u32 __iomem *reg)
  63. {
  64. group->width_8bit ? writeb(val, reg) : writel(val, reg);
  65. }
  66. static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
  67. {
  68. struct mstp_clock *clock = to_mstp_clock(hw);
  69. struct mstp_clock_group *group = clock->group;
  70. u32 bitmask = BIT(clock->bit_index);
  71. unsigned long flags;
  72. unsigned int i;
  73. u32 value;
  74. spin_lock_irqsave(&group->lock, flags);
  75. value = cpg_mstp_read(group, group->smstpcr);
  76. if (enable)
  77. value &= ~bitmask;
  78. else
  79. value |= bitmask;
  80. cpg_mstp_write(group, value, group->smstpcr);
  81. if (!group->mstpsr) {
  82. /* dummy read to ensure write has completed */
  83. cpg_mstp_read(group, group->smstpcr);
  84. barrier_data(group->smstpcr);
  85. }
  86. spin_unlock_irqrestore(&group->lock, flags);
  87. if (!enable || !group->mstpsr)
  88. return 0;
  89. for (i = 1000; i > 0; --i) {
  90. if (!(cpg_mstp_read(group, group->mstpsr) & bitmask))
  91. break;
  92. cpu_relax();
  93. }
  94. if (!i) {
  95. pr_err("%s: failed to enable %p[%d]\n", __func__,
  96. group->smstpcr, clock->bit_index);
  97. return -ETIMEDOUT;
  98. }
  99. return 0;
  100. }
  101. static int cpg_mstp_clock_enable(struct clk_hw *hw)
  102. {
  103. return cpg_mstp_clock_endisable(hw, true);
  104. }
  105. static void cpg_mstp_clock_disable(struct clk_hw *hw)
  106. {
  107. cpg_mstp_clock_endisable(hw, false);
  108. }
  109. static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
  110. {
  111. struct mstp_clock *clock = to_mstp_clock(hw);
  112. struct mstp_clock_group *group = clock->group;
  113. u32 value;
  114. if (group->mstpsr)
  115. value = cpg_mstp_read(group, group->mstpsr);
  116. else
  117. value = cpg_mstp_read(group, group->smstpcr);
  118. return !(value & BIT(clock->bit_index));
  119. }
  120. static const struct clk_ops cpg_mstp_clock_ops = {
  121. .enable = cpg_mstp_clock_enable,
  122. .disable = cpg_mstp_clock_disable,
  123. .is_enabled = cpg_mstp_clock_is_enabled,
  124. };
  125. static struct clk * __init cpg_mstp_clock_register(const char *name,
  126. const char *parent_name, unsigned int index,
  127. struct mstp_clock_group *group)
  128. {
  129. struct clk_init_data init;
  130. struct mstp_clock *clock;
  131. struct clk *clk;
  132. clock = kzalloc(sizeof(*clock), GFP_KERNEL);
  133. if (!clock)
  134. return ERR_PTR(-ENOMEM);
  135. init.name = name;
  136. init.ops = &cpg_mstp_clock_ops;
  137. init.flags = CLK_SET_RATE_PARENT;
  138. /* INTC-SYS is the module clock of the GIC, and must not be disabled */
  139. if (!strcmp(name, "intc-sys")) {
  140. pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
  141. init.flags |= CLK_IS_CRITICAL;
  142. }
  143. init.parent_names = &parent_name;
  144. init.num_parents = 1;
  145. clock->bit_index = index;
  146. clock->group = group;
  147. clock->hw.init = &init;
  148. clk = clk_register(NULL, &clock->hw);
  149. if (IS_ERR(clk))
  150. kfree(clock);
  151. return clk;
  152. }
  153. static void __init cpg_mstp_clocks_init(struct device_node *np)
  154. {
  155. struct mstp_clock_group *group;
  156. const char *idxname;
  157. struct clk **clks;
  158. unsigned int i;
  159. group = kzalloc(struct_size(group, clks, MSTP_MAX_CLOCKS), GFP_KERNEL);
  160. if (!group)
  161. return;
  162. clks = group->clks;
  163. spin_lock_init(&group->lock);
  164. group->data.clks = clks;
  165. group->smstpcr = of_iomap(np, 0);
  166. group->mstpsr = of_iomap(np, 1);
  167. if (group->smstpcr == NULL) {
  168. pr_err("%s: failed to remap SMSTPCR\n", __func__);
  169. kfree(group);
  170. return;
  171. }
  172. if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
  173. group->width_8bit = true;
  174. for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
  175. clks[i] = ERR_PTR(-ENOENT);
  176. if (of_find_property(np, "clock-indices", &i))
  177. idxname = "clock-indices";
  178. else
  179. idxname = "renesas,clock-indices";
  180. for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
  181. const char *parent_name;
  182. const char *name;
  183. u32 clkidx;
  184. int ret;
  185. /* Skip clocks with no name. */
  186. ret = of_property_read_string_index(np, "clock-output-names",
  187. i, &name);
  188. if (ret < 0 || strlen(name) == 0)
  189. continue;
  190. parent_name = of_clk_get_parent_name(np, i);
  191. ret = of_property_read_u32_index(np, idxname, i, &clkidx);
  192. if (parent_name == NULL || ret < 0)
  193. break;
  194. if (clkidx >= MSTP_MAX_CLOCKS) {
  195. pr_err("%s: invalid clock %pOFn %s index %u\n",
  196. __func__, np, name, clkidx);
  197. continue;
  198. }
  199. clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
  200. clkidx, group);
  201. if (!IS_ERR(clks[clkidx])) {
  202. group->data.clk_num = max(group->data.clk_num,
  203. clkidx + 1);
  204. /*
  205. * Register a clkdev to let board code retrieve the
  206. * clock by name and register aliases for non-DT
  207. * devices.
  208. *
  209. * FIXME: Remove this when all devices that require a
  210. * clock will be instantiated from DT.
  211. */
  212. clk_register_clkdev(clks[clkidx], name, NULL);
  213. } else {
  214. pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
  215. __func__, np, name, PTR_ERR(clks[clkidx]));
  216. }
  217. }
  218. of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
  219. }
  220. CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
  221. int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
  222. {
  223. struct device_node *np = dev->of_node;
  224. struct of_phandle_args clkspec;
  225. struct clk *clk;
  226. int i = 0;
  227. int error;
  228. while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
  229. &clkspec)) {
  230. if (of_device_is_compatible(clkspec.np,
  231. "renesas,cpg-mstp-clocks"))
  232. goto found;
  233. /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
  234. if (of_node_name_eq(clkspec.np, "zb_clk"))
  235. goto found;
  236. of_node_put(clkspec.np);
  237. i++;
  238. }
  239. return 0;
  240. found:
  241. clk = of_clk_get_from_provider(&clkspec);
  242. of_node_put(clkspec.np);
  243. if (IS_ERR(clk))
  244. return PTR_ERR(clk);
  245. error = pm_clk_create(dev);
  246. if (error)
  247. goto fail_put;
  248. error = pm_clk_add_clk(dev, clk);
  249. if (error)
  250. goto fail_destroy;
  251. return 0;
  252. fail_destroy:
  253. pm_clk_destroy(dev);
  254. fail_put:
  255. clk_put(clk);
  256. return error;
  257. }
  258. void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
  259. {
  260. if (!pm_clk_no_clocks(dev))
  261. pm_clk_destroy(dev);
  262. }
  263. void __init cpg_mstp_add_clk_domain(struct device_node *np)
  264. {
  265. struct generic_pm_domain *pd;
  266. u32 ncells;
  267. if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
  268. pr_warn("%pOF lacks #power-domain-cells\n", np);
  269. return;
  270. }
  271. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  272. if (!pd)
  273. return;
  274. pd->name = np->name;
  275. pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
  276. GENPD_FLAG_ACTIVE_WAKEUP;
  277. pd->attach_dev = cpg_mstp_attach_dev;
  278. pd->detach_dev = cpg_mstp_detach_dev;
  279. pm_genpd_init(pd, &pm_domain_always_on_gov, false);
  280. of_genpd_add_provider_simple(np, pd);
  281. }