clk-emev2.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * EMMA Mobile EV2 common clock framework support
  4. *
  5. * Copyright (C) 2013 Takashi Yoshii <takashi.yoshii.ze@renesas.com>
  6. * Copyright (C) 2012 Magnus Damm
  7. */
  8. #include <linux/clk-provider.h>
  9. #include <linux/clkdev.h>
  10. #include <linux/io.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. /* EMEV2 SMU registers */
  14. #define USIAU0_RSTCTRL 0x094
  15. #define USIBU1_RSTCTRL 0x0ac
  16. #define USIBU2_RSTCTRL 0x0b0
  17. #define USIBU3_RSTCTRL 0x0b4
  18. #define IIC0_RSTCTRL 0x0dc
  19. #define IIC1_RSTCTRL 0x0e0
  20. #define STI_RSTCTRL 0x124
  21. #define STI_CLKSEL 0x688
  22. static DEFINE_SPINLOCK(lock);
  23. /* not pretty, but hey */
  24. static void __iomem *smu_base;
  25. static void __init emev2_smu_write(unsigned long value, int offs)
  26. {
  27. BUG_ON(!smu_base || (offs >= PAGE_SIZE));
  28. writel_relaxed(value, smu_base + offs);
  29. }
  30. static const struct of_device_id smu_id[] __initconst = {
  31. { .compatible = "renesas,emev2-smu", },
  32. {},
  33. };
  34. static void __init emev2_smu_init(void)
  35. {
  36. struct device_node *np;
  37. np = of_find_matching_node(NULL, smu_id);
  38. BUG_ON(!np);
  39. smu_base = of_iomap(np, 0);
  40. BUG_ON(!smu_base);
  41. of_node_put(np);
  42. /* setup STI timer to run on 32.768 kHz and deassert reset */
  43. emev2_smu_write(0, STI_CLKSEL);
  44. emev2_smu_write(1, STI_RSTCTRL);
  45. /* deassert reset for UART0->UART3 */
  46. emev2_smu_write(2, USIAU0_RSTCTRL);
  47. emev2_smu_write(2, USIBU1_RSTCTRL);
  48. emev2_smu_write(2, USIBU2_RSTCTRL);
  49. emev2_smu_write(2, USIBU3_RSTCTRL);
  50. /* deassert reset for IIC0->IIC1 */
  51. emev2_smu_write(1, IIC0_RSTCTRL);
  52. emev2_smu_write(1, IIC1_RSTCTRL);
  53. }
  54. static void __init emev2_smu_clkdiv_init(struct device_node *np)
  55. {
  56. u32 reg[2];
  57. struct clk *clk;
  58. const char *parent_name = of_clk_get_parent_name(np, 0);
  59. if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
  60. return;
  61. if (!smu_base)
  62. emev2_smu_init();
  63. clk = clk_register_divider(NULL, np->name, parent_name, 0,
  64. smu_base + reg[0], reg[1], 8, 0, &lock);
  65. of_clk_add_provider(np, of_clk_src_simple_get, clk);
  66. clk_register_clkdev(clk, np->full_name, NULL);
  67. pr_debug("## %s %pOFn %p\n", __func__, np, clk);
  68. }
  69. CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
  70. emev2_smu_clkdiv_init);
  71. static void __init emev2_smu_gclk_init(struct device_node *np)
  72. {
  73. u32 reg[2];
  74. struct clk *clk;
  75. const char *parent_name = of_clk_get_parent_name(np, 0);
  76. if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
  77. return;
  78. if (!smu_base)
  79. emev2_smu_init();
  80. clk = clk_register_gate(NULL, np->name, parent_name, 0,
  81. smu_base + reg[0], reg[1], 0, &lock);
  82. of_clk_add_provider(np, of_clk_src_simple_get, clk);
  83. clk_register_clkdev(clk, np->full_name, NULL);
  84. pr_debug("## %s %pOFn %p\n", __func__, np, clk);
  85. }
  86. CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);