q6sstop-qcs404.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/bitops.h>
  6. #include <linux/err.h>
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/pm_clock.h>
  10. #include <linux/pm_runtime.h>
  11. #include <linux/regmap.h>
  12. #include <dt-bindings/clock/qcom,q6sstopcc-qcs404.h>
  13. #include "clk-regmap.h"
  14. #include "clk-branch.h"
  15. #include "common.h"
  16. #include "reset.h"
  17. static struct clk_branch lcc_ahbfabric_cbc_clk = {
  18. .halt_reg = 0x1b004,
  19. .halt_check = BRANCH_HALT,
  20. .clkr = {
  21. .enable_reg = 0x1b004,
  22. .enable_mask = BIT(0),
  23. .hw.init = &(struct clk_init_data){
  24. .name = "lcc_ahbfabric_cbc_clk",
  25. .ops = &clk_branch2_ops,
  26. },
  27. },
  28. };
  29. static struct clk_branch lcc_q6ss_ahbs_cbc_clk = {
  30. .halt_reg = 0x22000,
  31. .halt_check = BRANCH_VOTED,
  32. .clkr = {
  33. .enable_reg = 0x22000,
  34. .enable_mask = BIT(0),
  35. .hw.init = &(struct clk_init_data){
  36. .name = "lcc_q6ss_ahbs_cbc_clk",
  37. .ops = &clk_branch2_ops,
  38. },
  39. },
  40. };
  41. static struct clk_branch lcc_q6ss_tcm_slave_cbc_clk = {
  42. .halt_reg = 0x1c000,
  43. .halt_check = BRANCH_VOTED,
  44. .clkr = {
  45. .enable_reg = 0x1c000,
  46. .enable_mask = BIT(0),
  47. .hw.init = &(struct clk_init_data){
  48. .name = "lcc_q6ss_tcm_slave_cbc_clk",
  49. .ops = &clk_branch2_ops,
  50. },
  51. },
  52. };
  53. static struct clk_branch lcc_q6ss_ahbm_cbc_clk = {
  54. .halt_reg = 0x22004,
  55. .halt_check = BRANCH_VOTED,
  56. .clkr = {
  57. .enable_reg = 0x22004,
  58. .enable_mask = BIT(0),
  59. .hw.init = &(struct clk_init_data){
  60. .name = "lcc_q6ss_ahbm_cbc_clk",
  61. .ops = &clk_branch2_ops,
  62. },
  63. },
  64. };
  65. static struct clk_branch lcc_q6ss_axim_cbc_clk = {
  66. .halt_reg = 0x1c004,
  67. .halt_check = BRANCH_VOTED,
  68. .clkr = {
  69. .enable_reg = 0x1c004,
  70. .enable_mask = BIT(0),
  71. .hw.init = &(struct clk_init_data){
  72. .name = "lcc_q6ss_axim_cbc_clk",
  73. .ops = &clk_branch2_ops,
  74. },
  75. },
  76. };
  77. static struct clk_branch lcc_q6ss_bcr_sleep_clk = {
  78. .halt_reg = 0x6004,
  79. .halt_check = BRANCH_VOTED,
  80. .clkr = {
  81. .enable_reg = 0x6004,
  82. .enable_mask = BIT(0),
  83. .hw.init = &(struct clk_init_data){
  84. .name = "lcc_q6ss_bcr_sleep_clk",
  85. .ops = &clk_branch2_ops,
  86. },
  87. },
  88. };
  89. /* TCSR clock */
  90. static struct clk_branch tcsr_lcc_csr_cbcr_clk = {
  91. .halt_reg = 0x8008,
  92. .halt_check = BRANCH_VOTED,
  93. .clkr = {
  94. .enable_reg = 0x8008,
  95. .enable_mask = BIT(0),
  96. .hw.init = &(struct clk_init_data){
  97. .name = "tcsr_lcc_csr_cbcr_clk",
  98. .ops = &clk_branch2_ops,
  99. },
  100. },
  101. };
  102. static struct regmap_config q6sstop_regmap_config = {
  103. .reg_bits = 32,
  104. .reg_stride = 4,
  105. .val_bits = 32,
  106. .fast_io = true,
  107. };
  108. static struct clk_regmap *q6sstop_qcs404_clocks[] = {
  109. [LCC_AHBFABRIC_CBC_CLK] = &lcc_ahbfabric_cbc_clk.clkr,
  110. [LCC_Q6SS_AHBS_CBC_CLK] = &lcc_q6ss_ahbs_cbc_clk.clkr,
  111. [LCC_Q6SS_TCM_SLAVE_CBC_CLK] = &lcc_q6ss_tcm_slave_cbc_clk.clkr,
  112. [LCC_Q6SS_AHBM_CBC_CLK] = &lcc_q6ss_ahbm_cbc_clk.clkr,
  113. [LCC_Q6SS_AXIM_CBC_CLK] = &lcc_q6ss_axim_cbc_clk.clkr,
  114. [LCC_Q6SS_BCR_SLEEP_CLK] = &lcc_q6ss_bcr_sleep_clk.clkr,
  115. };
  116. static const struct qcom_reset_map q6sstop_qcs404_resets[] = {
  117. [Q6SSTOP_BCR_RESET] = { 0x6000 },
  118. };
  119. static const struct qcom_cc_desc q6sstop_qcs404_desc = {
  120. .config = &q6sstop_regmap_config,
  121. .clks = q6sstop_qcs404_clocks,
  122. .num_clks = ARRAY_SIZE(q6sstop_qcs404_clocks),
  123. .resets = q6sstop_qcs404_resets,
  124. .num_resets = ARRAY_SIZE(q6sstop_qcs404_resets),
  125. };
  126. static struct clk_regmap *tcsr_qcs404_clocks[] = {
  127. [TCSR_Q6SS_LCC_CBCR_CLK] = &tcsr_lcc_csr_cbcr_clk.clkr,
  128. };
  129. static const struct qcom_cc_desc tcsr_qcs404_desc = {
  130. .config = &q6sstop_regmap_config,
  131. .clks = tcsr_qcs404_clocks,
  132. .num_clks = ARRAY_SIZE(tcsr_qcs404_clocks),
  133. };
  134. static const struct of_device_id q6sstopcc_qcs404_match_table[] = {
  135. { .compatible = "qcom,qcs404-q6sstopcc" },
  136. { }
  137. };
  138. MODULE_DEVICE_TABLE(of, q6sstopcc_qcs404_match_table);
  139. static int q6sstopcc_qcs404_probe(struct platform_device *pdev)
  140. {
  141. const struct qcom_cc_desc *desc;
  142. int ret;
  143. pm_runtime_enable(&pdev->dev);
  144. ret = pm_clk_create(&pdev->dev);
  145. if (ret)
  146. goto disable_pm_runtime;
  147. ret = pm_clk_add(&pdev->dev, NULL);
  148. if (ret < 0) {
  149. dev_err(&pdev->dev, "failed to acquire iface clock\n");
  150. goto destroy_pm_clk;
  151. }
  152. q6sstop_regmap_config.name = "q6sstop_tcsr";
  153. desc = &tcsr_qcs404_desc;
  154. ret = qcom_cc_probe_by_index(pdev, 1, desc);
  155. if (ret)
  156. goto destroy_pm_clk;
  157. q6sstop_regmap_config.name = "q6sstop_cc";
  158. desc = &q6sstop_qcs404_desc;
  159. ret = qcom_cc_probe_by_index(pdev, 0, desc);
  160. if (ret)
  161. goto destroy_pm_clk;
  162. return 0;
  163. destroy_pm_clk:
  164. pm_clk_destroy(&pdev->dev);
  165. disable_pm_runtime:
  166. pm_runtime_disable(&pdev->dev);
  167. return ret;
  168. }
  169. static int q6sstopcc_qcs404_remove(struct platform_device *pdev)
  170. {
  171. pm_clk_destroy(&pdev->dev);
  172. pm_runtime_disable(&pdev->dev);
  173. return 0;
  174. }
  175. static const struct dev_pm_ops q6sstopcc_pm_ops = {
  176. SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
  177. };
  178. static struct platform_driver q6sstopcc_qcs404_driver = {
  179. .probe = q6sstopcc_qcs404_probe,
  180. .remove = q6sstopcc_qcs404_remove,
  181. .driver = {
  182. .name = "qcs404-q6sstopcc",
  183. .of_match_table = q6sstopcc_qcs404_match_table,
  184. .pm = &q6sstopcc_pm_ops,
  185. },
  186. };
  187. module_platform_driver(q6sstopcc_qcs404_driver);
  188. MODULE_DESCRIPTION("QTI QCS404 Q6SSTOP Clock Controller Driver");
  189. MODULE_LICENSE("GPL v2");