lpasscorecc-sc7180.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk-provider.h>
  6. #include <linux/err.h>
  7. #include <linux/module.h>
  8. #include <linux/of_device.h>
  9. #include <linux/pm_clock.h>
  10. #include <linux/pm_runtime.h>
  11. #include <linux/of.h>
  12. #include <linux/regmap.h>
  13. #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
  14. #include "clk-alpha-pll.h"
  15. #include "clk-branch.h"
  16. #include "clk-rcg.h"
  17. #include "clk-regmap.h"
  18. #include "common.h"
  19. #include "gdsc.h"
  20. enum {
  21. P_BI_TCXO,
  22. P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD,
  23. P_SLEEP_CLK,
  24. };
  25. static struct pll_vco fabia_vco[] = {
  26. { 249600000, 2000000000, 0 },
  27. };
  28. static const struct alpha_pll_config lpass_lpaaudio_dig_pll_config = {
  29. .l = 0x20,
  30. .alpha = 0x0,
  31. .config_ctl_val = 0x20485699,
  32. .config_ctl_hi_val = 0x00002067,
  33. .test_ctl_val = 0x40000000,
  34. .test_ctl_hi_val = 0x00000000,
  35. .user_ctl_val = 0x00005105,
  36. .user_ctl_hi_val = 0x00004805,
  37. };
  38. static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
  39. [CLK_ALPHA_PLL_TYPE_FABIA] = {
  40. [PLL_OFF_L_VAL] = 0x04,
  41. [PLL_OFF_CAL_L_VAL] = 0x8,
  42. [PLL_OFF_USER_CTL] = 0x0c,
  43. [PLL_OFF_USER_CTL_U] = 0x10,
  44. [PLL_OFF_USER_CTL_U1] = 0x14,
  45. [PLL_OFF_CONFIG_CTL] = 0x18,
  46. [PLL_OFF_CONFIG_CTL_U] = 0x1C,
  47. [PLL_OFF_CONFIG_CTL_U1] = 0x20,
  48. [PLL_OFF_TEST_CTL] = 0x24,
  49. [PLL_OFF_TEST_CTL_U] = 0x28,
  50. [PLL_OFF_STATUS] = 0x30,
  51. [PLL_OFF_OPMODE] = 0x38,
  52. [PLL_OFF_FRAC] = 0x40,
  53. },
  54. };
  55. static struct clk_alpha_pll lpass_lpaaudio_dig_pll = {
  56. .offset = 0x1000,
  57. .vco_table = fabia_vco,
  58. .num_vco = ARRAY_SIZE(fabia_vco),
  59. .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_FABIA],
  60. .clkr = {
  61. .hw.init = &(struct clk_init_data){
  62. .name = "lpass_lpaaudio_dig_pll",
  63. .parent_data = &(const struct clk_parent_data){
  64. .fw_name = "bi_tcxo",
  65. },
  66. .num_parents = 1,
  67. .ops = &clk_alpha_pll_fabia_ops,
  68. },
  69. },
  70. };
  71. static const struct clk_div_table
  72. post_div_table_lpass_lpaaudio_dig_pll_out_odd[] = {
  73. { 0x5, 5 },
  74. { }
  75. };
  76. static struct clk_alpha_pll_postdiv lpass_lpaaudio_dig_pll_out_odd = {
  77. .offset = 0x1000,
  78. .post_div_shift = 12,
  79. .post_div_table = post_div_table_lpass_lpaaudio_dig_pll_out_odd,
  80. .num_post_div =
  81. ARRAY_SIZE(post_div_table_lpass_lpaaudio_dig_pll_out_odd),
  82. .width = 4,
  83. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  84. .clkr.hw.init = &(struct clk_init_data){
  85. .name = "lpass_lpaaudio_dig_pll_out_odd",
  86. .parent_data = &(const struct clk_parent_data){
  87. .hw = &lpass_lpaaudio_dig_pll.clkr.hw,
  88. },
  89. .num_parents = 1,
  90. .flags = CLK_SET_RATE_PARENT,
  91. .ops = &clk_alpha_pll_postdiv_fabia_ops,
  92. },
  93. };
  94. static const struct parent_map lpass_core_cc_parent_map_0[] = {
  95. { P_BI_TCXO, 0 },
  96. { P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 5 },
  97. };
  98. static const struct clk_parent_data lpass_core_cc_parent_data_0[] = {
  99. { .fw_name = "bi_tcxo" },
  100. { .hw = &lpass_lpaaudio_dig_pll_out_odd.clkr.hw },
  101. };
  102. static const struct parent_map lpass_core_cc_parent_map_2[] = {
  103. { P_BI_TCXO, 0 },
  104. };
  105. static struct clk_rcg2 core_clk_src = {
  106. .cmd_rcgr = 0x1d000,
  107. .mnd_width = 8,
  108. .hid_width = 5,
  109. .parent_map = lpass_core_cc_parent_map_2,
  110. .clkr.hw.init = &(struct clk_init_data){
  111. .name = "core_clk_src",
  112. .parent_data = &(const struct clk_parent_data){
  113. .fw_name = "bi_tcxo",
  114. },
  115. .num_parents = 1,
  116. .ops = &clk_rcg2_ops,
  117. },
  118. };
  119. static const struct freq_tbl ftbl_ext_mclk0_clk_src[] = {
  120. F(9600000, P_BI_TCXO, 2, 0, 0),
  121. F(19200000, P_BI_TCXO, 1, 0, 0),
  122. { }
  123. };
  124. static const struct freq_tbl ftbl_ext_lpaif_clk_src[] = {
  125. F(256000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 32),
  126. F(512000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 16),
  127. F(768000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 16),
  128. F(1024000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 8),
  129. F(1536000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 8),
  130. F(2048000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 4),
  131. F(3072000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 4),
  132. F(4096000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 2),
  133. F(6144000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 2),
  134. F(8192000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 0, 0),
  135. F(9600000, P_BI_TCXO, 2, 0, 0),
  136. F(12288000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 0, 0),
  137. F(19200000, P_BI_TCXO, 1, 0, 0),
  138. F(24576000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 5, 0, 0),
  139. { }
  140. };
  141. static struct clk_rcg2 ext_mclk0_clk_src = {
  142. .cmd_rcgr = 0x20000,
  143. .mnd_width = 8,
  144. .hid_width = 5,
  145. .parent_map = lpass_core_cc_parent_map_0,
  146. .freq_tbl = ftbl_ext_mclk0_clk_src,
  147. .clkr.hw.init = &(struct clk_init_data){
  148. .name = "ext_mclk0_clk_src",
  149. .parent_data = lpass_core_cc_parent_data_0,
  150. .num_parents = 2,
  151. .flags = CLK_SET_RATE_PARENT,
  152. .ops = &clk_rcg2_ops,
  153. },
  154. };
  155. static struct clk_rcg2 lpaif_pri_clk_src = {
  156. .cmd_rcgr = 0x10000,
  157. .mnd_width = 16,
  158. .hid_width = 5,
  159. .parent_map = lpass_core_cc_parent_map_0,
  160. .freq_tbl = ftbl_ext_lpaif_clk_src,
  161. .clkr.hw.init = &(struct clk_init_data){
  162. .name = "lpaif_pri_clk_src",
  163. .parent_data = lpass_core_cc_parent_data_0,
  164. .num_parents = 2,
  165. .flags = CLK_SET_RATE_PARENT,
  166. .ops = &clk_rcg2_ops,
  167. },
  168. };
  169. static struct clk_rcg2 lpaif_sec_clk_src = {
  170. .cmd_rcgr = 0x11000,
  171. .mnd_width = 16,
  172. .hid_width = 5,
  173. .parent_map = lpass_core_cc_parent_map_0,
  174. .freq_tbl = ftbl_ext_lpaif_clk_src,
  175. .clkr.hw.init = &(struct clk_init_data){
  176. .name = "lpaif_sec_clk_src",
  177. .parent_data = lpass_core_cc_parent_data_0,
  178. .num_parents = 2,
  179. .flags = CLK_SET_RATE_PARENT,
  180. .ops = &clk_rcg2_ops,
  181. },
  182. };
  183. static struct clk_branch lpass_audio_core_ext_mclk0_clk = {
  184. .halt_reg = 0x20014,
  185. .halt_check = BRANCH_HALT,
  186. .hwcg_reg = 0x20014,
  187. .hwcg_bit = 1,
  188. .clkr = {
  189. .enable_reg = 0x20014,
  190. .enable_mask = BIT(0),
  191. .hw.init = &(struct clk_init_data){
  192. .name = "lpass_audio_core_ext_mclk0_clk",
  193. .parent_data = &(const struct clk_parent_data){
  194. .hw = &ext_mclk0_clk_src.clkr.hw,
  195. },
  196. .num_parents = 1,
  197. .flags = CLK_SET_RATE_PARENT,
  198. .ops = &clk_branch2_ops,
  199. },
  200. },
  201. };
  202. static struct clk_branch lpass_audio_core_lpaif_pri_ibit_clk = {
  203. .halt_reg = 0x10018,
  204. .halt_check = BRANCH_HALT,
  205. .hwcg_reg = 0x10018,
  206. .hwcg_bit = 1,
  207. .clkr = {
  208. .enable_reg = 0x10018,
  209. .enable_mask = BIT(0),
  210. .hw.init = &(struct clk_init_data){
  211. .name = "lpass_audio_core_lpaif_pri_ibit_clk",
  212. .parent_data = &(const struct clk_parent_data){
  213. .hw = &lpaif_pri_clk_src.clkr.hw,
  214. },
  215. .num_parents = 1,
  216. .flags = CLK_SET_RATE_PARENT,
  217. .ops = &clk_branch2_ops,
  218. },
  219. },
  220. };
  221. static struct clk_branch lpass_audio_core_lpaif_sec_ibit_clk = {
  222. .halt_reg = 0x11018,
  223. .halt_check = BRANCH_HALT,
  224. .hwcg_reg = 0x11018,
  225. .hwcg_bit = 1,
  226. .clkr = {
  227. .enable_reg = 0x11018,
  228. .enable_mask = BIT(0),
  229. .hw.init = &(struct clk_init_data){
  230. .name = "lpass_audio_core_lpaif_sec_ibit_clk",
  231. .parent_data = &(const struct clk_parent_data){
  232. .hw = &lpaif_sec_clk_src.clkr.hw,
  233. },
  234. .num_parents = 1,
  235. .flags = CLK_SET_RATE_PARENT,
  236. .ops = &clk_branch2_ops,
  237. },
  238. },
  239. };
  240. static struct clk_branch lpass_audio_core_sysnoc_mport_core_clk = {
  241. .halt_reg = 0x23000,
  242. .halt_check = BRANCH_HALT,
  243. .hwcg_reg = 0x23000,
  244. .hwcg_bit = 1,
  245. .clkr = {
  246. .enable_reg = 0x23000,
  247. .enable_mask = BIT(0),
  248. .hw.init = &(struct clk_init_data){
  249. .name = "lpass_audio_core_sysnoc_mport_core_clk",
  250. .parent_data = &(const struct clk_parent_data){
  251. .hw = &core_clk_src.clkr.hw,
  252. },
  253. .num_parents = 1,
  254. .flags = CLK_SET_RATE_PARENT,
  255. .ops = &clk_branch2_ops,
  256. },
  257. },
  258. };
  259. static struct clk_regmap *lpass_core_cc_sc7180_clocks[] = {
  260. [EXT_MCLK0_CLK_SRC] = &ext_mclk0_clk_src.clkr,
  261. [LPAIF_PRI_CLK_SRC] = &lpaif_pri_clk_src.clkr,
  262. [LPAIF_SEC_CLK_SRC] = &lpaif_sec_clk_src.clkr,
  263. [CORE_CLK_SRC] = &core_clk_src.clkr,
  264. [LPASS_AUDIO_CORE_EXT_MCLK0_CLK] = &lpass_audio_core_ext_mclk0_clk.clkr,
  265. [LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK] =
  266. &lpass_audio_core_lpaif_pri_ibit_clk.clkr,
  267. [LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK] =
  268. &lpass_audio_core_lpaif_sec_ibit_clk.clkr,
  269. [LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK] =
  270. &lpass_audio_core_sysnoc_mport_core_clk.clkr,
  271. [LPASS_LPAAUDIO_DIG_PLL] = &lpass_lpaaudio_dig_pll.clkr,
  272. [LPASS_LPAAUDIO_DIG_PLL_OUT_ODD] = &lpass_lpaaudio_dig_pll_out_odd.clkr,
  273. };
  274. static struct gdsc lpass_pdc_hm_gdsc = {
  275. .gdscr = 0x3090,
  276. .pd = {
  277. .name = "lpass_pdc_hm_gdsc",
  278. },
  279. .pwrsts = PWRSTS_OFF_ON,
  280. .flags = VOTABLE,
  281. };
  282. static struct gdsc lpass_audio_hm_gdsc = {
  283. .gdscr = 0x9090,
  284. .pd = {
  285. .name = "lpass_audio_hm_gdsc",
  286. },
  287. .pwrsts = PWRSTS_OFF_ON,
  288. };
  289. static struct gdsc lpass_core_hm_gdsc = {
  290. .gdscr = 0x0,
  291. .pd = {
  292. .name = "lpass_core_hm_gdsc",
  293. },
  294. .pwrsts = PWRSTS_OFF_ON,
  295. .flags = RETAIN_FF_ENABLE,
  296. };
  297. static struct gdsc *lpass_core_hm_sc7180_gdscs[] = {
  298. [LPASS_CORE_HM_GDSCR] = &lpass_core_hm_gdsc,
  299. };
  300. static struct gdsc *lpass_audio_hm_sc7180_gdscs[] = {
  301. [LPASS_PDC_HM_GDSCR] = &lpass_pdc_hm_gdsc,
  302. [LPASS_AUDIO_HM_GDSCR] = &lpass_audio_hm_gdsc,
  303. };
  304. static struct regmap_config lpass_core_cc_sc7180_regmap_config = {
  305. .reg_bits = 32,
  306. .reg_stride = 4,
  307. .val_bits = 32,
  308. .fast_io = true,
  309. };
  310. static const struct qcom_cc_desc lpass_core_hm_sc7180_desc = {
  311. .config = &lpass_core_cc_sc7180_regmap_config,
  312. .gdscs = lpass_core_hm_sc7180_gdscs,
  313. .num_gdscs = ARRAY_SIZE(lpass_core_hm_sc7180_gdscs),
  314. };
  315. static const struct qcom_cc_desc lpass_core_cc_sc7180_desc = {
  316. .config = &lpass_core_cc_sc7180_regmap_config,
  317. .clks = lpass_core_cc_sc7180_clocks,
  318. .num_clks = ARRAY_SIZE(lpass_core_cc_sc7180_clocks),
  319. };
  320. static const struct qcom_cc_desc lpass_audio_hm_sc7180_desc = {
  321. .config = &lpass_core_cc_sc7180_regmap_config,
  322. .gdscs = lpass_audio_hm_sc7180_gdscs,
  323. .num_gdscs = ARRAY_SIZE(lpass_audio_hm_sc7180_gdscs),
  324. };
  325. static int lpass_core_cc_sc7180_probe(struct platform_device *pdev)
  326. {
  327. const struct qcom_cc_desc *desc;
  328. struct regmap *regmap;
  329. int ret;
  330. lpass_core_cc_sc7180_regmap_config.name = "lpass_audio_cc";
  331. desc = &lpass_audio_hm_sc7180_desc;
  332. ret = qcom_cc_probe_by_index(pdev, 1, desc);
  333. if (ret)
  334. return ret;
  335. lpass_core_cc_sc7180_regmap_config.name = "lpass_core_cc";
  336. regmap = qcom_cc_map(pdev, &lpass_core_cc_sc7180_desc);
  337. if (IS_ERR(regmap))
  338. return PTR_ERR(regmap);
  339. /*
  340. * Keep the CLK always-ON
  341. * LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK
  342. */
  343. regmap_update_bits(regmap, 0x24000, BIT(0), BIT(0));
  344. /* PLL settings */
  345. regmap_write(regmap, 0x1008, 0x20);
  346. regmap_update_bits(regmap, 0x1014, BIT(0), BIT(0));
  347. clk_fabia_pll_configure(&lpass_lpaaudio_dig_pll, regmap,
  348. &lpass_lpaaudio_dig_pll_config);
  349. return qcom_cc_really_probe(pdev, &lpass_core_cc_sc7180_desc, regmap);
  350. }
  351. static int lpass_hm_core_probe(struct platform_device *pdev)
  352. {
  353. const struct qcom_cc_desc *desc;
  354. lpass_core_cc_sc7180_regmap_config.name = "lpass_hm_core";
  355. desc = &lpass_core_hm_sc7180_desc;
  356. return qcom_cc_probe_by_index(pdev, 0, desc);
  357. }
  358. static const struct of_device_id lpass_core_cc_sc7180_match_table[] = {
  359. {
  360. .compatible = "qcom,sc7180-lpasshm",
  361. .data = lpass_hm_core_probe,
  362. },
  363. {
  364. .compatible = "qcom,sc7180-lpasscorecc",
  365. .data = lpass_core_cc_sc7180_probe,
  366. },
  367. { }
  368. };
  369. MODULE_DEVICE_TABLE(of, lpass_core_cc_sc7180_match_table);
  370. static int lpass_core_sc7180_probe(struct platform_device *pdev)
  371. {
  372. int (*clk_probe)(struct platform_device *p);
  373. int ret;
  374. pm_runtime_enable(&pdev->dev);
  375. ret = pm_clk_create(&pdev->dev);
  376. if (ret)
  377. goto disable_pm_runtime;
  378. ret = pm_clk_add(&pdev->dev, "iface");
  379. if (ret < 0) {
  380. dev_err(&pdev->dev, "failed to acquire iface clock\n");
  381. goto destroy_pm_clk;
  382. }
  383. ret = -EINVAL;
  384. clk_probe = of_device_get_match_data(&pdev->dev);
  385. if (!clk_probe)
  386. goto destroy_pm_clk;
  387. ret = clk_probe(pdev);
  388. if (ret)
  389. goto destroy_pm_clk;
  390. return 0;
  391. destroy_pm_clk:
  392. pm_clk_destroy(&pdev->dev);
  393. disable_pm_runtime:
  394. pm_runtime_disable(&pdev->dev);
  395. return ret;
  396. }
  397. static const struct dev_pm_ops lpass_core_cc_pm_ops = {
  398. SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
  399. };
  400. static struct platform_driver lpass_core_cc_sc7180_driver = {
  401. .probe = lpass_core_sc7180_probe,
  402. .driver = {
  403. .name = "lpass_core_cc-sc7180",
  404. .of_match_table = lpass_core_cc_sc7180_match_table,
  405. .pm = &lpass_core_cc_pm_ops,
  406. },
  407. };
  408. static int __init lpass_core_cc_sc7180_init(void)
  409. {
  410. return platform_driver_register(&lpass_core_cc_sc7180_driver);
  411. }
  412. subsys_initcall(lpass_core_cc_sc7180_init);
  413. static void __exit lpass_core_cc_sc7180_exit(void)
  414. {
  415. platform_driver_unregister(&lpass_core_cc_sc7180_driver);
  416. }
  417. module_exit(lpass_core_cc_sc7180_exit);
  418. MODULE_DESCRIPTION("QTI LPASS_CORE_CC SC7180 Driver");
  419. MODULE_LICENSE("GPL v2");