gpucc-sm8250.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk-provider.h>
  6. #include <linux/module.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/regmap.h>
  9. #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
  10. #include "common.h"
  11. #include "clk-alpha-pll.h"
  12. #include "clk-branch.h"
  13. #include "clk-pll.h"
  14. #include "clk-rcg.h"
  15. #include "clk-regmap.h"
  16. #include "reset.h"
  17. #include "gdsc.h"
  18. #define CX_GMU_CBCR_SLEEP_MASK 0xf
  19. #define CX_GMU_CBCR_SLEEP_SHIFT 4
  20. #define CX_GMU_CBCR_WAKE_MASK 0xf
  21. #define CX_GMU_CBCR_WAKE_SHIFT 8
  22. enum {
  23. P_BI_TCXO,
  24. P_CORE_BI_PLL_TEST_SE,
  25. P_GPLL0_OUT_MAIN,
  26. P_GPLL0_OUT_MAIN_DIV,
  27. P_GPU_CC_PLL0_OUT_MAIN,
  28. P_GPU_CC_PLL1_OUT_MAIN,
  29. };
  30. static struct pll_vco lucid_vco[] = {
  31. { 249600000, 2000000000, 0 },
  32. };
  33. static const struct alpha_pll_config gpu_cc_pll1_config = {
  34. .l = 0x1a,
  35. .alpha = 0xaaa,
  36. .config_ctl_val = 0x20485699,
  37. .config_ctl_hi_val = 0x00002261,
  38. .config_ctl_hi1_val = 0x029a699c,
  39. .user_ctl_val = 0x00000000,
  40. .user_ctl_hi_val = 0x00000805,
  41. .user_ctl_hi1_val = 0x00000000,
  42. };
  43. static struct clk_alpha_pll gpu_cc_pll1 = {
  44. .offset = 0x100,
  45. .vco_table = lucid_vco,
  46. .num_vco = ARRAY_SIZE(lucid_vco),
  47. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  48. .clkr = {
  49. .hw.init = &(struct clk_init_data){
  50. .name = "gpu_cc_pll1",
  51. .parent_data = &(const struct clk_parent_data){
  52. .fw_name = "bi_tcxo",
  53. },
  54. .num_parents = 1,
  55. .ops = &clk_alpha_pll_lucid_ops,
  56. },
  57. },
  58. };
  59. static const struct parent_map gpu_cc_parent_map_0[] = {
  60. { P_BI_TCXO, 0 },
  61. { P_GPU_CC_PLL1_OUT_MAIN, 3 },
  62. { P_GPLL0_OUT_MAIN, 5 },
  63. { P_GPLL0_OUT_MAIN_DIV, 6 },
  64. };
  65. static const struct clk_parent_data gpu_cc_parent_data_0[] = {
  66. { .fw_name = "bi_tcxo" },
  67. { .hw = &gpu_cc_pll1.clkr.hw },
  68. { .fw_name = "gcc_gpu_gpll0_clk_src" },
  69. { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
  70. };
  71. static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
  72. F(19200000, P_BI_TCXO, 1, 0, 0),
  73. F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
  74. F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
  75. { }
  76. };
  77. static struct clk_rcg2 gpu_cc_gmu_clk_src = {
  78. .cmd_rcgr = 0x1120,
  79. .mnd_width = 0,
  80. .hid_width = 5,
  81. .parent_map = gpu_cc_parent_map_0,
  82. .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
  83. .clkr.hw.init = &(struct clk_init_data){
  84. .name = "gpu_cc_gmu_clk_src",
  85. .parent_data = gpu_cc_parent_data_0,
  86. .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
  87. .flags = CLK_SET_RATE_PARENT,
  88. .ops = &clk_rcg2_ops,
  89. },
  90. };
  91. static struct clk_branch gpu_cc_ahb_clk = {
  92. .halt_reg = 0x1078,
  93. .halt_check = BRANCH_HALT_DELAY,
  94. .clkr = {
  95. .enable_reg = 0x1078,
  96. .enable_mask = BIT(0),
  97. .hw.init = &(struct clk_init_data){
  98. .name = "gpu_cc_ahb_clk",
  99. .ops = &clk_branch2_ops,
  100. },
  101. },
  102. };
  103. static struct clk_branch gpu_cc_crc_ahb_clk = {
  104. .halt_reg = 0x107c,
  105. .halt_check = BRANCH_HALT_VOTED,
  106. .clkr = {
  107. .enable_reg = 0x107c,
  108. .enable_mask = BIT(0),
  109. .hw.init = &(struct clk_init_data){
  110. .name = "gpu_cc_crc_ahb_clk",
  111. .ops = &clk_branch2_ops,
  112. },
  113. },
  114. };
  115. static struct clk_branch gpu_cc_cx_apb_clk = {
  116. .halt_reg = 0x1088,
  117. .halt_check = BRANCH_HALT_VOTED,
  118. .clkr = {
  119. .enable_reg = 0x1088,
  120. .enable_mask = BIT(0),
  121. .hw.init = &(struct clk_init_data){
  122. .name = "gpu_cc_cx_apb_clk",
  123. .ops = &clk_branch2_ops,
  124. },
  125. },
  126. };
  127. static struct clk_branch gpu_cc_cx_gmu_clk = {
  128. .halt_reg = 0x1098,
  129. .halt_check = BRANCH_HALT,
  130. .clkr = {
  131. .enable_reg = 0x1098,
  132. .enable_mask = BIT(0),
  133. .hw.init = &(struct clk_init_data){
  134. .name = "gpu_cc_cx_gmu_clk",
  135. .parent_data = &(const struct clk_parent_data){
  136. .hw = &gpu_cc_gmu_clk_src.clkr.hw,
  137. },
  138. .num_parents = 1,
  139. .flags = CLK_SET_RATE_PARENT,
  140. .ops = &clk_branch2_ops,
  141. },
  142. },
  143. };
  144. static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
  145. .halt_reg = 0x108c,
  146. .halt_check = BRANCH_HALT_VOTED,
  147. .clkr = {
  148. .enable_reg = 0x108c,
  149. .enable_mask = BIT(0),
  150. .hw.init = &(struct clk_init_data){
  151. .name = "gpu_cc_cx_snoc_dvm_clk",
  152. .ops = &clk_branch2_ops,
  153. },
  154. },
  155. };
  156. static struct clk_branch gpu_cc_cxo_aon_clk = {
  157. .halt_reg = 0x1004,
  158. .halt_check = BRANCH_HALT_VOTED,
  159. .clkr = {
  160. .enable_reg = 0x1004,
  161. .enable_mask = BIT(0),
  162. .hw.init = &(struct clk_init_data){
  163. .name = "gpu_cc_cxo_aon_clk",
  164. .ops = &clk_branch2_ops,
  165. },
  166. },
  167. };
  168. static struct clk_branch gpu_cc_cxo_clk = {
  169. .halt_reg = 0x109c,
  170. .halt_check = BRANCH_HALT,
  171. .clkr = {
  172. .enable_reg = 0x109c,
  173. .enable_mask = BIT(0),
  174. .hw.init = &(struct clk_init_data){
  175. .name = "gpu_cc_cxo_clk",
  176. .ops = &clk_branch2_ops,
  177. },
  178. },
  179. };
  180. static struct clk_branch gpu_cc_gx_gmu_clk = {
  181. .halt_reg = 0x1064,
  182. .halt_check = BRANCH_HALT,
  183. .clkr = {
  184. .enable_reg = 0x1064,
  185. .enable_mask = BIT(0),
  186. .hw.init = &(struct clk_init_data){
  187. .name = "gpu_cc_gx_gmu_clk",
  188. .parent_data = &(const struct clk_parent_data){
  189. .hw = &gpu_cc_gmu_clk_src.clkr.hw,
  190. },
  191. .num_parents = 1,
  192. .flags = CLK_SET_RATE_PARENT,
  193. .ops = &clk_branch2_ops,
  194. },
  195. },
  196. };
  197. static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
  198. .halt_reg = 0x5000,
  199. .halt_check = BRANCH_VOTED,
  200. .clkr = {
  201. .enable_reg = 0x5000,
  202. .enable_mask = BIT(0),
  203. .hw.init = &(struct clk_init_data){
  204. .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
  205. .ops = &clk_branch2_ops,
  206. },
  207. },
  208. };
  209. static struct gdsc gpu_cx_gdsc = {
  210. .gdscr = 0x106c,
  211. .gds_hw_ctrl = 0x1540,
  212. .pd = {
  213. .name = "gpu_cx_gdsc",
  214. },
  215. .pwrsts = PWRSTS_OFF_ON,
  216. .flags = VOTABLE,
  217. };
  218. static struct gdsc gpu_gx_gdsc = {
  219. .gdscr = 0x100c,
  220. .clamp_io_ctrl = 0x1508,
  221. .pd = {
  222. .name = "gpu_gx_gdsc",
  223. .power_on = gdsc_gx_do_nothing_enable,
  224. },
  225. .pwrsts = PWRSTS_OFF_ON,
  226. .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
  227. };
  228. static struct clk_regmap *gpu_cc_sm8250_clocks[] = {
  229. [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
  230. [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
  231. [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
  232. [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
  233. [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
  234. [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
  235. [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
  236. [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
  237. [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
  238. [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
  239. [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
  240. };
  241. static const struct qcom_reset_map gpu_cc_sm8250_resets[] = {
  242. [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
  243. [GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
  244. [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
  245. [GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
  246. [GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
  247. [GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
  248. };
  249. static struct gdsc *gpu_cc_sm8250_gdscs[] = {
  250. [GPU_CX_GDSC] = &gpu_cx_gdsc,
  251. [GPU_GX_GDSC] = &gpu_gx_gdsc,
  252. };
  253. static const struct regmap_config gpu_cc_sm8250_regmap_config = {
  254. .reg_bits = 32,
  255. .reg_stride = 4,
  256. .val_bits = 32,
  257. .max_register = 0x8008,
  258. .fast_io = true,
  259. };
  260. static const struct qcom_cc_desc gpu_cc_sm8250_desc = {
  261. .config = &gpu_cc_sm8250_regmap_config,
  262. .clks = gpu_cc_sm8250_clocks,
  263. .num_clks = ARRAY_SIZE(gpu_cc_sm8250_clocks),
  264. .resets = gpu_cc_sm8250_resets,
  265. .num_resets = ARRAY_SIZE(gpu_cc_sm8250_resets),
  266. .gdscs = gpu_cc_sm8250_gdscs,
  267. .num_gdscs = ARRAY_SIZE(gpu_cc_sm8250_gdscs),
  268. };
  269. static const struct of_device_id gpu_cc_sm8250_match_table[] = {
  270. { .compatible = "qcom,sm8250-gpucc" },
  271. { }
  272. };
  273. MODULE_DEVICE_TABLE(of, gpu_cc_sm8250_match_table);
  274. static int gpu_cc_sm8250_probe(struct platform_device *pdev)
  275. {
  276. struct regmap *regmap;
  277. unsigned int value, mask;
  278. regmap = qcom_cc_map(pdev, &gpu_cc_sm8250_desc);
  279. if (IS_ERR(regmap))
  280. return PTR_ERR(regmap);
  281. clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
  282. /*
  283. * Configure gpu_cc_cx_gmu_clk with recommended
  284. * wakeup/sleep settings
  285. */
  286. mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
  287. mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
  288. value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
  289. regmap_update_bits(regmap, 0x1098, mask, value);
  290. return qcom_cc_really_probe(pdev, &gpu_cc_sm8250_desc, regmap);
  291. }
  292. static struct platform_driver gpu_cc_sm8250_driver = {
  293. .probe = gpu_cc_sm8250_probe,
  294. .driver = {
  295. .name = "sm8250-gpucc",
  296. .of_match_table = gpu_cc_sm8250_match_table,
  297. },
  298. };
  299. static int __init gpu_cc_sm8250_init(void)
  300. {
  301. return platform_driver_register(&gpu_cc_sm8250_driver);
  302. }
  303. subsys_initcall(gpu_cc_sm8250_init);
  304. static void __exit gpu_cc_sm8250_exit(void)
  305. {
  306. platform_driver_unregister(&gpu_cc_sm8250_driver);
  307. }
  308. module_exit(gpu_cc_sm8250_exit);
  309. MODULE_DESCRIPTION("QTI GPU_CC SM8250 Driver");
  310. MODULE_LICENSE("GPL v2");