gcc-sm8150.c 97 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
  3. #include <linux/kernel.h>
  4. #include <linux/bitops.h>
  5. #include <linux/err.h>
  6. #include <linux/platform_device.h>
  7. #include <linux/module.h>
  8. #include <linux/of.h>
  9. #include <linux/of_device.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/regmap.h>
  12. #include <linux/reset-controller.h>
  13. #include <dt-bindings/clock/qcom,gcc-sm8150.h>
  14. #include "common.h"
  15. #include "clk-alpha-pll.h"
  16. #include "clk-branch.h"
  17. #include "clk-pll.h"
  18. #include "clk-rcg.h"
  19. #include "clk-regmap.h"
  20. #include "reset.h"
  21. #include "gdsc.h"
  22. enum {
  23. P_BI_TCXO,
  24. P_AUD_REF_CLK,
  25. P_CORE_BI_PLL_TEST_SE,
  26. P_GPLL0_OUT_EVEN,
  27. P_GPLL0_OUT_MAIN,
  28. P_GPLL7_OUT_MAIN,
  29. P_GPLL9_OUT_MAIN,
  30. P_SLEEP_CLK,
  31. };
  32. static struct clk_alpha_pll gpll0 = {
  33. .offset = 0x0,
  34. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  35. .clkr = {
  36. .enable_reg = 0x52000,
  37. .enable_mask = BIT(0),
  38. .hw.init = &(struct clk_init_data){
  39. .name = "gpll0",
  40. .parent_data = &(const struct clk_parent_data){
  41. .fw_name = "bi_tcxo",
  42. .name = "bi_tcxo",
  43. },
  44. .num_parents = 1,
  45. .ops = &clk_alpha_pll_fixed_trion_ops,
  46. },
  47. },
  48. };
  49. static const struct clk_div_table post_div_table_trion_even[] = {
  50. { 0x0, 1 },
  51. { 0x1, 2 },
  52. { 0x3, 4 },
  53. { 0x7, 8 },
  54. { }
  55. };
  56. static struct clk_alpha_pll_postdiv gpll0_out_even = {
  57. .offset = 0x0,
  58. .post_div_shift = 8,
  59. .post_div_table = post_div_table_trion_even,
  60. .num_post_div = ARRAY_SIZE(post_div_table_trion_even),
  61. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  62. .width = 4,
  63. .clkr.hw.init = &(struct clk_init_data){
  64. .name = "gpll0_out_even",
  65. .parent_data = &(const struct clk_parent_data){
  66. .hw = &gpll0.clkr.hw,
  67. },
  68. .num_parents = 1,
  69. .ops = &clk_alpha_pll_postdiv_trion_ops,
  70. },
  71. };
  72. static struct clk_alpha_pll gpll7 = {
  73. .offset = 0x1a000,
  74. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  75. .clkr = {
  76. .enable_reg = 0x52000,
  77. .enable_mask = BIT(7),
  78. .hw.init = &(struct clk_init_data){
  79. .name = "gpll7",
  80. .parent_data = &(const struct clk_parent_data){
  81. .fw_name = "bi_tcxo",
  82. .name = "bi_tcxo",
  83. },
  84. .num_parents = 1,
  85. .ops = &clk_alpha_pll_fixed_trion_ops,
  86. },
  87. },
  88. };
  89. static struct clk_alpha_pll gpll9 = {
  90. .offset = 0x1c000,
  91. .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  92. .clkr = {
  93. .enable_reg = 0x52000,
  94. .enable_mask = BIT(9),
  95. .hw.init = &(struct clk_init_data){
  96. .name = "gpll9",
  97. .parent_data = &(const struct clk_parent_data){
  98. .fw_name = "bi_tcxo",
  99. .name = "bi_tcxo",
  100. },
  101. .num_parents = 1,
  102. .ops = &clk_alpha_pll_fixed_trion_ops,
  103. },
  104. },
  105. };
  106. static const struct parent_map gcc_parent_map_0[] = {
  107. { P_BI_TCXO, 0 },
  108. { P_GPLL0_OUT_MAIN, 1 },
  109. { P_GPLL0_OUT_EVEN, 6 },
  110. { P_CORE_BI_PLL_TEST_SE, 7 },
  111. };
  112. static const struct clk_parent_data gcc_parents_0[] = {
  113. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  114. { .hw = &gpll0.clkr.hw },
  115. { .hw = &gpll0_out_even.clkr.hw },
  116. { .fw_name = "core_bi_pll_test_se" },
  117. };
  118. static const struct parent_map gcc_parent_map_1[] = {
  119. { P_BI_TCXO, 0 },
  120. { P_GPLL0_OUT_MAIN, 1 },
  121. { P_SLEEP_CLK, 5 },
  122. { P_GPLL0_OUT_EVEN, 6 },
  123. { P_CORE_BI_PLL_TEST_SE, 7 },
  124. };
  125. static const struct clk_parent_data gcc_parents_1[] = {
  126. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  127. { .hw = &gpll0.clkr.hw },
  128. { .fw_name = "sleep_clk", .name = "sleep_clk" },
  129. { .hw = &gpll0_out_even.clkr.hw },
  130. { .fw_name = "core_bi_pll_test_se" },
  131. };
  132. static const struct parent_map gcc_parent_map_2[] = {
  133. { P_BI_TCXO, 0 },
  134. { P_SLEEP_CLK, 5 },
  135. { P_CORE_BI_PLL_TEST_SE, 7 },
  136. };
  137. static const struct clk_parent_data gcc_parents_2[] = {
  138. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  139. { .fw_name = "sleep_clk", .name = "sleep_clk" },
  140. { .fw_name = "core_bi_pll_test_se" },
  141. };
  142. static const struct parent_map gcc_parent_map_3[] = {
  143. { P_BI_TCXO, 0 },
  144. { P_GPLL0_OUT_MAIN, 1 },
  145. { P_CORE_BI_PLL_TEST_SE, 7 },
  146. };
  147. static const struct clk_parent_data gcc_parents_3[] = {
  148. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  149. { .hw = &gpll0.clkr.hw },
  150. { .fw_name = "core_bi_pll_test_se"},
  151. };
  152. static const struct parent_map gcc_parent_map_4[] = {
  153. { P_BI_TCXO, 0 },
  154. { P_CORE_BI_PLL_TEST_SE, 7 },
  155. };
  156. static const struct clk_parent_data gcc_parents_4[] = {
  157. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  158. { .fw_name = "core_bi_pll_test_se" },
  159. };
  160. static const struct parent_map gcc_parent_map_5[] = {
  161. { P_BI_TCXO, 0 },
  162. { P_GPLL0_OUT_MAIN, 1 },
  163. { P_GPLL7_OUT_MAIN, 3 },
  164. { P_GPLL0_OUT_EVEN, 6 },
  165. { P_CORE_BI_PLL_TEST_SE, 7 },
  166. };
  167. static const struct clk_parent_data gcc_parents_5[] = {
  168. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  169. { .hw = &gpll0.clkr.hw },
  170. { .hw = &gpll7.clkr.hw },
  171. { .hw = &gpll0_out_even.clkr.hw },
  172. { .fw_name = "core_bi_pll_test_se" },
  173. };
  174. static const struct parent_map gcc_parent_map_6[] = {
  175. { P_BI_TCXO, 0 },
  176. { P_GPLL0_OUT_MAIN, 1 },
  177. { P_GPLL9_OUT_MAIN, 2 },
  178. { P_GPLL0_OUT_EVEN, 6 },
  179. { P_CORE_BI_PLL_TEST_SE, 7 },
  180. };
  181. static const struct clk_parent_data gcc_parents_6[] = {
  182. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  183. { .hw = &gpll0.clkr.hw },
  184. { .hw = &gpll9.clkr.hw },
  185. { .hw = &gpll0_out_even.clkr.hw },
  186. { .fw_name = "core_bi_pll_test_se" },
  187. };
  188. static const struct parent_map gcc_parent_map_7[] = {
  189. { P_BI_TCXO, 0 },
  190. { P_GPLL0_OUT_MAIN, 1 },
  191. { P_AUD_REF_CLK, 2 },
  192. { P_GPLL0_OUT_EVEN, 6 },
  193. { P_CORE_BI_PLL_TEST_SE, 7 },
  194. };
  195. static const struct clk_parent_data gcc_parents_7[] = {
  196. { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
  197. { .hw = &gpll0.clkr.hw },
  198. { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
  199. { .hw = &gpll0_out_even.clkr.hw },
  200. { .fw_name = "core_bi_pll_test_se" },
  201. };
  202. static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
  203. F(19200000, P_BI_TCXO, 1, 0, 0),
  204. F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
  205. F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
  206. { }
  207. };
  208. static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
  209. .cmd_rcgr = 0x48014,
  210. .mnd_width = 0,
  211. .hid_width = 5,
  212. .parent_map = gcc_parent_map_0,
  213. .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
  214. .clkr.hw.init = &(struct clk_init_data){
  215. .name = "gcc_cpuss_ahb_clk_src",
  216. .parent_data = gcc_parents_0,
  217. .num_parents = 4,
  218. .flags = CLK_SET_RATE_PARENT,
  219. .ops = &clk_rcg2_ops,
  220. },
  221. };
  222. static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
  223. F(19200000, P_BI_TCXO, 1, 0, 0),
  224. F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
  225. F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
  226. F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
  227. { }
  228. };
  229. static struct clk_rcg2 gcc_emac_ptp_clk_src = {
  230. .cmd_rcgr = 0x6038,
  231. .mnd_width = 0,
  232. .hid_width = 5,
  233. .parent_map = gcc_parent_map_5,
  234. .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
  235. .clkr.hw.init = &(struct clk_init_data){
  236. .name = "gcc_emac_ptp_clk_src",
  237. .parent_data = gcc_parents_5,
  238. .num_parents = 5,
  239. .flags = CLK_SET_RATE_PARENT,
  240. .ops = &clk_rcg2_ops,
  241. },
  242. };
  243. static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
  244. F(2500000, P_BI_TCXO, 1, 25, 192),
  245. F(5000000, P_BI_TCXO, 1, 25, 96),
  246. F(19200000, P_BI_TCXO, 1, 0, 0),
  247. F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
  248. F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
  249. F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
  250. F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
  251. { }
  252. };
  253. static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
  254. .cmd_rcgr = 0x601c,
  255. .mnd_width = 8,
  256. .hid_width = 5,
  257. .parent_map = gcc_parent_map_5,
  258. .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
  259. .clkr.hw.init = &(struct clk_init_data){
  260. .name = "gcc_emac_rgmii_clk_src",
  261. .parent_data = gcc_parents_5,
  262. .num_parents = 5,
  263. .flags = CLK_SET_RATE_PARENT,
  264. .ops = &clk_rcg2_ops,
  265. },
  266. };
  267. static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
  268. F(19200000, P_BI_TCXO, 1, 0, 0),
  269. F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
  270. F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
  271. F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
  272. F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
  273. { }
  274. };
  275. static struct clk_rcg2 gcc_gp1_clk_src = {
  276. .cmd_rcgr = 0x64004,
  277. .mnd_width = 8,
  278. .hid_width = 5,
  279. .parent_map = gcc_parent_map_1,
  280. .freq_tbl = ftbl_gcc_gp1_clk_src,
  281. .clkr.hw.init = &(struct clk_init_data){
  282. .name = "gcc_gp1_clk_src",
  283. .parent_data = gcc_parents_1,
  284. .num_parents = 5,
  285. .flags = CLK_SET_RATE_PARENT,
  286. .ops = &clk_rcg2_ops,
  287. },
  288. };
  289. static struct clk_rcg2 gcc_gp2_clk_src = {
  290. .cmd_rcgr = 0x65004,
  291. .mnd_width = 8,
  292. .hid_width = 5,
  293. .parent_map = gcc_parent_map_1,
  294. .freq_tbl = ftbl_gcc_gp1_clk_src,
  295. .clkr.hw.init = &(struct clk_init_data){
  296. .name = "gcc_gp2_clk_src",
  297. .parent_data = gcc_parents_1,
  298. .num_parents = 5,
  299. .flags = CLK_SET_RATE_PARENT,
  300. .ops = &clk_rcg2_ops,
  301. },
  302. };
  303. static struct clk_rcg2 gcc_gp3_clk_src = {
  304. .cmd_rcgr = 0x66004,
  305. .mnd_width = 8,
  306. .hid_width = 5,
  307. .parent_map = gcc_parent_map_1,
  308. .freq_tbl = ftbl_gcc_gp1_clk_src,
  309. .clkr.hw.init = &(struct clk_init_data){
  310. .name = "gcc_gp3_clk_src",
  311. .parent_data = gcc_parents_1,
  312. .num_parents = 5,
  313. .flags = CLK_SET_RATE_PARENT,
  314. .ops = &clk_rcg2_ops,
  315. },
  316. };
  317. static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
  318. F(9600000, P_BI_TCXO, 2, 0, 0),
  319. F(19200000, P_BI_TCXO, 1, 0, 0),
  320. { }
  321. };
  322. static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
  323. .cmd_rcgr = 0x6b02c,
  324. .mnd_width = 16,
  325. .hid_width = 5,
  326. .parent_map = gcc_parent_map_2,
  327. .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
  328. .clkr.hw.init = &(struct clk_init_data){
  329. .name = "gcc_pcie_0_aux_clk_src",
  330. .parent_data = gcc_parents_2,
  331. .num_parents = 3,
  332. .flags = CLK_SET_RATE_PARENT,
  333. .ops = &clk_rcg2_ops,
  334. },
  335. };
  336. static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
  337. .cmd_rcgr = 0x8d02c,
  338. .mnd_width = 16,
  339. .hid_width = 5,
  340. .parent_map = gcc_parent_map_2,
  341. .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
  342. .clkr.hw.init = &(struct clk_init_data){
  343. .name = "gcc_pcie_1_aux_clk_src",
  344. .parent_data = gcc_parents_2,
  345. .num_parents = 3,
  346. .flags = CLK_SET_RATE_PARENT,
  347. .ops = &clk_rcg2_ops,
  348. },
  349. };
  350. static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
  351. F(19200000, P_BI_TCXO, 1, 0, 0),
  352. F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
  353. { }
  354. };
  355. static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
  356. .cmd_rcgr = 0x6f014,
  357. .mnd_width = 0,
  358. .hid_width = 5,
  359. .parent_map = gcc_parent_map_0,
  360. .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
  361. .clkr.hw.init = &(struct clk_init_data){
  362. .name = "gcc_pcie_phy_refgen_clk_src",
  363. .parent_data = gcc_parents_0,
  364. .num_parents = 4,
  365. .flags = CLK_SET_RATE_PARENT,
  366. .ops = &clk_rcg2_ops,
  367. },
  368. };
  369. static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
  370. F(9600000, P_BI_TCXO, 2, 0, 0),
  371. F(19200000, P_BI_TCXO, 1, 0, 0),
  372. F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
  373. { }
  374. };
  375. static struct clk_rcg2 gcc_pdm2_clk_src = {
  376. .cmd_rcgr = 0x33010,
  377. .mnd_width = 0,
  378. .hid_width = 5,
  379. .parent_map = gcc_parent_map_0,
  380. .freq_tbl = ftbl_gcc_pdm2_clk_src,
  381. .clkr.hw.init = &(struct clk_init_data){
  382. .name = "gcc_pdm2_clk_src",
  383. .parent_data = gcc_parents_0,
  384. .num_parents = 4,
  385. .flags = CLK_SET_RATE_PARENT,
  386. .ops = &clk_rcg2_ops,
  387. },
  388. };
  389. static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
  390. F(19200000, P_BI_TCXO, 1, 0, 0),
  391. F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
  392. F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
  393. F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
  394. { }
  395. };
  396. static struct clk_rcg2 gcc_qspi_core_clk_src = {
  397. .cmd_rcgr = 0x4b008,
  398. .mnd_width = 0,
  399. .hid_width = 5,
  400. .parent_map = gcc_parent_map_0,
  401. .freq_tbl = ftbl_gcc_qspi_core_clk_src,
  402. .clkr.hw.init = &(struct clk_init_data){
  403. .name = "gcc_qspi_core_clk_src",
  404. .parent_data = gcc_parents_0,
  405. .num_parents = 4,
  406. .flags = CLK_SET_RATE_PARENT,
  407. .ops = &clk_rcg2_ops,
  408. },
  409. };
  410. static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
  411. F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
  412. F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
  413. F(19200000, P_BI_TCXO, 1, 0, 0),
  414. F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
  415. F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
  416. F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
  417. F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
  418. F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
  419. F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
  420. F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
  421. F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
  422. F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
  423. F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
  424. F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
  425. F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
  426. { }
  427. };
  428. static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
  429. .cmd_rcgr = 0x17148,
  430. .mnd_width = 16,
  431. .hid_width = 5,
  432. .parent_map = gcc_parent_map_0,
  433. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  434. .clkr.hw.init = &(struct clk_init_data){
  435. .name = "gcc_qupv3_wrap0_s0_clk_src",
  436. .parent_data = gcc_parents_0,
  437. .num_parents = 4,
  438. .flags = CLK_SET_RATE_PARENT,
  439. .ops = &clk_rcg2_ops,
  440. },
  441. };
  442. static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
  443. .cmd_rcgr = 0x17278,
  444. .mnd_width = 16,
  445. .hid_width = 5,
  446. .parent_map = gcc_parent_map_0,
  447. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  448. .clkr.hw.init = &(struct clk_init_data){
  449. .name = "gcc_qupv3_wrap0_s1_clk_src",
  450. .parent_data = gcc_parents_0,
  451. .num_parents = 4,
  452. .flags = CLK_SET_RATE_PARENT,
  453. .ops = &clk_rcg2_ops,
  454. },
  455. };
  456. static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
  457. .cmd_rcgr = 0x173a8,
  458. .mnd_width = 16,
  459. .hid_width = 5,
  460. .parent_map = gcc_parent_map_0,
  461. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  462. .clkr.hw.init = &(struct clk_init_data){
  463. .name = "gcc_qupv3_wrap0_s2_clk_src",
  464. .parent_data = gcc_parents_0,
  465. .num_parents = 4,
  466. .flags = CLK_SET_RATE_PARENT,
  467. .ops = &clk_rcg2_ops,
  468. },
  469. };
  470. static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
  471. .cmd_rcgr = 0x174d8,
  472. .mnd_width = 16,
  473. .hid_width = 5,
  474. .parent_map = gcc_parent_map_0,
  475. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  476. .clkr.hw.init = &(struct clk_init_data){
  477. .name = "gcc_qupv3_wrap0_s3_clk_src",
  478. .parent_data = gcc_parents_0,
  479. .num_parents = 4,
  480. .flags = CLK_SET_RATE_PARENT,
  481. .ops = &clk_rcg2_ops,
  482. },
  483. };
  484. static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
  485. .cmd_rcgr = 0x17608,
  486. .mnd_width = 16,
  487. .hid_width = 5,
  488. .parent_map = gcc_parent_map_0,
  489. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  490. .clkr.hw.init = &(struct clk_init_data){
  491. .name = "gcc_qupv3_wrap0_s4_clk_src",
  492. .parent_data = gcc_parents_0,
  493. .num_parents = 4,
  494. .flags = CLK_SET_RATE_PARENT,
  495. .ops = &clk_rcg2_ops,
  496. },
  497. };
  498. static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
  499. .cmd_rcgr = 0x17738,
  500. .mnd_width = 16,
  501. .hid_width = 5,
  502. .parent_map = gcc_parent_map_0,
  503. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  504. .clkr.hw.init = &(struct clk_init_data){
  505. .name = "gcc_qupv3_wrap0_s5_clk_src",
  506. .parent_data = gcc_parents_0,
  507. .num_parents = 4,
  508. .flags = CLK_SET_RATE_PARENT,
  509. .ops = &clk_rcg2_ops,
  510. },
  511. };
  512. static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
  513. .cmd_rcgr = 0x17868,
  514. .mnd_width = 16,
  515. .hid_width = 5,
  516. .parent_map = gcc_parent_map_0,
  517. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  518. .clkr.hw.init = &(struct clk_init_data){
  519. .name = "gcc_qupv3_wrap0_s6_clk_src",
  520. .parent_data = gcc_parents_0,
  521. .num_parents = 4,
  522. .flags = CLK_SET_RATE_PARENT,
  523. .ops = &clk_rcg2_ops,
  524. },
  525. };
  526. static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
  527. .cmd_rcgr = 0x17998,
  528. .mnd_width = 16,
  529. .hid_width = 5,
  530. .parent_map = gcc_parent_map_0,
  531. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  532. .clkr.hw.init = &(struct clk_init_data){
  533. .name = "gcc_qupv3_wrap0_s7_clk_src",
  534. .parent_data = gcc_parents_0,
  535. .num_parents = 4,
  536. .flags = CLK_SET_RATE_PARENT,
  537. .ops = &clk_rcg2_ops,
  538. },
  539. };
  540. static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
  541. .cmd_rcgr = 0x18148,
  542. .mnd_width = 16,
  543. .hid_width = 5,
  544. .parent_map = gcc_parent_map_0,
  545. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  546. .clkr.hw.init = &(struct clk_init_data){
  547. .name = "gcc_qupv3_wrap1_s0_clk_src",
  548. .parent_data = gcc_parents_0,
  549. .num_parents = 4,
  550. .flags = CLK_SET_RATE_PARENT,
  551. .ops = &clk_rcg2_ops,
  552. },
  553. };
  554. static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
  555. .cmd_rcgr = 0x18278,
  556. .mnd_width = 16,
  557. .hid_width = 5,
  558. .parent_map = gcc_parent_map_0,
  559. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  560. .clkr.hw.init = &(struct clk_init_data){
  561. .name = "gcc_qupv3_wrap1_s1_clk_src",
  562. .parent_data = gcc_parents_0,
  563. .num_parents = 4,
  564. .flags = CLK_SET_RATE_PARENT,
  565. .ops = &clk_rcg2_ops,
  566. },
  567. };
  568. static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
  569. .cmd_rcgr = 0x183a8,
  570. .mnd_width = 16,
  571. .hid_width = 5,
  572. .parent_map = gcc_parent_map_0,
  573. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  574. .clkr.hw.init = &(struct clk_init_data){
  575. .name = "gcc_qupv3_wrap1_s2_clk_src",
  576. .parent_data = gcc_parents_0,
  577. .num_parents = 4,
  578. .flags = CLK_SET_RATE_PARENT,
  579. .ops = &clk_rcg2_ops,
  580. },
  581. };
  582. static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
  583. .cmd_rcgr = 0x184d8,
  584. .mnd_width = 16,
  585. .hid_width = 5,
  586. .parent_map = gcc_parent_map_0,
  587. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  588. .clkr.hw.init = &(struct clk_init_data){
  589. .name = "gcc_qupv3_wrap1_s3_clk_src",
  590. .parent_data = gcc_parents_0,
  591. .num_parents = 4,
  592. .flags = CLK_SET_RATE_PARENT,
  593. .ops = &clk_rcg2_ops,
  594. },
  595. };
  596. static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
  597. .cmd_rcgr = 0x18608,
  598. .mnd_width = 16,
  599. .hid_width = 5,
  600. .parent_map = gcc_parent_map_0,
  601. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  602. .clkr.hw.init = &(struct clk_init_data){
  603. .name = "gcc_qupv3_wrap1_s4_clk_src",
  604. .parent_data = gcc_parents_0,
  605. .num_parents = 4,
  606. .flags = CLK_SET_RATE_PARENT,
  607. .ops = &clk_rcg2_ops,
  608. },
  609. };
  610. static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
  611. .cmd_rcgr = 0x18738,
  612. .mnd_width = 16,
  613. .hid_width = 5,
  614. .parent_map = gcc_parent_map_0,
  615. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  616. .clkr.hw.init = &(struct clk_init_data){
  617. .name = "gcc_qupv3_wrap1_s5_clk_src",
  618. .parent_data = gcc_parents_0,
  619. .num_parents = 4,
  620. .flags = CLK_SET_RATE_PARENT,
  621. .ops = &clk_rcg2_ops,
  622. },
  623. };
  624. static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
  625. .cmd_rcgr = 0x1e148,
  626. .mnd_width = 16,
  627. .hid_width = 5,
  628. .parent_map = gcc_parent_map_0,
  629. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  630. .clkr.hw.init = &(struct clk_init_data){
  631. .name = "gcc_qupv3_wrap2_s0_clk_src",
  632. .parent_data = gcc_parents_0,
  633. .num_parents = 4,
  634. .flags = CLK_SET_RATE_PARENT,
  635. .ops = &clk_rcg2_ops,
  636. },
  637. };
  638. static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
  639. .cmd_rcgr = 0x1e278,
  640. .mnd_width = 16,
  641. .hid_width = 5,
  642. .parent_map = gcc_parent_map_0,
  643. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  644. .clkr.hw.init = &(struct clk_init_data){
  645. .name = "gcc_qupv3_wrap2_s1_clk_src",
  646. .parent_data = gcc_parents_0,
  647. .num_parents = 4,
  648. .flags = CLK_SET_RATE_PARENT,
  649. .ops = &clk_rcg2_ops,
  650. },
  651. };
  652. static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
  653. .cmd_rcgr = 0x1e3a8,
  654. .mnd_width = 16,
  655. .hid_width = 5,
  656. .parent_map = gcc_parent_map_0,
  657. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  658. .clkr.hw.init = &(struct clk_init_data){
  659. .name = "gcc_qupv3_wrap2_s2_clk_src",
  660. .parent_data = gcc_parents_0,
  661. .num_parents = 4,
  662. .flags = CLK_SET_RATE_PARENT,
  663. .ops = &clk_rcg2_ops,
  664. },
  665. };
  666. static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
  667. .cmd_rcgr = 0x1e4d8,
  668. .mnd_width = 16,
  669. .hid_width = 5,
  670. .parent_map = gcc_parent_map_0,
  671. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  672. .clkr.hw.init = &(struct clk_init_data){
  673. .name = "gcc_qupv3_wrap2_s3_clk_src",
  674. .parent_data = gcc_parents_0,
  675. .num_parents = 4,
  676. .flags = CLK_SET_RATE_PARENT,
  677. .ops = &clk_rcg2_ops,
  678. },
  679. };
  680. static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
  681. .cmd_rcgr = 0x1e608,
  682. .mnd_width = 16,
  683. .hid_width = 5,
  684. .parent_map = gcc_parent_map_0,
  685. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  686. .clkr.hw.init = &(struct clk_init_data){
  687. .name = "gcc_qupv3_wrap2_s4_clk_src",
  688. .parent_data = gcc_parents_0,
  689. .num_parents = 4,
  690. .flags = CLK_SET_RATE_PARENT,
  691. .ops = &clk_rcg2_ops,
  692. },
  693. };
  694. static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
  695. .cmd_rcgr = 0x1e738,
  696. .mnd_width = 16,
  697. .hid_width = 5,
  698. .parent_map = gcc_parent_map_0,
  699. .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
  700. .clkr.hw.init = &(struct clk_init_data){
  701. .name = "gcc_qupv3_wrap2_s5_clk_src",
  702. .parent_data = gcc_parents_0,
  703. .num_parents = 4,
  704. .flags = CLK_SET_RATE_PARENT,
  705. .ops = &clk_rcg2_ops,
  706. },
  707. };
  708. static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
  709. F(400000, P_BI_TCXO, 12, 1, 4),
  710. F(9600000, P_BI_TCXO, 2, 0, 0),
  711. F(19200000, P_BI_TCXO, 1, 0, 0),
  712. F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
  713. F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
  714. F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
  715. F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
  716. { }
  717. };
  718. static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
  719. .cmd_rcgr = 0x1400c,
  720. .mnd_width = 8,
  721. .hid_width = 5,
  722. .parent_map = gcc_parent_map_6,
  723. .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
  724. .clkr.hw.init = &(struct clk_init_data){
  725. .name = "gcc_sdcc2_apps_clk_src",
  726. .parent_data = gcc_parents_6,
  727. .num_parents = 5,
  728. .flags = CLK_SET_RATE_PARENT,
  729. .ops = &clk_rcg2_floor_ops,
  730. },
  731. };
  732. static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
  733. F(400000, P_BI_TCXO, 12, 1, 4),
  734. F(9600000, P_BI_TCXO, 2, 0, 0),
  735. F(19200000, P_BI_TCXO, 1, 0, 0),
  736. F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
  737. F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
  738. F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
  739. { }
  740. };
  741. static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
  742. .cmd_rcgr = 0x1600c,
  743. .mnd_width = 8,
  744. .hid_width = 5,
  745. .parent_map = gcc_parent_map_3,
  746. .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
  747. .clkr.hw.init = &(struct clk_init_data){
  748. .name = "gcc_sdcc4_apps_clk_src",
  749. .parent_data = gcc_parents_3,
  750. .num_parents = 3,
  751. .flags = CLK_SET_RATE_PARENT,
  752. .ops = &clk_rcg2_floor_ops,
  753. },
  754. };
  755. static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
  756. F(105495, P_BI_TCXO, 2, 1, 91),
  757. { }
  758. };
  759. static struct clk_rcg2 gcc_tsif_ref_clk_src = {
  760. .cmd_rcgr = 0x36010,
  761. .mnd_width = 8,
  762. .hid_width = 5,
  763. .parent_map = gcc_parent_map_7,
  764. .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
  765. .clkr.hw.init = &(struct clk_init_data){
  766. .name = "gcc_tsif_ref_clk_src",
  767. .parent_data = gcc_parents_7,
  768. .num_parents = 5,
  769. .flags = CLK_SET_RATE_PARENT,
  770. .ops = &clk_rcg2_ops,
  771. },
  772. };
  773. static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
  774. F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
  775. F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
  776. F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
  777. F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
  778. F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
  779. { }
  780. };
  781. static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
  782. .cmd_rcgr = 0x75020,
  783. .mnd_width = 8,
  784. .hid_width = 5,
  785. .parent_map = gcc_parent_map_0,
  786. .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
  787. .clkr.hw.init = &(struct clk_init_data){
  788. .name = "gcc_ufs_card_axi_clk_src",
  789. .parent_data = gcc_parents_0,
  790. .num_parents = 4,
  791. .flags = CLK_SET_RATE_PARENT,
  792. .ops = &clk_rcg2_ops,
  793. },
  794. };
  795. static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
  796. F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
  797. F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
  798. F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
  799. F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
  800. { }
  801. };
  802. static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
  803. .cmd_rcgr = 0x75060,
  804. .mnd_width = 0,
  805. .hid_width = 5,
  806. .parent_map = gcc_parent_map_0,
  807. .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
  808. .clkr.hw.init = &(struct clk_init_data){
  809. .name = "gcc_ufs_card_ice_core_clk_src",
  810. .parent_data = gcc_parents_0,
  811. .num_parents = 4,
  812. .flags = CLK_SET_RATE_PARENT,
  813. .ops = &clk_rcg2_ops,
  814. },
  815. };
  816. static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
  817. F(19200000, P_BI_TCXO, 1, 0, 0),
  818. { }
  819. };
  820. static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
  821. .cmd_rcgr = 0x75094,
  822. .mnd_width = 0,
  823. .hid_width = 5,
  824. .parent_map = gcc_parent_map_4,
  825. .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
  826. .clkr.hw.init = &(struct clk_init_data){
  827. .name = "gcc_ufs_card_phy_aux_clk_src",
  828. .parent_data = gcc_parents_4,
  829. .num_parents = 2,
  830. .flags = CLK_SET_RATE_PARENT,
  831. .ops = &clk_rcg2_ops,
  832. },
  833. };
  834. static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
  835. F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
  836. F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
  837. F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
  838. { }
  839. };
  840. static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
  841. .cmd_rcgr = 0x75078,
  842. .mnd_width = 0,
  843. .hid_width = 5,
  844. .parent_map = gcc_parent_map_0,
  845. .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
  846. .clkr.hw.init = &(struct clk_init_data){
  847. .name = "gcc_ufs_card_unipro_core_clk_src",
  848. .parent_data = gcc_parents_0,
  849. .num_parents = 4,
  850. .flags = CLK_SET_RATE_PARENT,
  851. .ops = &clk_rcg2_ops,
  852. },
  853. };
  854. static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
  855. F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
  856. F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
  857. F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
  858. F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
  859. F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
  860. { }
  861. };
  862. static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
  863. .cmd_rcgr = 0x77020,
  864. .mnd_width = 8,
  865. .hid_width = 5,
  866. .parent_map = gcc_parent_map_0,
  867. .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
  868. .clkr.hw.init = &(struct clk_init_data){
  869. .name = "gcc_ufs_phy_axi_clk_src",
  870. .parent_data = gcc_parents_0,
  871. .num_parents = 4,
  872. .flags = CLK_SET_RATE_PARENT,
  873. .ops = &clk_rcg2_ops,
  874. },
  875. };
  876. static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
  877. .cmd_rcgr = 0x77060,
  878. .mnd_width = 0,
  879. .hid_width = 5,
  880. .parent_map = gcc_parent_map_0,
  881. .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
  882. .clkr.hw.init = &(struct clk_init_data){
  883. .name = "gcc_ufs_phy_ice_core_clk_src",
  884. .parent_data = gcc_parents_0,
  885. .num_parents = 4,
  886. .flags = CLK_SET_RATE_PARENT,
  887. .ops = &clk_rcg2_ops,
  888. },
  889. };
  890. static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
  891. .cmd_rcgr = 0x77094,
  892. .mnd_width = 0,
  893. .hid_width = 5,
  894. .parent_map = gcc_parent_map_4,
  895. .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
  896. .clkr.hw.init = &(struct clk_init_data){
  897. .name = "gcc_ufs_phy_phy_aux_clk_src",
  898. .parent_data = gcc_parents_4,
  899. .num_parents = 2,
  900. .flags = CLK_SET_RATE_PARENT,
  901. .ops = &clk_rcg2_ops,
  902. },
  903. };
  904. static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
  905. .cmd_rcgr = 0x77078,
  906. .mnd_width = 0,
  907. .hid_width = 5,
  908. .parent_map = gcc_parent_map_0,
  909. .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
  910. .clkr.hw.init = &(struct clk_init_data){
  911. .name = "gcc_ufs_phy_unipro_core_clk_src",
  912. .parent_data = gcc_parents_0,
  913. .num_parents = 4,
  914. .flags = CLK_SET_RATE_PARENT,
  915. .ops = &clk_rcg2_ops,
  916. },
  917. };
  918. static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
  919. F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
  920. F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
  921. F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
  922. F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
  923. F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
  924. { }
  925. };
  926. static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
  927. .cmd_rcgr = 0xf01c,
  928. .mnd_width = 8,
  929. .hid_width = 5,
  930. .parent_map = gcc_parent_map_0,
  931. .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
  932. .clkr.hw.init = &(struct clk_init_data){
  933. .name = "gcc_usb30_prim_master_clk_src",
  934. .parent_data = gcc_parents_0,
  935. .num_parents = 4,
  936. .flags = CLK_SET_RATE_PARENT,
  937. .ops = &clk_rcg2_ops,
  938. },
  939. };
  940. static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
  941. F(19200000, P_BI_TCXO, 1, 0, 0),
  942. F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
  943. F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
  944. { }
  945. };
  946. static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
  947. .cmd_rcgr = 0xf034,
  948. .mnd_width = 0,
  949. .hid_width = 5,
  950. .parent_map = gcc_parent_map_0,
  951. .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
  952. .clkr.hw.init = &(struct clk_init_data){
  953. .name = "gcc_usb30_prim_mock_utmi_clk_src",
  954. .parent_data = gcc_parents_0,
  955. .num_parents = 4,
  956. .flags = CLK_SET_RATE_PARENT,
  957. .ops = &clk_rcg2_ops,
  958. },
  959. };
  960. static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
  961. .cmd_rcgr = 0x1001c,
  962. .mnd_width = 8,
  963. .hid_width = 5,
  964. .parent_map = gcc_parent_map_0,
  965. .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
  966. .clkr.hw.init = &(struct clk_init_data){
  967. .name = "gcc_usb30_sec_master_clk_src",
  968. .parent_data = gcc_parents_0,
  969. .num_parents = 4,
  970. .flags = CLK_SET_RATE_PARENT,
  971. .ops = &clk_rcg2_ops,
  972. },
  973. };
  974. static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
  975. .cmd_rcgr = 0x10034,
  976. .mnd_width = 0,
  977. .hid_width = 5,
  978. .parent_map = gcc_parent_map_0,
  979. .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
  980. .clkr.hw.init = &(struct clk_init_data){
  981. .name = "gcc_usb30_sec_mock_utmi_clk_src",
  982. .parent_data = gcc_parents_0,
  983. .num_parents = 4,
  984. .flags = CLK_SET_RATE_PARENT,
  985. .ops = &clk_rcg2_ops,
  986. },
  987. };
  988. static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
  989. .cmd_rcgr = 0xf060,
  990. .mnd_width = 0,
  991. .hid_width = 5,
  992. .parent_map = gcc_parent_map_2,
  993. .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
  994. .clkr.hw.init = &(struct clk_init_data){
  995. .name = "gcc_usb3_prim_phy_aux_clk_src",
  996. .parent_data = gcc_parents_2,
  997. .num_parents = 3,
  998. .flags = CLK_SET_RATE_PARENT,
  999. .ops = &clk_rcg2_ops,
  1000. },
  1001. };
  1002. static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
  1003. .cmd_rcgr = 0x10060,
  1004. .mnd_width = 0,
  1005. .hid_width = 5,
  1006. .parent_map = gcc_parent_map_2,
  1007. .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
  1008. .clkr.hw.init = &(struct clk_init_data){
  1009. .name = "gcc_usb3_sec_phy_aux_clk_src",
  1010. .parent_data = gcc_parents_2,
  1011. .num_parents = 3,
  1012. .flags = CLK_SET_RATE_PARENT,
  1013. .ops = &clk_rcg2_ops,
  1014. },
  1015. };
  1016. static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
  1017. .halt_reg = 0x90018,
  1018. .halt_check = BRANCH_HALT,
  1019. .clkr = {
  1020. .enable_reg = 0x90018,
  1021. .enable_mask = BIT(0),
  1022. .hw.init = &(struct clk_init_data){
  1023. .name = "gcc_aggre_noc_pcie_tbu_clk",
  1024. .ops = &clk_branch2_ops,
  1025. },
  1026. },
  1027. };
  1028. static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
  1029. .halt_reg = 0x750c0,
  1030. .halt_check = BRANCH_HALT,
  1031. .hwcg_reg = 0x750c0,
  1032. .hwcg_bit = 1,
  1033. .clkr = {
  1034. .enable_reg = 0x750c0,
  1035. .enable_mask = BIT(0),
  1036. .hw.init = &(struct clk_init_data){
  1037. .name = "gcc_aggre_ufs_card_axi_clk",
  1038. .parent_hws = (const struct clk_hw *[]){
  1039. &gcc_ufs_card_axi_clk_src.clkr.hw },
  1040. .num_parents = 1,
  1041. .flags = CLK_SET_RATE_PARENT,
  1042. .ops = &clk_branch2_ops,
  1043. },
  1044. },
  1045. };
  1046. static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
  1047. .halt_reg = 0x750c0,
  1048. .halt_check = BRANCH_HALT,
  1049. .hwcg_reg = 0x750c0,
  1050. .hwcg_bit = 1,
  1051. .clkr = {
  1052. .enable_reg = 0x750c0,
  1053. .enable_mask = BIT(1),
  1054. .hw.init = &(struct clk_init_data){
  1055. .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
  1056. .parent_hws = (const struct clk_hw *[]){
  1057. &gcc_aggre_ufs_card_axi_clk.clkr.hw },
  1058. .num_parents = 1,
  1059. .flags = CLK_SET_RATE_PARENT,
  1060. .ops = &clk_branch_simple_ops,
  1061. },
  1062. },
  1063. };
  1064. static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
  1065. .halt_reg = 0x770c0,
  1066. .halt_check = BRANCH_HALT,
  1067. .hwcg_reg = 0x770c0,
  1068. .hwcg_bit = 1,
  1069. .clkr = {
  1070. .enable_reg = 0x770c0,
  1071. .enable_mask = BIT(0),
  1072. .hw.init = &(struct clk_init_data){
  1073. .name = "gcc_aggre_ufs_phy_axi_clk",
  1074. .parent_hws = (const struct clk_hw *[]){
  1075. &gcc_ufs_phy_axi_clk_src.clkr.hw },
  1076. .num_parents = 1,
  1077. .flags = CLK_SET_RATE_PARENT,
  1078. .ops = &clk_branch2_ops,
  1079. },
  1080. },
  1081. };
  1082. static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
  1083. .halt_reg = 0x770c0,
  1084. .halt_check = BRANCH_HALT,
  1085. .hwcg_reg = 0x770c0,
  1086. .hwcg_bit = 1,
  1087. .clkr = {
  1088. .enable_reg = 0x770c0,
  1089. .enable_mask = BIT(1),
  1090. .hw.init = &(struct clk_init_data){
  1091. .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
  1092. .parent_hws = (const struct clk_hw *[]){
  1093. &gcc_aggre_ufs_phy_axi_clk.clkr.hw },
  1094. .num_parents = 1,
  1095. .flags = CLK_SET_RATE_PARENT,
  1096. .ops = &clk_branch_simple_ops,
  1097. },
  1098. },
  1099. };
  1100. static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
  1101. .halt_reg = 0xf07c,
  1102. .halt_check = BRANCH_HALT,
  1103. .clkr = {
  1104. .enable_reg = 0xf07c,
  1105. .enable_mask = BIT(0),
  1106. .hw.init = &(struct clk_init_data){
  1107. .name = "gcc_aggre_usb3_prim_axi_clk",
  1108. .parent_hws = (const struct clk_hw *[]){
  1109. &gcc_usb30_prim_master_clk_src.clkr.hw },
  1110. .num_parents = 1,
  1111. .flags = CLK_SET_RATE_PARENT,
  1112. .ops = &clk_branch2_ops,
  1113. },
  1114. },
  1115. };
  1116. static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
  1117. .halt_reg = 0x1007c,
  1118. .halt_check = BRANCH_HALT,
  1119. .clkr = {
  1120. .enable_reg = 0x1007c,
  1121. .enable_mask = BIT(0),
  1122. .hw.init = &(struct clk_init_data){
  1123. .name = "gcc_aggre_usb3_sec_axi_clk",
  1124. .parent_hws = (const struct clk_hw *[]){
  1125. &gcc_usb30_sec_master_clk_src.clkr.hw },
  1126. .num_parents = 1,
  1127. .flags = CLK_SET_RATE_PARENT,
  1128. .ops = &clk_branch2_ops,
  1129. },
  1130. },
  1131. };
  1132. static struct clk_branch gcc_boot_rom_ahb_clk = {
  1133. .halt_reg = 0x38004,
  1134. .halt_check = BRANCH_HALT_VOTED,
  1135. .hwcg_reg = 0x38004,
  1136. .hwcg_bit = 1,
  1137. .clkr = {
  1138. .enable_reg = 0x52004,
  1139. .enable_mask = BIT(10),
  1140. .hw.init = &(struct clk_init_data){
  1141. .name = "gcc_boot_rom_ahb_clk",
  1142. .ops = &clk_branch2_ops,
  1143. },
  1144. },
  1145. };
  1146. /*
  1147. * Clock ON depends on external parent 'config noc', so cant poll
  1148. * delay and also mark as crtitical for camss boot
  1149. */
  1150. static struct clk_branch gcc_camera_ahb_clk = {
  1151. .halt_reg = 0xb008,
  1152. .halt_check = BRANCH_HALT_DELAY,
  1153. .hwcg_reg = 0xb008,
  1154. .hwcg_bit = 1,
  1155. .clkr = {
  1156. .enable_reg = 0xb008,
  1157. .enable_mask = BIT(0),
  1158. .hw.init = &(struct clk_init_data){
  1159. .name = "gcc_camera_ahb_clk",
  1160. .flags = CLK_IS_CRITICAL,
  1161. .ops = &clk_branch2_ops,
  1162. },
  1163. },
  1164. };
  1165. static struct clk_branch gcc_camera_hf_axi_clk = {
  1166. .halt_reg = 0xb030,
  1167. .halt_check = BRANCH_HALT,
  1168. .clkr = {
  1169. .enable_reg = 0xb030,
  1170. .enable_mask = BIT(0),
  1171. .hw.init = &(struct clk_init_data){
  1172. .name = "gcc_camera_hf_axi_clk",
  1173. .ops = &clk_branch2_ops,
  1174. },
  1175. },
  1176. };
  1177. static struct clk_branch gcc_camera_sf_axi_clk = {
  1178. .halt_reg = 0xb034,
  1179. .halt_check = BRANCH_HALT,
  1180. .clkr = {
  1181. .enable_reg = 0xb034,
  1182. .enable_mask = BIT(0),
  1183. .hw.init = &(struct clk_init_data){
  1184. .name = "gcc_camera_sf_axi_clk",
  1185. .ops = &clk_branch2_ops,
  1186. },
  1187. },
  1188. };
  1189. /* XO critical input to camss, so no need to poll */
  1190. static struct clk_branch gcc_camera_xo_clk = {
  1191. .halt_reg = 0xb044,
  1192. .halt_check = BRANCH_HALT_DELAY,
  1193. .clkr = {
  1194. .enable_reg = 0xb044,
  1195. .enable_mask = BIT(0),
  1196. .hw.init = &(struct clk_init_data){
  1197. .name = "gcc_camera_xo_clk",
  1198. .flags = CLK_IS_CRITICAL,
  1199. .ops = &clk_branch2_ops,
  1200. },
  1201. },
  1202. };
  1203. static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
  1204. .halt_reg = 0xf078,
  1205. .halt_check = BRANCH_HALT,
  1206. .clkr = {
  1207. .enable_reg = 0xf078,
  1208. .enable_mask = BIT(0),
  1209. .hw.init = &(struct clk_init_data){
  1210. .name = "gcc_cfg_noc_usb3_prim_axi_clk",
  1211. .parent_hws = (const struct clk_hw *[]){
  1212. &gcc_usb30_prim_master_clk_src.clkr.hw },
  1213. .num_parents = 1,
  1214. .flags = CLK_SET_RATE_PARENT,
  1215. .ops = &clk_branch2_ops,
  1216. },
  1217. },
  1218. };
  1219. static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
  1220. .halt_reg = 0x10078,
  1221. .halt_check = BRANCH_HALT,
  1222. .clkr = {
  1223. .enable_reg = 0x10078,
  1224. .enable_mask = BIT(0),
  1225. .hw.init = &(struct clk_init_data){
  1226. .name = "gcc_cfg_noc_usb3_sec_axi_clk",
  1227. .parent_hws = (const struct clk_hw *[]){
  1228. &gcc_usb30_sec_master_clk_src.clkr.hw },
  1229. .num_parents = 1,
  1230. .flags = CLK_SET_RATE_PARENT,
  1231. .ops = &clk_branch2_ops,
  1232. },
  1233. },
  1234. };
  1235. static struct clk_branch gcc_cpuss_ahb_clk = {
  1236. .halt_reg = 0x48000,
  1237. .halt_check = BRANCH_HALT_VOTED,
  1238. .clkr = {
  1239. .enable_reg = 0x52004,
  1240. .enable_mask = BIT(21),
  1241. .hw.init = &(struct clk_init_data){
  1242. .name = "gcc_cpuss_ahb_clk",
  1243. .parent_hws = (const struct clk_hw *[]){
  1244. &gcc_cpuss_ahb_clk_src.clkr.hw },
  1245. .num_parents = 1,
  1246. /* required for cpuss */
  1247. .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
  1248. .ops = &clk_branch2_ops,
  1249. },
  1250. },
  1251. };
  1252. static struct clk_branch gcc_cpuss_dvm_bus_clk = {
  1253. .halt_reg = 0x48190,
  1254. .halt_check = BRANCH_HALT,
  1255. .clkr = {
  1256. .enable_reg = 0x48190,
  1257. .enable_mask = BIT(0),
  1258. .hw.init = &(struct clk_init_data){
  1259. .name = "gcc_cpuss_dvm_bus_clk",
  1260. /* required for cpuss */
  1261. .flags = CLK_IS_CRITICAL,
  1262. .ops = &clk_branch2_ops,
  1263. },
  1264. },
  1265. };
  1266. static struct clk_branch gcc_cpuss_gnoc_clk = {
  1267. .halt_reg = 0x48004,
  1268. .halt_check = BRANCH_HALT_VOTED,
  1269. .hwcg_reg = 0x48004,
  1270. .hwcg_bit = 1,
  1271. .clkr = {
  1272. .enable_reg = 0x52004,
  1273. .enable_mask = BIT(22),
  1274. .hw.init = &(struct clk_init_data){
  1275. .name = "gcc_cpuss_gnoc_clk",
  1276. /* required for cpuss */
  1277. .flags = CLK_IS_CRITICAL,
  1278. .ops = &clk_branch2_ops,
  1279. },
  1280. },
  1281. };
  1282. static struct clk_branch gcc_cpuss_rbcpr_clk = {
  1283. .halt_reg = 0x48008,
  1284. .halt_check = BRANCH_HALT,
  1285. .clkr = {
  1286. .enable_reg = 0x48008,
  1287. .enable_mask = BIT(0),
  1288. .hw.init = &(struct clk_init_data){
  1289. .name = "gcc_cpuss_rbcpr_clk",
  1290. .ops = &clk_branch2_ops,
  1291. },
  1292. },
  1293. };
  1294. static struct clk_branch gcc_ddrss_gpu_axi_clk = {
  1295. .halt_reg = 0x71154,
  1296. .halt_check = BRANCH_VOTED,
  1297. .clkr = {
  1298. .enable_reg = 0x71154,
  1299. .enable_mask = BIT(0),
  1300. .hw.init = &(struct clk_init_data){
  1301. .name = "gcc_ddrss_gpu_axi_clk",
  1302. .ops = &clk_branch2_ops,
  1303. },
  1304. },
  1305. };
  1306. /*
  1307. * Clock ON depends on external parent 'config noc', so cant poll
  1308. * delay and also mark as crtitical for disp boot
  1309. */
  1310. static struct clk_branch gcc_disp_ahb_clk = {
  1311. .halt_reg = 0xb00c,
  1312. .halt_check = BRANCH_HALT_DELAY,
  1313. .hwcg_reg = 0xb00c,
  1314. .hwcg_bit = 1,
  1315. .clkr = {
  1316. .enable_reg = 0xb00c,
  1317. .enable_mask = BIT(0),
  1318. .hw.init = &(struct clk_init_data){
  1319. .name = "gcc_disp_ahb_clk",
  1320. .flags = CLK_IS_CRITICAL,
  1321. .ops = &clk_branch2_ops,
  1322. },
  1323. },
  1324. };
  1325. static struct clk_branch gcc_disp_hf_axi_clk = {
  1326. .halt_reg = 0xb038,
  1327. .halt_check = BRANCH_HALT,
  1328. .clkr = {
  1329. .enable_reg = 0xb038,
  1330. .enable_mask = BIT(0),
  1331. .hw.init = &(struct clk_init_data){
  1332. .name = "gcc_disp_hf_axi_clk",
  1333. .ops = &clk_branch2_ops,
  1334. },
  1335. },
  1336. };
  1337. static struct clk_branch gcc_disp_sf_axi_clk = {
  1338. .halt_reg = 0xb03c,
  1339. .halt_check = BRANCH_HALT,
  1340. .clkr = {
  1341. .enable_reg = 0xb03c,
  1342. .enable_mask = BIT(0),
  1343. .hw.init = &(struct clk_init_data){
  1344. .name = "gcc_disp_sf_axi_clk",
  1345. .ops = &clk_branch2_ops,
  1346. },
  1347. },
  1348. };
  1349. /* XO critical input to disp, so no need to poll */
  1350. static struct clk_branch gcc_disp_xo_clk = {
  1351. .halt_reg = 0xb048,
  1352. .halt_check = BRANCH_HALT_DELAY,
  1353. .clkr = {
  1354. .enable_reg = 0xb048,
  1355. .enable_mask = BIT(0),
  1356. .hw.init = &(struct clk_init_data){
  1357. .name = "gcc_disp_xo_clk",
  1358. .flags = CLK_IS_CRITICAL,
  1359. .ops = &clk_branch2_ops,
  1360. },
  1361. },
  1362. };
  1363. static struct clk_branch gcc_emac_axi_clk = {
  1364. .halt_reg = 0x6010,
  1365. .halt_check = BRANCH_HALT,
  1366. .clkr = {
  1367. .enable_reg = 0x6010,
  1368. .enable_mask = BIT(0),
  1369. .hw.init = &(struct clk_init_data){
  1370. .name = "gcc_emac_axi_clk",
  1371. .ops = &clk_branch2_ops,
  1372. },
  1373. },
  1374. };
  1375. static struct clk_branch gcc_emac_ptp_clk = {
  1376. .halt_reg = 0x6034,
  1377. .halt_check = BRANCH_HALT,
  1378. .clkr = {
  1379. .enable_reg = 0x6034,
  1380. .enable_mask = BIT(0),
  1381. .hw.init = &(struct clk_init_data){
  1382. .name = "gcc_emac_ptp_clk",
  1383. .parent_hws = (const struct clk_hw *[]){
  1384. &gcc_emac_ptp_clk_src.clkr.hw },
  1385. .num_parents = 1,
  1386. .flags = CLK_SET_RATE_PARENT,
  1387. .ops = &clk_branch2_ops,
  1388. },
  1389. },
  1390. };
  1391. static struct clk_branch gcc_emac_rgmii_clk = {
  1392. .halt_reg = 0x6018,
  1393. .halt_check = BRANCH_HALT,
  1394. .clkr = {
  1395. .enable_reg = 0x6018,
  1396. .enable_mask = BIT(0),
  1397. .hw.init = &(struct clk_init_data){
  1398. .name = "gcc_emac_rgmii_clk",
  1399. .parent_hws = (const struct clk_hw *[]){
  1400. &gcc_emac_rgmii_clk_src.clkr.hw },
  1401. .num_parents = 1,
  1402. .flags = CLK_SET_RATE_PARENT,
  1403. .ops = &clk_branch2_ops,
  1404. },
  1405. },
  1406. };
  1407. static struct clk_branch gcc_emac_slv_ahb_clk = {
  1408. .halt_reg = 0x6014,
  1409. .halt_check = BRANCH_HALT,
  1410. .hwcg_reg = 0x6014,
  1411. .hwcg_bit = 1,
  1412. .clkr = {
  1413. .enable_reg = 0x6014,
  1414. .enable_mask = BIT(0),
  1415. .hw.init = &(struct clk_init_data){
  1416. .name = "gcc_emac_slv_ahb_clk",
  1417. .ops = &clk_branch2_ops,
  1418. },
  1419. },
  1420. };
  1421. static struct clk_branch gcc_gp1_clk = {
  1422. .halt_reg = 0x64000,
  1423. .halt_check = BRANCH_HALT,
  1424. .clkr = {
  1425. .enable_reg = 0x64000,
  1426. .enable_mask = BIT(0),
  1427. .hw.init = &(struct clk_init_data){
  1428. .name = "gcc_gp1_clk",
  1429. .parent_hws = (const struct clk_hw *[]){
  1430. &gcc_gp1_clk_src.clkr.hw },
  1431. .num_parents = 1,
  1432. .flags = CLK_SET_RATE_PARENT,
  1433. .ops = &clk_branch2_ops,
  1434. },
  1435. },
  1436. };
  1437. static struct clk_branch gcc_gp2_clk = {
  1438. .halt_reg = 0x65000,
  1439. .halt_check = BRANCH_HALT,
  1440. .clkr = {
  1441. .enable_reg = 0x65000,
  1442. .enable_mask = BIT(0),
  1443. .hw.init = &(struct clk_init_data){
  1444. .name = "gcc_gp2_clk",
  1445. .parent_hws = (const struct clk_hw *[]){
  1446. &gcc_gp2_clk_src.clkr.hw },
  1447. .num_parents = 1,
  1448. .flags = CLK_SET_RATE_PARENT,
  1449. .ops = &clk_branch2_ops,
  1450. },
  1451. },
  1452. };
  1453. static struct clk_branch gcc_gp3_clk = {
  1454. .halt_reg = 0x66000,
  1455. .halt_check = BRANCH_HALT,
  1456. .clkr = {
  1457. .enable_reg = 0x66000,
  1458. .enable_mask = BIT(0),
  1459. .hw.init = &(struct clk_init_data){
  1460. .name = "gcc_gp3_clk",
  1461. .parent_hws = (const struct clk_hw *[]){
  1462. &gcc_gp3_clk_src.clkr.hw },
  1463. .num_parents = 1,
  1464. .flags = CLK_SET_RATE_PARENT,
  1465. .ops = &clk_branch2_ops,
  1466. },
  1467. },
  1468. };
  1469. static struct clk_branch gcc_gpu_cfg_ahb_clk = {
  1470. .halt_reg = 0x71004,
  1471. .halt_check = BRANCH_HALT,
  1472. .hwcg_reg = 0x71004,
  1473. .hwcg_bit = 1,
  1474. .clkr = {
  1475. .enable_reg = 0x71004,
  1476. .enable_mask = BIT(0),
  1477. .hw.init = &(struct clk_init_data){
  1478. .name = "gcc_gpu_cfg_ahb_clk",
  1479. /* required for gpu */
  1480. .flags = CLK_IS_CRITICAL,
  1481. .ops = &clk_branch2_ops,
  1482. },
  1483. },
  1484. };
  1485. static struct clk_branch gcc_gpu_gpll0_clk_src = {
  1486. .halt_check = BRANCH_HALT_SKIP,
  1487. .clkr = {
  1488. .enable_reg = 0x52004,
  1489. .enable_mask = BIT(15),
  1490. .hw.init = &(struct clk_init_data){
  1491. .name = "gcc_gpu_gpll0_clk_src",
  1492. .parent_hws = (const struct clk_hw *[]){
  1493. &gpll0.clkr.hw },
  1494. .num_parents = 1,
  1495. .flags = CLK_SET_RATE_PARENT,
  1496. .ops = &clk_branch2_ops,
  1497. },
  1498. },
  1499. };
  1500. static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
  1501. .halt_check = BRANCH_HALT_SKIP,
  1502. .clkr = {
  1503. .enable_reg = 0x52004,
  1504. .enable_mask = BIT(16),
  1505. .hw.init = &(struct clk_init_data){
  1506. .name = "gcc_gpu_gpll0_div_clk_src",
  1507. .parent_hws = (const struct clk_hw *[]){
  1508. &gpll0_out_even.clkr.hw },
  1509. .num_parents = 1,
  1510. .flags = CLK_SET_RATE_PARENT,
  1511. .ops = &clk_branch2_ops,
  1512. },
  1513. },
  1514. };
  1515. static struct clk_branch gcc_gpu_iref_clk = {
  1516. .halt_reg = 0x8c010,
  1517. .halt_check = BRANCH_HALT,
  1518. .clkr = {
  1519. .enable_reg = 0x8c010,
  1520. .enable_mask = BIT(0),
  1521. .hw.init = &(struct clk_init_data){
  1522. .name = "gcc_gpu_iref_clk",
  1523. .ops = &clk_branch2_ops,
  1524. },
  1525. },
  1526. };
  1527. static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
  1528. .halt_reg = 0x7100c,
  1529. .halt_check = BRANCH_VOTED,
  1530. .clkr = {
  1531. .enable_reg = 0x7100c,
  1532. .enable_mask = BIT(0),
  1533. .hw.init = &(struct clk_init_data){
  1534. .name = "gcc_gpu_memnoc_gfx_clk",
  1535. .ops = &clk_branch2_ops,
  1536. },
  1537. },
  1538. };
  1539. static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
  1540. .halt_reg = 0x71018,
  1541. .halt_check = BRANCH_HALT,
  1542. .clkr = {
  1543. .enable_reg = 0x71018,
  1544. .enable_mask = BIT(0),
  1545. .hw.init = &(struct clk_init_data){
  1546. .name = "gcc_gpu_snoc_dvm_gfx_clk",
  1547. .ops = &clk_branch2_ops,
  1548. },
  1549. },
  1550. };
  1551. static struct clk_branch gcc_npu_at_clk = {
  1552. .halt_reg = 0x4d010,
  1553. .halt_check = BRANCH_VOTED,
  1554. .clkr = {
  1555. .enable_reg = 0x4d010,
  1556. .enable_mask = BIT(0),
  1557. .hw.init = &(struct clk_init_data){
  1558. .name = "gcc_npu_at_clk",
  1559. .ops = &clk_branch2_ops,
  1560. },
  1561. },
  1562. };
  1563. static struct clk_branch gcc_npu_axi_clk = {
  1564. .halt_reg = 0x4d008,
  1565. .halt_check = BRANCH_VOTED,
  1566. .clkr = {
  1567. .enable_reg = 0x4d008,
  1568. .enable_mask = BIT(0),
  1569. .hw.init = &(struct clk_init_data){
  1570. .name = "gcc_npu_axi_clk",
  1571. .ops = &clk_branch2_ops,
  1572. },
  1573. },
  1574. };
  1575. static struct clk_branch gcc_npu_cfg_ahb_clk = {
  1576. .halt_reg = 0x4d004,
  1577. .halt_check = BRANCH_HALT,
  1578. .hwcg_reg = 0x4d004,
  1579. .hwcg_bit = 1,
  1580. .clkr = {
  1581. .enable_reg = 0x4d004,
  1582. .enable_mask = BIT(0),
  1583. .hw.init = &(struct clk_init_data){
  1584. .name = "gcc_npu_cfg_ahb_clk",
  1585. /* required for npu */
  1586. .flags = CLK_IS_CRITICAL,
  1587. .ops = &clk_branch2_ops,
  1588. },
  1589. },
  1590. };
  1591. static struct clk_branch gcc_npu_gpll0_clk_src = {
  1592. .halt_check = BRANCH_HALT_SKIP,
  1593. .clkr = {
  1594. .enable_reg = 0x52004,
  1595. .enable_mask = BIT(18),
  1596. .hw.init = &(struct clk_init_data){
  1597. .name = "gcc_npu_gpll0_clk_src",
  1598. .parent_hws = (const struct clk_hw *[]){
  1599. &gpll0.clkr.hw },
  1600. .num_parents = 1,
  1601. .flags = CLK_SET_RATE_PARENT,
  1602. .ops = &clk_branch2_ops,
  1603. },
  1604. },
  1605. };
  1606. static struct clk_branch gcc_npu_gpll0_div_clk_src = {
  1607. .halt_check = BRANCH_HALT_SKIP,
  1608. .clkr = {
  1609. .enable_reg = 0x52004,
  1610. .enable_mask = BIT(19),
  1611. .hw.init = &(struct clk_init_data){
  1612. .name = "gcc_npu_gpll0_div_clk_src",
  1613. .parent_hws = (const struct clk_hw *[]){
  1614. &gpll0_out_even.clkr.hw },
  1615. .num_parents = 1,
  1616. .flags = CLK_SET_RATE_PARENT,
  1617. .ops = &clk_branch2_ops,
  1618. },
  1619. },
  1620. };
  1621. static struct clk_branch gcc_npu_trig_clk = {
  1622. .halt_reg = 0x4d00c,
  1623. .halt_check = BRANCH_VOTED,
  1624. .clkr = {
  1625. .enable_reg = 0x4d00c,
  1626. .enable_mask = BIT(0),
  1627. .hw.init = &(struct clk_init_data){
  1628. .name = "gcc_npu_trig_clk",
  1629. .ops = &clk_branch2_ops,
  1630. },
  1631. },
  1632. };
  1633. static struct clk_branch gcc_pcie0_phy_refgen_clk = {
  1634. .halt_reg = 0x6f02c,
  1635. .halt_check = BRANCH_HALT,
  1636. .clkr = {
  1637. .enable_reg = 0x6f02c,
  1638. .enable_mask = BIT(0),
  1639. .hw.init = &(struct clk_init_data){
  1640. .name = "gcc_pcie0_phy_refgen_clk",
  1641. .parent_hws = (const struct clk_hw *[]){
  1642. &gcc_pcie_phy_refgen_clk_src.clkr.hw },
  1643. .num_parents = 1,
  1644. .flags = CLK_SET_RATE_PARENT,
  1645. .ops = &clk_branch2_ops,
  1646. },
  1647. },
  1648. };
  1649. static struct clk_branch gcc_pcie1_phy_refgen_clk = {
  1650. .halt_reg = 0x6f030,
  1651. .halt_check = BRANCH_HALT,
  1652. .clkr = {
  1653. .enable_reg = 0x6f030,
  1654. .enable_mask = BIT(0),
  1655. .hw.init = &(struct clk_init_data){
  1656. .name = "gcc_pcie1_phy_refgen_clk",
  1657. .parent_hws = (const struct clk_hw *[]){
  1658. &gcc_pcie_phy_refgen_clk_src.clkr.hw },
  1659. .num_parents = 1,
  1660. .flags = CLK_SET_RATE_PARENT,
  1661. .ops = &clk_branch2_ops,
  1662. },
  1663. },
  1664. };
  1665. static struct clk_branch gcc_pcie_0_aux_clk = {
  1666. .halt_reg = 0x6b020,
  1667. .halt_check = BRANCH_HALT_VOTED,
  1668. .clkr = {
  1669. .enable_reg = 0x5200c,
  1670. .enable_mask = BIT(3),
  1671. .hw.init = &(struct clk_init_data){
  1672. .name = "gcc_pcie_0_aux_clk",
  1673. .parent_hws = (const struct clk_hw *[]){
  1674. &gcc_pcie_0_aux_clk_src.clkr.hw },
  1675. .num_parents = 1,
  1676. .flags = CLK_SET_RATE_PARENT,
  1677. .ops = &clk_branch2_ops,
  1678. },
  1679. },
  1680. };
  1681. static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
  1682. .halt_reg = 0x6b01c,
  1683. .halt_check = BRANCH_HALT_VOTED,
  1684. .hwcg_reg = 0x6b01c,
  1685. .hwcg_bit = 1,
  1686. .clkr = {
  1687. .enable_reg = 0x5200c,
  1688. .enable_mask = BIT(2),
  1689. .hw.init = &(struct clk_init_data){
  1690. .name = "gcc_pcie_0_cfg_ahb_clk",
  1691. .ops = &clk_branch2_ops,
  1692. },
  1693. },
  1694. };
  1695. static struct clk_branch gcc_pcie_0_clkref_clk = {
  1696. .halt_reg = 0x8c00c,
  1697. .halt_check = BRANCH_HALT,
  1698. .clkr = {
  1699. .enable_reg = 0x8c00c,
  1700. .enable_mask = BIT(0),
  1701. .hw.init = &(struct clk_init_data){
  1702. .name = "gcc_pcie_0_clkref_clk",
  1703. .ops = &clk_branch2_ops,
  1704. },
  1705. },
  1706. };
  1707. static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
  1708. .halt_reg = 0x6b018,
  1709. .halt_check = BRANCH_HALT_VOTED,
  1710. .clkr = {
  1711. .enable_reg = 0x5200c,
  1712. .enable_mask = BIT(1),
  1713. .hw.init = &(struct clk_init_data){
  1714. .name = "gcc_pcie_0_mstr_axi_clk",
  1715. .ops = &clk_branch2_ops,
  1716. },
  1717. },
  1718. };
  1719. /* Clock ON depends on external parent 'PIPE' clock, so dont poll */
  1720. static struct clk_branch gcc_pcie_0_pipe_clk = {
  1721. .halt_reg = 0x6b024,
  1722. .halt_check = BRANCH_HALT_DELAY,
  1723. .clkr = {
  1724. .enable_reg = 0x5200c,
  1725. .enable_mask = BIT(4),
  1726. .hw.init = &(struct clk_init_data){
  1727. .name = "gcc_pcie_0_pipe_clk",
  1728. .ops = &clk_branch2_ops,
  1729. },
  1730. },
  1731. };
  1732. static struct clk_branch gcc_pcie_0_slv_axi_clk = {
  1733. .halt_reg = 0x6b014,
  1734. .halt_check = BRANCH_HALT_VOTED,
  1735. .hwcg_reg = 0x6b014,
  1736. .hwcg_bit = 1,
  1737. .clkr = {
  1738. .enable_reg = 0x5200c,
  1739. .enable_mask = BIT(0),
  1740. .hw.init = &(struct clk_init_data){
  1741. .name = "gcc_pcie_0_slv_axi_clk",
  1742. .ops = &clk_branch2_ops,
  1743. },
  1744. },
  1745. };
  1746. static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
  1747. .halt_reg = 0x6b010,
  1748. .halt_check = BRANCH_HALT_VOTED,
  1749. .clkr = {
  1750. .enable_reg = 0x5200c,
  1751. .enable_mask = BIT(5),
  1752. .hw.init = &(struct clk_init_data){
  1753. .name = "gcc_pcie_0_slv_q2a_axi_clk",
  1754. .ops = &clk_branch2_ops,
  1755. },
  1756. },
  1757. };
  1758. static struct clk_branch gcc_pcie_1_aux_clk = {
  1759. .halt_reg = 0x8d020,
  1760. .halt_check = BRANCH_HALT_VOTED,
  1761. .clkr = {
  1762. .enable_reg = 0x52004,
  1763. .enable_mask = BIT(29),
  1764. .hw.init = &(struct clk_init_data){
  1765. .name = "gcc_pcie_1_aux_clk",
  1766. .parent_hws = (const struct clk_hw *[]){
  1767. &gcc_pcie_1_aux_clk_src.clkr.hw },
  1768. .num_parents = 1,
  1769. .flags = CLK_SET_RATE_PARENT,
  1770. .ops = &clk_branch2_ops,
  1771. },
  1772. },
  1773. };
  1774. static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
  1775. .halt_reg = 0x8d01c,
  1776. .halt_check = BRANCH_HALT_VOTED,
  1777. .hwcg_reg = 0x8d01c,
  1778. .hwcg_bit = 1,
  1779. .clkr = {
  1780. .enable_reg = 0x52004,
  1781. .enable_mask = BIT(28),
  1782. .hw.init = &(struct clk_init_data){
  1783. .name = "gcc_pcie_1_cfg_ahb_clk",
  1784. .ops = &clk_branch2_ops,
  1785. },
  1786. },
  1787. };
  1788. static struct clk_branch gcc_pcie_1_clkref_clk = {
  1789. .halt_reg = 0x8c02c,
  1790. .halt_check = BRANCH_HALT,
  1791. .clkr = {
  1792. .enable_reg = 0x8c02c,
  1793. .enable_mask = BIT(0),
  1794. .hw.init = &(struct clk_init_data){
  1795. .name = "gcc_pcie_1_clkref_clk",
  1796. .ops = &clk_branch2_ops,
  1797. },
  1798. },
  1799. };
  1800. static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
  1801. .halt_reg = 0x8d018,
  1802. .halt_check = BRANCH_HALT_VOTED,
  1803. .clkr = {
  1804. .enable_reg = 0x52004,
  1805. .enable_mask = BIT(27),
  1806. .hw.init = &(struct clk_init_data){
  1807. .name = "gcc_pcie_1_mstr_axi_clk",
  1808. .ops = &clk_branch2_ops,
  1809. },
  1810. },
  1811. };
  1812. /* Clock ON depends on external parent 'PIPE' clock, so dont poll */
  1813. static struct clk_branch gcc_pcie_1_pipe_clk = {
  1814. .halt_reg = 0x8d024,
  1815. .halt_check = BRANCH_HALT_DELAY,
  1816. .clkr = {
  1817. .enable_reg = 0x52004,
  1818. .enable_mask = BIT(30),
  1819. .hw.init = &(struct clk_init_data){
  1820. .name = "gcc_pcie_1_pipe_clk",
  1821. .ops = &clk_branch2_ops,
  1822. },
  1823. },
  1824. };
  1825. static struct clk_branch gcc_pcie_1_slv_axi_clk = {
  1826. .halt_reg = 0x8d014,
  1827. .halt_check = BRANCH_HALT_VOTED,
  1828. .hwcg_reg = 0x8d014,
  1829. .hwcg_bit = 1,
  1830. .clkr = {
  1831. .enable_reg = 0x52004,
  1832. .enable_mask = BIT(26),
  1833. .hw.init = &(struct clk_init_data){
  1834. .name = "gcc_pcie_1_slv_axi_clk",
  1835. .ops = &clk_branch2_ops,
  1836. },
  1837. },
  1838. };
  1839. static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
  1840. .halt_reg = 0x8d010,
  1841. .halt_check = BRANCH_HALT_VOTED,
  1842. .clkr = {
  1843. .enable_reg = 0x52004,
  1844. .enable_mask = BIT(25),
  1845. .hw.init = &(struct clk_init_data){
  1846. .name = "gcc_pcie_1_slv_q2a_axi_clk",
  1847. .ops = &clk_branch2_ops,
  1848. },
  1849. },
  1850. };
  1851. static struct clk_branch gcc_pcie_phy_aux_clk = {
  1852. .halt_reg = 0x6f004,
  1853. .halt_check = BRANCH_HALT,
  1854. .clkr = {
  1855. .enable_reg = 0x6f004,
  1856. .enable_mask = BIT(0),
  1857. .hw.init = &(struct clk_init_data){
  1858. .name = "gcc_pcie_phy_aux_clk",
  1859. .parent_hws = (const struct clk_hw *[]){
  1860. &gcc_pcie_0_aux_clk_src.clkr.hw },
  1861. .num_parents = 1,
  1862. .flags = CLK_SET_RATE_PARENT,
  1863. .ops = &clk_branch2_ops,
  1864. },
  1865. },
  1866. };
  1867. static struct clk_branch gcc_pdm2_clk = {
  1868. .halt_reg = 0x3300c,
  1869. .halt_check = BRANCH_HALT,
  1870. .clkr = {
  1871. .enable_reg = 0x3300c,
  1872. .enable_mask = BIT(0),
  1873. .hw.init = &(struct clk_init_data){
  1874. .name = "gcc_pdm2_clk",
  1875. .parent_hws = (const struct clk_hw *[]){
  1876. &gcc_pdm2_clk_src.clkr.hw },
  1877. .num_parents = 1,
  1878. .flags = CLK_SET_RATE_PARENT,
  1879. .ops = &clk_branch2_ops,
  1880. },
  1881. },
  1882. };
  1883. static struct clk_branch gcc_pdm_ahb_clk = {
  1884. .halt_reg = 0x33004,
  1885. .halt_check = BRANCH_HALT,
  1886. .hwcg_reg = 0x33004,
  1887. .hwcg_bit = 1,
  1888. .clkr = {
  1889. .enable_reg = 0x33004,
  1890. .enable_mask = BIT(0),
  1891. .hw.init = &(struct clk_init_data){
  1892. .name = "gcc_pdm_ahb_clk",
  1893. .ops = &clk_branch2_ops,
  1894. },
  1895. },
  1896. };
  1897. static struct clk_branch gcc_pdm_xo4_clk = {
  1898. .halt_reg = 0x33008,
  1899. .halt_check = BRANCH_HALT,
  1900. .clkr = {
  1901. .enable_reg = 0x33008,
  1902. .enable_mask = BIT(0),
  1903. .hw.init = &(struct clk_init_data){
  1904. .name = "gcc_pdm_xo4_clk",
  1905. .ops = &clk_branch2_ops,
  1906. },
  1907. },
  1908. };
  1909. static struct clk_branch gcc_prng_ahb_clk = {
  1910. .halt_reg = 0x34004,
  1911. .halt_check = BRANCH_HALT_VOTED,
  1912. .clkr = {
  1913. .enable_reg = 0x52004,
  1914. .enable_mask = BIT(13),
  1915. .hw.init = &(struct clk_init_data){
  1916. .name = "gcc_prng_ahb_clk",
  1917. .ops = &clk_branch2_ops,
  1918. },
  1919. },
  1920. };
  1921. static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
  1922. .halt_reg = 0xb018,
  1923. .halt_check = BRANCH_HALT,
  1924. .hwcg_reg = 0xb018,
  1925. .hwcg_bit = 1,
  1926. .clkr = {
  1927. .enable_reg = 0xb018,
  1928. .enable_mask = BIT(0),
  1929. .hw.init = &(struct clk_init_data){
  1930. .name = "gcc_qmip_camera_nrt_ahb_clk",
  1931. .ops = &clk_branch2_ops,
  1932. },
  1933. },
  1934. };
  1935. static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
  1936. .halt_reg = 0xb01c,
  1937. .halt_check = BRANCH_HALT,
  1938. .hwcg_reg = 0xb01c,
  1939. .hwcg_bit = 1,
  1940. .clkr = {
  1941. .enable_reg = 0xb01c,
  1942. .enable_mask = BIT(0),
  1943. .hw.init = &(struct clk_init_data){
  1944. .name = "gcc_qmip_camera_rt_ahb_clk",
  1945. .ops = &clk_branch2_ops,
  1946. },
  1947. },
  1948. };
  1949. static struct clk_branch gcc_qmip_disp_ahb_clk = {
  1950. .halt_reg = 0xb020,
  1951. .halt_check = BRANCH_HALT,
  1952. .hwcg_reg = 0xb020,
  1953. .hwcg_bit = 1,
  1954. .clkr = {
  1955. .enable_reg = 0xb020,
  1956. .enable_mask = BIT(0),
  1957. .hw.init = &(struct clk_init_data){
  1958. .name = "gcc_qmip_disp_ahb_clk",
  1959. .ops = &clk_branch2_ops,
  1960. },
  1961. },
  1962. };
  1963. static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
  1964. .halt_reg = 0xb010,
  1965. .halt_check = BRANCH_HALT,
  1966. .hwcg_reg = 0xb010,
  1967. .hwcg_bit = 1,
  1968. .clkr = {
  1969. .enable_reg = 0xb010,
  1970. .enable_mask = BIT(0),
  1971. .hw.init = &(struct clk_init_data){
  1972. .name = "gcc_qmip_video_cvp_ahb_clk",
  1973. .ops = &clk_branch2_ops,
  1974. },
  1975. },
  1976. };
  1977. static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
  1978. .halt_reg = 0xb014,
  1979. .halt_check = BRANCH_HALT,
  1980. .hwcg_reg = 0xb014,
  1981. .hwcg_bit = 1,
  1982. .clkr = {
  1983. .enable_reg = 0xb014,
  1984. .enable_mask = BIT(0),
  1985. .hw.init = &(struct clk_init_data){
  1986. .name = "gcc_qmip_video_vcodec_ahb_clk",
  1987. .ops = &clk_branch2_ops,
  1988. },
  1989. },
  1990. };
  1991. static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
  1992. .halt_reg = 0x4b000,
  1993. .halt_check = BRANCH_HALT,
  1994. .clkr = {
  1995. .enable_reg = 0x4b000,
  1996. .enable_mask = BIT(0),
  1997. .hw.init = &(struct clk_init_data){
  1998. .name = "gcc_qspi_cnoc_periph_ahb_clk",
  1999. .ops = &clk_branch2_ops,
  2000. },
  2001. },
  2002. };
  2003. static struct clk_branch gcc_qspi_core_clk = {
  2004. .halt_reg = 0x4b004,
  2005. .halt_check = BRANCH_HALT,
  2006. .clkr = {
  2007. .enable_reg = 0x4b004,
  2008. .enable_mask = BIT(0),
  2009. .hw.init = &(struct clk_init_data){
  2010. .name = "gcc_qspi_core_clk",
  2011. .parent_hws = (const struct clk_hw *[]){
  2012. &gcc_qspi_core_clk_src.clkr.hw },
  2013. .num_parents = 1,
  2014. .flags = CLK_SET_RATE_PARENT,
  2015. .ops = &clk_branch2_ops,
  2016. },
  2017. },
  2018. };
  2019. static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
  2020. .halt_reg = 0x17144,
  2021. .halt_check = BRANCH_HALT_VOTED,
  2022. .clkr = {
  2023. .enable_reg = 0x5200c,
  2024. .enable_mask = BIT(10),
  2025. .hw.init = &(struct clk_init_data){
  2026. .name = "gcc_qupv3_wrap0_s0_clk",
  2027. .parent_hws = (const struct clk_hw *[]){
  2028. &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
  2029. .num_parents = 1,
  2030. .flags = CLK_SET_RATE_PARENT,
  2031. .ops = &clk_branch2_ops,
  2032. },
  2033. },
  2034. };
  2035. static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
  2036. .halt_reg = 0x17274,
  2037. .halt_check = BRANCH_HALT_VOTED,
  2038. .clkr = {
  2039. .enable_reg = 0x5200c,
  2040. .enable_mask = BIT(11),
  2041. .hw.init = &(struct clk_init_data){
  2042. .name = "gcc_qupv3_wrap0_s1_clk",
  2043. .parent_hws = (const struct clk_hw *[]){
  2044. &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
  2045. .num_parents = 1,
  2046. .flags = CLK_SET_RATE_PARENT,
  2047. .ops = &clk_branch2_ops,
  2048. },
  2049. },
  2050. };
  2051. static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
  2052. .halt_reg = 0x173a4,
  2053. .halt_check = BRANCH_HALT_VOTED,
  2054. .clkr = {
  2055. .enable_reg = 0x5200c,
  2056. .enable_mask = BIT(12),
  2057. .hw.init = &(struct clk_init_data){
  2058. .name = "gcc_qupv3_wrap0_s2_clk",
  2059. .parent_hws = (const struct clk_hw *[]){
  2060. &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
  2061. .num_parents = 1,
  2062. .flags = CLK_SET_RATE_PARENT,
  2063. .ops = &clk_branch2_ops,
  2064. },
  2065. },
  2066. };
  2067. static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
  2068. .halt_reg = 0x174d4,
  2069. .halt_check = BRANCH_HALT_VOTED,
  2070. .clkr = {
  2071. .enable_reg = 0x5200c,
  2072. .enable_mask = BIT(13),
  2073. .hw.init = &(struct clk_init_data){
  2074. .name = "gcc_qupv3_wrap0_s3_clk",
  2075. .parent_hws = (const struct clk_hw *[]){
  2076. &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
  2077. .num_parents = 1,
  2078. .flags = CLK_SET_RATE_PARENT,
  2079. .ops = &clk_branch2_ops,
  2080. },
  2081. },
  2082. };
  2083. static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
  2084. .halt_reg = 0x17604,
  2085. .halt_check = BRANCH_HALT_VOTED,
  2086. .clkr = {
  2087. .enable_reg = 0x5200c,
  2088. .enable_mask = BIT(14),
  2089. .hw.init = &(struct clk_init_data){
  2090. .name = "gcc_qupv3_wrap0_s4_clk",
  2091. .parent_hws = (const struct clk_hw *[]){
  2092. &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
  2093. .num_parents = 1,
  2094. .flags = CLK_SET_RATE_PARENT,
  2095. .ops = &clk_branch2_ops,
  2096. },
  2097. },
  2098. };
  2099. static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
  2100. .halt_reg = 0x17734,
  2101. .halt_check = BRANCH_HALT_VOTED,
  2102. .clkr = {
  2103. .enable_reg = 0x5200c,
  2104. .enable_mask = BIT(15),
  2105. .hw.init = &(struct clk_init_data){
  2106. .name = "gcc_qupv3_wrap0_s5_clk",
  2107. .parent_hws = (const struct clk_hw *[]){
  2108. &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
  2109. .num_parents = 1,
  2110. .flags = CLK_SET_RATE_PARENT,
  2111. .ops = &clk_branch2_ops,
  2112. },
  2113. },
  2114. };
  2115. static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
  2116. .halt_reg = 0x17864,
  2117. .halt_check = BRANCH_HALT_VOTED,
  2118. .clkr = {
  2119. .enable_reg = 0x5200c,
  2120. .enable_mask = BIT(16),
  2121. .hw.init = &(struct clk_init_data){
  2122. .name = "gcc_qupv3_wrap0_s6_clk",
  2123. .parent_hws = (const struct clk_hw *[]){
  2124. &gcc_qupv3_wrap0_s6_clk_src.clkr.hw },
  2125. .num_parents = 1,
  2126. .flags = CLK_SET_RATE_PARENT,
  2127. .ops = &clk_branch2_ops,
  2128. },
  2129. },
  2130. };
  2131. static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
  2132. .halt_reg = 0x17994,
  2133. .halt_check = BRANCH_HALT_VOTED,
  2134. .clkr = {
  2135. .enable_reg = 0x5200c,
  2136. .enable_mask = BIT(17),
  2137. .hw.init = &(struct clk_init_data){
  2138. .name = "gcc_qupv3_wrap0_s7_clk",
  2139. .parent_hws = (const struct clk_hw *[]){
  2140. &gcc_qupv3_wrap0_s7_clk_src.clkr.hw },
  2141. .num_parents = 1,
  2142. .flags = CLK_SET_RATE_PARENT,
  2143. .ops = &clk_branch2_ops,
  2144. },
  2145. },
  2146. };
  2147. static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
  2148. .halt_reg = 0x18144,
  2149. .halt_check = BRANCH_HALT_VOTED,
  2150. .clkr = {
  2151. .enable_reg = 0x5200c,
  2152. .enable_mask = BIT(22),
  2153. .hw.init = &(struct clk_init_data){
  2154. .name = "gcc_qupv3_wrap1_s0_clk",
  2155. .parent_hws = (const struct clk_hw *[]){
  2156. &gcc_qupv3_wrap1_s0_clk_src.clkr.hw },
  2157. .num_parents = 1,
  2158. .flags = CLK_SET_RATE_PARENT,
  2159. .ops = &clk_branch2_ops,
  2160. },
  2161. },
  2162. };
  2163. static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
  2164. .halt_reg = 0x18274,
  2165. .halt_check = BRANCH_HALT_VOTED,
  2166. .clkr = {
  2167. .enable_reg = 0x5200c,
  2168. .enable_mask = BIT(23),
  2169. .hw.init = &(struct clk_init_data){
  2170. .name = "gcc_qupv3_wrap1_s1_clk",
  2171. .parent_hws = (const struct clk_hw *[]){
  2172. &gcc_qupv3_wrap1_s1_clk_src.clkr.hw },
  2173. .num_parents = 1,
  2174. .flags = CLK_SET_RATE_PARENT,
  2175. .ops = &clk_branch2_ops,
  2176. },
  2177. },
  2178. };
  2179. static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
  2180. .halt_reg = 0x183a4,
  2181. .halt_check = BRANCH_HALT_VOTED,
  2182. .clkr = {
  2183. .enable_reg = 0x5200c,
  2184. .enable_mask = BIT(24),
  2185. .hw.init = &(struct clk_init_data){
  2186. .name = "gcc_qupv3_wrap1_s2_clk",
  2187. .parent_hws = (const struct clk_hw *[]){
  2188. &gcc_qupv3_wrap1_s2_clk_src.clkr.hw },
  2189. .num_parents = 1,
  2190. .flags = CLK_SET_RATE_PARENT,
  2191. .ops = &clk_branch2_ops,
  2192. },
  2193. },
  2194. };
  2195. static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
  2196. .halt_reg = 0x184d4,
  2197. .halt_check = BRANCH_HALT_VOTED,
  2198. .clkr = {
  2199. .enable_reg = 0x5200c,
  2200. .enable_mask = BIT(25),
  2201. .hw.init = &(struct clk_init_data){
  2202. .name = "gcc_qupv3_wrap1_s3_clk",
  2203. .parent_hws = (const struct clk_hw *[]){
  2204. &gcc_qupv3_wrap1_s3_clk_src.clkr.hw },
  2205. .num_parents = 1,
  2206. .flags = CLK_SET_RATE_PARENT,
  2207. .ops = &clk_branch2_ops,
  2208. },
  2209. },
  2210. };
  2211. static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
  2212. .halt_reg = 0x18604,
  2213. .halt_check = BRANCH_HALT_VOTED,
  2214. .clkr = {
  2215. .enable_reg = 0x5200c,
  2216. .enable_mask = BIT(26),
  2217. .hw.init = &(struct clk_init_data){
  2218. .name = "gcc_qupv3_wrap1_s4_clk",
  2219. .parent_hws = (const struct clk_hw *[]){
  2220. &gcc_qupv3_wrap1_s4_clk_src.clkr.hw },
  2221. .num_parents = 1,
  2222. .flags = CLK_SET_RATE_PARENT,
  2223. .ops = &clk_branch2_ops,
  2224. },
  2225. },
  2226. };
  2227. static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
  2228. .halt_reg = 0x18734,
  2229. .halt_check = BRANCH_HALT_VOTED,
  2230. .clkr = {
  2231. .enable_reg = 0x5200c,
  2232. .enable_mask = BIT(27),
  2233. .hw.init = &(struct clk_init_data){
  2234. .name = "gcc_qupv3_wrap1_s5_clk",
  2235. .parent_hws = (const struct clk_hw *[]){
  2236. &gcc_qupv3_wrap1_s5_clk_src.clkr.hw },
  2237. .num_parents = 1,
  2238. .flags = CLK_SET_RATE_PARENT,
  2239. .ops = &clk_branch2_ops,
  2240. },
  2241. },
  2242. };
  2243. static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
  2244. .halt_reg = 0x1e144,
  2245. .halt_check = BRANCH_HALT_VOTED,
  2246. .clkr = {
  2247. .enable_reg = 0x52014,
  2248. .enable_mask = BIT(4),
  2249. .hw.init = &(struct clk_init_data){
  2250. .name = "gcc_qupv3_wrap2_s0_clk",
  2251. .parent_hws = (const struct clk_hw *[]){
  2252. &gcc_qupv3_wrap2_s0_clk_src.clkr.hw },
  2253. .num_parents = 1,
  2254. .flags = CLK_SET_RATE_PARENT,
  2255. .ops = &clk_branch2_ops,
  2256. },
  2257. },
  2258. };
  2259. static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
  2260. .halt_reg = 0x1e274,
  2261. .halt_check = BRANCH_HALT_VOTED,
  2262. .clkr = {
  2263. .enable_reg = 0x52014,
  2264. .enable_mask = BIT(5),
  2265. .hw.init = &(struct clk_init_data){
  2266. .name = "gcc_qupv3_wrap2_s1_clk",
  2267. .parent_hws = (const struct clk_hw *[]){
  2268. &gcc_qupv3_wrap2_s1_clk_src.clkr.hw },
  2269. .num_parents = 1,
  2270. .flags = CLK_SET_RATE_PARENT,
  2271. .ops = &clk_branch2_ops,
  2272. },
  2273. },
  2274. };
  2275. static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
  2276. .halt_reg = 0x1e3a4,
  2277. .halt_check = BRANCH_HALT_VOTED,
  2278. .clkr = {
  2279. .enable_reg = 0x52014,
  2280. .enable_mask = BIT(6),
  2281. .hw.init = &(struct clk_init_data){
  2282. .name = "gcc_qupv3_wrap2_s2_clk",
  2283. .parent_hws = (const struct clk_hw *[]){
  2284. &gcc_qupv3_wrap2_s2_clk_src.clkr.hw },
  2285. .num_parents = 1,
  2286. .flags = CLK_SET_RATE_PARENT,
  2287. .ops = &clk_branch2_ops,
  2288. },
  2289. },
  2290. };
  2291. static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
  2292. .halt_reg = 0x1e4d4,
  2293. .halt_check = BRANCH_HALT_VOTED,
  2294. .clkr = {
  2295. .enable_reg = 0x52014,
  2296. .enable_mask = BIT(7),
  2297. .hw.init = &(struct clk_init_data){
  2298. .name = "gcc_qupv3_wrap2_s3_clk",
  2299. .parent_hws = (const struct clk_hw *[]){
  2300. &gcc_qupv3_wrap2_s3_clk_src.clkr.hw },
  2301. .num_parents = 1,
  2302. .flags = CLK_SET_RATE_PARENT,
  2303. .ops = &clk_branch2_ops,
  2304. },
  2305. },
  2306. };
  2307. static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
  2308. .halt_reg = 0x1e604,
  2309. .halt_check = BRANCH_HALT_VOTED,
  2310. .clkr = {
  2311. .enable_reg = 0x52014,
  2312. .enable_mask = BIT(8),
  2313. .hw.init = &(struct clk_init_data){
  2314. .name = "gcc_qupv3_wrap2_s4_clk",
  2315. .parent_hws = (const struct clk_hw *[]){
  2316. &gcc_qupv3_wrap2_s4_clk_src.clkr.hw },
  2317. .num_parents = 1,
  2318. .flags = CLK_SET_RATE_PARENT,
  2319. .ops = &clk_branch2_ops,
  2320. },
  2321. },
  2322. };
  2323. static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
  2324. .halt_reg = 0x1e734,
  2325. .halt_check = BRANCH_HALT_VOTED,
  2326. .clkr = {
  2327. .enable_reg = 0x52014,
  2328. .enable_mask = BIT(9),
  2329. .hw.init = &(struct clk_init_data){
  2330. .name = "gcc_qupv3_wrap2_s5_clk",
  2331. .parent_hws = (const struct clk_hw *[]){
  2332. &gcc_qupv3_wrap2_s5_clk_src.clkr.hw },
  2333. .num_parents = 1,
  2334. .flags = CLK_SET_RATE_PARENT,
  2335. .ops = &clk_branch2_ops,
  2336. },
  2337. },
  2338. };
  2339. static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
  2340. .halt_reg = 0x17004,
  2341. .halt_check = BRANCH_HALT_VOTED,
  2342. .clkr = {
  2343. .enable_reg = 0x5200c,
  2344. .enable_mask = BIT(6),
  2345. .hw.init = &(struct clk_init_data){
  2346. .name = "gcc_qupv3_wrap_0_m_ahb_clk",
  2347. .ops = &clk_branch2_ops,
  2348. },
  2349. },
  2350. };
  2351. static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
  2352. .halt_reg = 0x17008,
  2353. .halt_check = BRANCH_HALT_VOTED,
  2354. .hwcg_reg = 0x17008,
  2355. .hwcg_bit = 1,
  2356. .clkr = {
  2357. .enable_reg = 0x5200c,
  2358. .enable_mask = BIT(7),
  2359. .hw.init = &(struct clk_init_data){
  2360. .name = "gcc_qupv3_wrap_0_s_ahb_clk",
  2361. .ops = &clk_branch2_ops,
  2362. },
  2363. },
  2364. };
  2365. static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
  2366. .halt_reg = 0x18004,
  2367. .halt_check = BRANCH_HALT_VOTED,
  2368. .clkr = {
  2369. .enable_reg = 0x5200c,
  2370. .enable_mask = BIT(20),
  2371. .hw.init = &(struct clk_init_data){
  2372. .name = "gcc_qupv3_wrap_1_m_ahb_clk",
  2373. .ops = &clk_branch2_ops,
  2374. },
  2375. },
  2376. };
  2377. static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
  2378. .halt_reg = 0x18008,
  2379. .halt_check = BRANCH_HALT_VOTED,
  2380. .hwcg_reg = 0x18008,
  2381. .hwcg_bit = 1,
  2382. .clkr = {
  2383. .enable_reg = 0x5200c,
  2384. .enable_mask = BIT(21),
  2385. .hw.init = &(struct clk_init_data){
  2386. .name = "gcc_qupv3_wrap_1_s_ahb_clk",
  2387. .ops = &clk_branch2_ops,
  2388. },
  2389. },
  2390. };
  2391. static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
  2392. .halt_reg = 0x1e004,
  2393. .halt_check = BRANCH_HALT_VOTED,
  2394. .clkr = {
  2395. .enable_reg = 0x52014,
  2396. .enable_mask = BIT(2),
  2397. .hw.init = &(struct clk_init_data){
  2398. .name = "gcc_qupv3_wrap_2_m_ahb_clk",
  2399. .ops = &clk_branch2_ops,
  2400. },
  2401. },
  2402. };
  2403. static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
  2404. .halt_reg = 0x1e008,
  2405. .halt_check = BRANCH_HALT_VOTED,
  2406. .hwcg_reg = 0x1e008,
  2407. .hwcg_bit = 1,
  2408. .clkr = {
  2409. .enable_reg = 0x52014,
  2410. .enable_mask = BIT(1),
  2411. .hw.init = &(struct clk_init_data){
  2412. .name = "gcc_qupv3_wrap_2_s_ahb_clk",
  2413. .ops = &clk_branch2_ops,
  2414. },
  2415. },
  2416. };
  2417. static struct clk_branch gcc_sdcc2_ahb_clk = {
  2418. .halt_reg = 0x14008,
  2419. .halt_check = BRANCH_HALT,
  2420. .clkr = {
  2421. .enable_reg = 0x14008,
  2422. .enable_mask = BIT(0),
  2423. .hw.init = &(struct clk_init_data){
  2424. .name = "gcc_sdcc2_ahb_clk",
  2425. .ops = &clk_branch2_ops,
  2426. },
  2427. },
  2428. };
  2429. static struct clk_branch gcc_sdcc2_apps_clk = {
  2430. .halt_reg = 0x14004,
  2431. .halt_check = BRANCH_HALT,
  2432. .clkr = {
  2433. .enable_reg = 0x14004,
  2434. .enable_mask = BIT(0),
  2435. .hw.init = &(struct clk_init_data){
  2436. .name = "gcc_sdcc2_apps_clk",
  2437. .parent_hws = (const struct clk_hw *[]){
  2438. &gcc_sdcc2_apps_clk_src.clkr.hw },
  2439. .num_parents = 1,
  2440. .flags = CLK_SET_RATE_PARENT,
  2441. .ops = &clk_branch2_ops,
  2442. },
  2443. },
  2444. };
  2445. static struct clk_branch gcc_sdcc4_ahb_clk = {
  2446. .halt_reg = 0x16008,
  2447. .halt_check = BRANCH_HALT,
  2448. .clkr = {
  2449. .enable_reg = 0x16008,
  2450. .enable_mask = BIT(0),
  2451. .hw.init = &(struct clk_init_data){
  2452. .name = "gcc_sdcc4_ahb_clk",
  2453. .ops = &clk_branch2_ops,
  2454. },
  2455. },
  2456. };
  2457. static struct clk_branch gcc_sdcc4_apps_clk = {
  2458. .halt_reg = 0x16004,
  2459. .halt_check = BRANCH_HALT,
  2460. .clkr = {
  2461. .enable_reg = 0x16004,
  2462. .enable_mask = BIT(0),
  2463. .hw.init = &(struct clk_init_data){
  2464. .name = "gcc_sdcc4_apps_clk",
  2465. .parent_hws = (const struct clk_hw *[]){
  2466. &gcc_sdcc4_apps_clk_src.clkr.hw },
  2467. .num_parents = 1,
  2468. .flags = CLK_SET_RATE_PARENT,
  2469. .ops = &clk_branch2_ops,
  2470. },
  2471. },
  2472. };
  2473. static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
  2474. .halt_reg = 0x4819c,
  2475. .halt_check = BRANCH_HALT_VOTED,
  2476. .clkr = {
  2477. .enable_reg = 0x52004,
  2478. .enable_mask = BIT(0),
  2479. .hw.init = &(struct clk_init_data){
  2480. .name = "gcc_sys_noc_cpuss_ahb_clk",
  2481. .parent_hws = (const struct clk_hw *[]){
  2482. &gcc_cpuss_ahb_clk_src.clkr.hw },
  2483. .num_parents = 1,
  2484. /* required for cpuss */
  2485. .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
  2486. .ops = &clk_branch2_ops,
  2487. },
  2488. },
  2489. };
  2490. static struct clk_branch gcc_tsif_ahb_clk = {
  2491. .halt_reg = 0x36004,
  2492. .halt_check = BRANCH_HALT,
  2493. .clkr = {
  2494. .enable_reg = 0x36004,
  2495. .enable_mask = BIT(0),
  2496. .hw.init = &(struct clk_init_data){
  2497. .name = "gcc_tsif_ahb_clk",
  2498. .ops = &clk_branch2_ops,
  2499. },
  2500. },
  2501. };
  2502. static struct clk_branch gcc_tsif_inactivity_timers_clk = {
  2503. .halt_reg = 0x3600c,
  2504. .halt_check = BRANCH_HALT,
  2505. .clkr = {
  2506. .enable_reg = 0x3600c,
  2507. .enable_mask = BIT(0),
  2508. .hw.init = &(struct clk_init_data){
  2509. .name = "gcc_tsif_inactivity_timers_clk",
  2510. .ops = &clk_branch2_ops,
  2511. },
  2512. },
  2513. };
  2514. static struct clk_branch gcc_tsif_ref_clk = {
  2515. .halt_reg = 0x36008,
  2516. .halt_check = BRANCH_HALT,
  2517. .clkr = {
  2518. .enable_reg = 0x36008,
  2519. .enable_mask = BIT(0),
  2520. .hw.init = &(struct clk_init_data){
  2521. .name = "gcc_tsif_ref_clk",
  2522. .parent_hws = (const struct clk_hw *[]){
  2523. &gcc_tsif_ref_clk_src.clkr.hw },
  2524. .num_parents = 1,
  2525. .flags = CLK_SET_RATE_PARENT,
  2526. .ops = &clk_branch2_ops,
  2527. },
  2528. },
  2529. };
  2530. static struct clk_branch gcc_ufs_card_ahb_clk = {
  2531. .halt_reg = 0x75014,
  2532. .halt_check = BRANCH_HALT,
  2533. .hwcg_reg = 0x75014,
  2534. .hwcg_bit = 1,
  2535. .clkr = {
  2536. .enable_reg = 0x75014,
  2537. .enable_mask = BIT(0),
  2538. .hw.init = &(struct clk_init_data){
  2539. .name = "gcc_ufs_card_ahb_clk",
  2540. .ops = &clk_branch2_ops,
  2541. },
  2542. },
  2543. };
  2544. static struct clk_branch gcc_ufs_card_axi_clk = {
  2545. .halt_reg = 0x75010,
  2546. .halt_check = BRANCH_HALT,
  2547. .hwcg_reg = 0x75010,
  2548. .hwcg_bit = 1,
  2549. .clkr = {
  2550. .enable_reg = 0x75010,
  2551. .enable_mask = BIT(0),
  2552. .hw.init = &(struct clk_init_data){
  2553. .name = "gcc_ufs_card_axi_clk",
  2554. .parent_hws = (const struct clk_hw *[]){
  2555. &gcc_ufs_card_axi_clk_src.clkr.hw },
  2556. .num_parents = 1,
  2557. .flags = CLK_SET_RATE_PARENT,
  2558. .ops = &clk_branch2_ops,
  2559. },
  2560. },
  2561. };
  2562. static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
  2563. .halt_reg = 0x75010,
  2564. .halt_check = BRANCH_HALT,
  2565. .hwcg_reg = 0x75010,
  2566. .hwcg_bit = 1,
  2567. .clkr = {
  2568. .enable_reg = 0x75010,
  2569. .enable_mask = BIT(1),
  2570. .hw.init = &(struct clk_init_data){
  2571. .name = "gcc_ufs_card_axi_hw_ctl_clk",
  2572. .parent_hws = (const struct clk_hw *[]){
  2573. &gcc_ufs_card_axi_clk.clkr.hw },
  2574. .num_parents = 1,
  2575. .flags = CLK_SET_RATE_PARENT,
  2576. .ops = &clk_branch_simple_ops,
  2577. },
  2578. },
  2579. };
  2580. static struct clk_branch gcc_ufs_card_clkref_clk = {
  2581. .halt_reg = 0x8c004,
  2582. .halt_check = BRANCH_HALT,
  2583. .clkr = {
  2584. .enable_reg = 0x8c004,
  2585. .enable_mask = BIT(0),
  2586. .hw.init = &(struct clk_init_data){
  2587. .name = "gcc_ufs_card_clkref_clk",
  2588. .ops = &clk_branch2_ops,
  2589. },
  2590. },
  2591. };
  2592. static struct clk_branch gcc_ufs_card_ice_core_clk = {
  2593. .halt_reg = 0x7505c,
  2594. .halt_check = BRANCH_HALT,
  2595. .hwcg_reg = 0x7505c,
  2596. .hwcg_bit = 1,
  2597. .clkr = {
  2598. .enable_reg = 0x7505c,
  2599. .enable_mask = BIT(0),
  2600. .hw.init = &(struct clk_init_data){
  2601. .name = "gcc_ufs_card_ice_core_clk",
  2602. .parent_hws = (const struct clk_hw *[]){
  2603. &gcc_ufs_card_ice_core_clk_src.clkr.hw },
  2604. .num_parents = 1,
  2605. .flags = CLK_SET_RATE_PARENT,
  2606. .ops = &clk_branch2_ops,
  2607. },
  2608. },
  2609. };
  2610. static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
  2611. .halt_reg = 0x7505c,
  2612. .halt_check = BRANCH_HALT,
  2613. .hwcg_reg = 0x7505c,
  2614. .hwcg_bit = 1,
  2615. .clkr = {
  2616. .enable_reg = 0x7505c,
  2617. .enable_mask = BIT(1),
  2618. .hw.init = &(struct clk_init_data){
  2619. .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
  2620. .parent_hws = (const struct clk_hw *[]){
  2621. &gcc_ufs_card_ice_core_clk.clkr.hw },
  2622. .num_parents = 1,
  2623. .flags = CLK_SET_RATE_PARENT,
  2624. .ops = &clk_branch_simple_ops,
  2625. },
  2626. },
  2627. };
  2628. static struct clk_branch gcc_ufs_card_phy_aux_clk = {
  2629. .halt_reg = 0x75090,
  2630. .halt_check = BRANCH_HALT,
  2631. .hwcg_reg = 0x75090,
  2632. .hwcg_bit = 1,
  2633. .clkr = {
  2634. .enable_reg = 0x75090,
  2635. .enable_mask = BIT(0),
  2636. .hw.init = &(struct clk_init_data){
  2637. .name = "gcc_ufs_card_phy_aux_clk",
  2638. .parent_hws = (const struct clk_hw *[]){
  2639. &gcc_ufs_card_phy_aux_clk_src.clkr.hw },
  2640. .num_parents = 1,
  2641. .flags = CLK_SET_RATE_PARENT,
  2642. .ops = &clk_branch2_ops,
  2643. },
  2644. },
  2645. };
  2646. static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
  2647. .halt_reg = 0x75090,
  2648. .halt_check = BRANCH_HALT,
  2649. .hwcg_reg = 0x75090,
  2650. .hwcg_bit = 1,
  2651. .clkr = {
  2652. .enable_reg = 0x75090,
  2653. .enable_mask = BIT(1),
  2654. .hw.init = &(struct clk_init_data){
  2655. .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
  2656. .parent_hws = (const struct clk_hw *[]){
  2657. &gcc_ufs_card_phy_aux_clk.clkr.hw },
  2658. .num_parents = 1,
  2659. .flags = CLK_SET_RATE_PARENT,
  2660. .ops = &clk_branch_simple_ops,
  2661. },
  2662. },
  2663. };
  2664. /* external clocks so add BRANCH_HALT_SKIP */
  2665. static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
  2666. .halt_check = BRANCH_HALT_SKIP,
  2667. .clkr = {
  2668. .enable_reg = 0x7501c,
  2669. .enable_mask = BIT(0),
  2670. .hw.init = &(struct clk_init_data){
  2671. .name = "gcc_ufs_card_rx_symbol_0_clk",
  2672. .ops = &clk_branch2_ops,
  2673. },
  2674. },
  2675. };
  2676. /* external clocks so add BRANCH_HALT_SKIP */
  2677. static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
  2678. .halt_check = BRANCH_HALT_SKIP,
  2679. .clkr = {
  2680. .enable_reg = 0x750ac,
  2681. .enable_mask = BIT(0),
  2682. .hw.init = &(struct clk_init_data){
  2683. .name = "gcc_ufs_card_rx_symbol_1_clk",
  2684. .ops = &clk_branch2_ops,
  2685. },
  2686. },
  2687. };
  2688. /* external clocks so add BRANCH_HALT_SKIP */
  2689. static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
  2690. .halt_check = BRANCH_HALT_SKIP,
  2691. .clkr = {
  2692. .enable_reg = 0x75018,
  2693. .enable_mask = BIT(0),
  2694. .hw.init = &(struct clk_init_data){
  2695. .name = "gcc_ufs_card_tx_symbol_0_clk",
  2696. .ops = &clk_branch2_ops,
  2697. },
  2698. },
  2699. };
  2700. static struct clk_branch gcc_ufs_card_unipro_core_clk = {
  2701. .halt_reg = 0x75058,
  2702. .halt_check = BRANCH_HALT,
  2703. .hwcg_reg = 0x75058,
  2704. .hwcg_bit = 1,
  2705. .clkr = {
  2706. .enable_reg = 0x75058,
  2707. .enable_mask = BIT(0),
  2708. .hw.init = &(struct clk_init_data){
  2709. .name = "gcc_ufs_card_unipro_core_clk",
  2710. .parent_hws = (const struct clk_hw *[]){
  2711. &gcc_ufs_card_unipro_core_clk_src.clkr.hw },
  2712. .num_parents = 1,
  2713. .flags = CLK_SET_RATE_PARENT,
  2714. .ops = &clk_branch2_ops,
  2715. },
  2716. },
  2717. };
  2718. static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
  2719. .halt_reg = 0x75058,
  2720. .halt_check = BRANCH_HALT,
  2721. .hwcg_reg = 0x75058,
  2722. .hwcg_bit = 1,
  2723. .clkr = {
  2724. .enable_reg = 0x75058,
  2725. .enable_mask = BIT(1),
  2726. .hw.init = &(struct clk_init_data){
  2727. .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
  2728. .parent_hws = (const struct clk_hw *[]){
  2729. &gcc_ufs_card_unipro_core_clk.clkr.hw },
  2730. .num_parents = 1,
  2731. .flags = CLK_SET_RATE_PARENT,
  2732. .ops = &clk_branch_simple_ops,
  2733. },
  2734. },
  2735. };
  2736. static struct clk_branch gcc_ufs_mem_clkref_clk = {
  2737. .halt_reg = 0x8c000,
  2738. .halt_check = BRANCH_HALT,
  2739. .clkr = {
  2740. .enable_reg = 0x8c000,
  2741. .enable_mask = BIT(0),
  2742. .hw.init = &(struct clk_init_data){
  2743. .name = "gcc_ufs_mem_clkref_clk",
  2744. .ops = &clk_branch2_ops,
  2745. },
  2746. },
  2747. };
  2748. static struct clk_branch gcc_ufs_phy_ahb_clk = {
  2749. .halt_reg = 0x77014,
  2750. .halt_check = BRANCH_HALT,
  2751. .hwcg_reg = 0x77014,
  2752. .hwcg_bit = 1,
  2753. .clkr = {
  2754. .enable_reg = 0x77014,
  2755. .enable_mask = BIT(0),
  2756. .hw.init = &(struct clk_init_data){
  2757. .name = "gcc_ufs_phy_ahb_clk",
  2758. .ops = &clk_branch2_ops,
  2759. },
  2760. },
  2761. };
  2762. static struct clk_branch gcc_ufs_phy_axi_clk = {
  2763. .halt_reg = 0x77010,
  2764. .halt_check = BRANCH_HALT,
  2765. .hwcg_reg = 0x77010,
  2766. .hwcg_bit = 1,
  2767. .clkr = {
  2768. .enable_reg = 0x77010,
  2769. .enable_mask = BIT(0),
  2770. .hw.init = &(struct clk_init_data){
  2771. .name = "gcc_ufs_phy_axi_clk",
  2772. .parent_hws = (const struct clk_hw *[]){
  2773. &gcc_ufs_phy_axi_clk_src.clkr.hw },
  2774. .num_parents = 1,
  2775. .flags = CLK_SET_RATE_PARENT,
  2776. .ops = &clk_branch2_ops,
  2777. },
  2778. },
  2779. };
  2780. static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
  2781. .halt_reg = 0x77010,
  2782. .halt_check = BRANCH_HALT,
  2783. .hwcg_reg = 0x77010,
  2784. .hwcg_bit = 1,
  2785. .clkr = {
  2786. .enable_reg = 0x77010,
  2787. .enable_mask = BIT(1),
  2788. .hw.init = &(struct clk_init_data){
  2789. .name = "gcc_ufs_phy_axi_hw_ctl_clk",
  2790. .parent_hws = (const struct clk_hw *[]){
  2791. &gcc_ufs_phy_axi_clk.clkr.hw },
  2792. .num_parents = 1,
  2793. .flags = CLK_SET_RATE_PARENT,
  2794. .ops = &clk_branch_simple_ops,
  2795. },
  2796. },
  2797. };
  2798. static struct clk_branch gcc_ufs_phy_ice_core_clk = {
  2799. .halt_reg = 0x7705c,
  2800. .halt_check = BRANCH_HALT,
  2801. .hwcg_reg = 0x7705c,
  2802. .hwcg_bit = 1,
  2803. .clkr = {
  2804. .enable_reg = 0x7705c,
  2805. .enable_mask = BIT(0),
  2806. .hw.init = &(struct clk_init_data){
  2807. .name = "gcc_ufs_phy_ice_core_clk",
  2808. .parent_hws = (const struct clk_hw *[]){
  2809. &gcc_ufs_phy_ice_core_clk_src.clkr.hw },
  2810. .num_parents = 1,
  2811. .flags = CLK_SET_RATE_PARENT,
  2812. .ops = &clk_branch2_ops,
  2813. },
  2814. },
  2815. };
  2816. static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
  2817. .halt_reg = 0x7705c,
  2818. .halt_check = BRANCH_HALT,
  2819. .hwcg_reg = 0x7705c,
  2820. .hwcg_bit = 1,
  2821. .clkr = {
  2822. .enable_reg = 0x7705c,
  2823. .enable_mask = BIT(1),
  2824. .hw.init = &(struct clk_init_data){
  2825. .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
  2826. .parent_hws = (const struct clk_hw *[]){
  2827. &gcc_ufs_phy_ice_core_clk.clkr.hw },
  2828. .num_parents = 1,
  2829. .flags = CLK_SET_RATE_PARENT,
  2830. .ops = &clk_branch_simple_ops,
  2831. },
  2832. },
  2833. };
  2834. static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
  2835. .halt_reg = 0x77090,
  2836. .halt_check = BRANCH_HALT,
  2837. .hwcg_reg = 0x77090,
  2838. .hwcg_bit = 1,
  2839. .clkr = {
  2840. .enable_reg = 0x77090,
  2841. .enable_mask = BIT(0),
  2842. .hw.init = &(struct clk_init_data){
  2843. .name = "gcc_ufs_phy_phy_aux_clk",
  2844. .parent_hws = (const struct clk_hw *[]){
  2845. &gcc_ufs_phy_phy_aux_clk_src.clkr.hw },
  2846. .num_parents = 1,
  2847. .flags = CLK_SET_RATE_PARENT,
  2848. .ops = &clk_branch2_ops,
  2849. },
  2850. },
  2851. };
  2852. static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
  2853. .halt_reg = 0x77090,
  2854. .halt_check = BRANCH_HALT,
  2855. .hwcg_reg = 0x77090,
  2856. .hwcg_bit = 1,
  2857. .clkr = {
  2858. .enable_reg = 0x77090,
  2859. .enable_mask = BIT(1),
  2860. .hw.init = &(struct clk_init_data){
  2861. .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
  2862. .parent_hws = (const struct clk_hw *[]){
  2863. &gcc_ufs_phy_phy_aux_clk.clkr.hw },
  2864. .num_parents = 1,
  2865. .flags = CLK_SET_RATE_PARENT,
  2866. .ops = &clk_branch_simple_ops,
  2867. },
  2868. },
  2869. };
  2870. /* external clocks so add BRANCH_HALT_SKIP */
  2871. static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
  2872. .halt_check = BRANCH_HALT_SKIP,
  2873. .clkr = {
  2874. .enable_reg = 0x7701c,
  2875. .enable_mask = BIT(0),
  2876. .hw.init = &(struct clk_init_data){
  2877. .name = "gcc_ufs_phy_rx_symbol_0_clk",
  2878. .ops = &clk_branch2_ops,
  2879. },
  2880. },
  2881. };
  2882. /* external clocks so add BRANCH_HALT_SKIP */
  2883. static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
  2884. .halt_check = BRANCH_HALT_SKIP,
  2885. .clkr = {
  2886. .enable_reg = 0x770ac,
  2887. .enable_mask = BIT(0),
  2888. .hw.init = &(struct clk_init_data){
  2889. .name = "gcc_ufs_phy_rx_symbol_1_clk",
  2890. .ops = &clk_branch2_ops,
  2891. },
  2892. },
  2893. };
  2894. /* external clocks so add BRANCH_HALT_SKIP */
  2895. static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
  2896. .halt_check = BRANCH_HALT_SKIP,
  2897. .clkr = {
  2898. .enable_reg = 0x77018,
  2899. .enable_mask = BIT(0),
  2900. .hw.init = &(struct clk_init_data){
  2901. .name = "gcc_ufs_phy_tx_symbol_0_clk",
  2902. .ops = &clk_branch2_ops,
  2903. },
  2904. },
  2905. };
  2906. static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
  2907. .halt_reg = 0x77058,
  2908. .halt_check = BRANCH_HALT,
  2909. .hwcg_reg = 0x77058,
  2910. .hwcg_bit = 1,
  2911. .clkr = {
  2912. .enable_reg = 0x77058,
  2913. .enable_mask = BIT(0),
  2914. .hw.init = &(struct clk_init_data){
  2915. .name = "gcc_ufs_phy_unipro_core_clk",
  2916. .parent_hws = (const struct clk_hw *[]){
  2917. &gcc_ufs_phy_unipro_core_clk_src.clkr.hw },
  2918. .num_parents = 1,
  2919. .flags = CLK_SET_RATE_PARENT,
  2920. .ops = &clk_branch2_ops,
  2921. },
  2922. },
  2923. };
  2924. static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
  2925. .halt_reg = 0x77058,
  2926. .halt_check = BRANCH_HALT,
  2927. .hwcg_reg = 0x77058,
  2928. .hwcg_bit = 1,
  2929. .clkr = {
  2930. .enable_reg = 0x77058,
  2931. .enable_mask = BIT(1),
  2932. .hw.init = &(struct clk_init_data){
  2933. .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
  2934. .parent_hws = (const struct clk_hw *[]){
  2935. &gcc_ufs_phy_unipro_core_clk.clkr.hw },
  2936. .num_parents = 1,
  2937. .flags = CLK_SET_RATE_PARENT,
  2938. .ops = &clk_branch_simple_ops,
  2939. },
  2940. },
  2941. };
  2942. static struct clk_branch gcc_usb30_prim_master_clk = {
  2943. .halt_reg = 0xf010,
  2944. .halt_check = BRANCH_HALT,
  2945. .clkr = {
  2946. .enable_reg = 0xf010,
  2947. .enable_mask = BIT(0),
  2948. .hw.init = &(struct clk_init_data){
  2949. .name = "gcc_usb30_prim_master_clk",
  2950. .parent_hws = (const struct clk_hw *[]){
  2951. &gcc_usb30_prim_master_clk_src.clkr.hw },
  2952. .num_parents = 1,
  2953. .flags = CLK_SET_RATE_PARENT,
  2954. .ops = &clk_branch2_ops,
  2955. },
  2956. },
  2957. };
  2958. static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
  2959. .halt_reg = 0xf018,
  2960. .halt_check = BRANCH_HALT,
  2961. .clkr = {
  2962. .enable_reg = 0xf018,
  2963. .enable_mask = BIT(0),
  2964. .hw.init = &(struct clk_init_data){
  2965. .name = "gcc_usb30_prim_mock_utmi_clk",
  2966. .parent_hws = (const struct clk_hw *[]){
  2967. &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
  2968. .num_parents = 1,
  2969. .flags = CLK_SET_RATE_PARENT,
  2970. .ops = &clk_branch2_ops,
  2971. },
  2972. },
  2973. };
  2974. static struct clk_branch gcc_usb30_prim_sleep_clk = {
  2975. .halt_reg = 0xf014,
  2976. .halt_check = BRANCH_HALT,
  2977. .clkr = {
  2978. .enable_reg = 0xf014,
  2979. .enable_mask = BIT(0),
  2980. .hw.init = &(struct clk_init_data){
  2981. .name = "gcc_usb30_prim_sleep_clk",
  2982. .ops = &clk_branch2_ops,
  2983. },
  2984. },
  2985. };
  2986. static struct clk_branch gcc_usb30_sec_master_clk = {
  2987. .halt_reg = 0x10010,
  2988. .halt_check = BRANCH_HALT,
  2989. .clkr = {
  2990. .enable_reg = 0x10010,
  2991. .enable_mask = BIT(0),
  2992. .hw.init = &(struct clk_init_data){
  2993. .name = "gcc_usb30_sec_master_clk",
  2994. .parent_hws = (const struct clk_hw *[]){
  2995. &gcc_usb30_sec_master_clk_src.clkr.hw },
  2996. .num_parents = 1,
  2997. .flags = CLK_SET_RATE_PARENT,
  2998. .ops = &clk_branch2_ops,
  2999. },
  3000. },
  3001. };
  3002. static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
  3003. .halt_reg = 0x10018,
  3004. .halt_check = BRANCH_HALT,
  3005. .clkr = {
  3006. .enable_reg = 0x10018,
  3007. .enable_mask = BIT(0),
  3008. .hw.init = &(struct clk_init_data){
  3009. .name = "gcc_usb30_sec_mock_utmi_clk",
  3010. .parent_hws = (const struct clk_hw *[]){
  3011. &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw },
  3012. .num_parents = 1,
  3013. .flags = CLK_SET_RATE_PARENT,
  3014. .ops = &clk_branch2_ops,
  3015. },
  3016. },
  3017. };
  3018. static struct clk_branch gcc_usb30_sec_sleep_clk = {
  3019. .halt_reg = 0x10014,
  3020. .halt_check = BRANCH_HALT,
  3021. .clkr = {
  3022. .enable_reg = 0x10014,
  3023. .enable_mask = BIT(0),
  3024. .hw.init = &(struct clk_init_data){
  3025. .name = "gcc_usb30_sec_sleep_clk",
  3026. .ops = &clk_branch2_ops,
  3027. },
  3028. },
  3029. };
  3030. static struct clk_branch gcc_usb3_prim_clkref_clk = {
  3031. .halt_reg = 0x8c008,
  3032. .halt_check = BRANCH_HALT,
  3033. .clkr = {
  3034. .enable_reg = 0x8c008,
  3035. .enable_mask = BIT(0),
  3036. .hw.init = &(struct clk_init_data){
  3037. .name = "gcc_usb3_prim_clkref_clk",
  3038. .ops = &clk_branch2_ops,
  3039. },
  3040. },
  3041. };
  3042. static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
  3043. .halt_reg = 0xf050,
  3044. .halt_check = BRANCH_HALT,
  3045. .clkr = {
  3046. .enable_reg = 0xf050,
  3047. .enable_mask = BIT(0),
  3048. .hw.init = &(struct clk_init_data){
  3049. .name = "gcc_usb3_prim_phy_aux_clk",
  3050. .parent_hws = (const struct clk_hw *[]){
  3051. &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
  3052. .num_parents = 1,
  3053. .flags = CLK_SET_RATE_PARENT,
  3054. .ops = &clk_branch2_ops,
  3055. },
  3056. },
  3057. };
  3058. static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
  3059. .halt_reg = 0xf054,
  3060. .halt_check = BRANCH_HALT,
  3061. .clkr = {
  3062. .enable_reg = 0xf054,
  3063. .enable_mask = BIT(0),
  3064. .hw.init = &(struct clk_init_data){
  3065. .name = "gcc_usb3_prim_phy_com_aux_clk",
  3066. .parent_hws = (const struct clk_hw *[]){
  3067. &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
  3068. .num_parents = 1,
  3069. .flags = CLK_SET_RATE_PARENT,
  3070. .ops = &clk_branch2_ops,
  3071. },
  3072. },
  3073. };
  3074. static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
  3075. .halt_check = BRANCH_HALT_SKIP,
  3076. .clkr = {
  3077. .enable_reg = 0xf058,
  3078. .enable_mask = BIT(0),
  3079. .hw.init = &(struct clk_init_data){
  3080. .name = "gcc_usb3_prim_phy_pipe_clk",
  3081. .ops = &clk_branch2_ops,
  3082. },
  3083. },
  3084. };
  3085. static struct clk_branch gcc_usb3_sec_clkref_clk = {
  3086. .halt_reg = 0x8c028,
  3087. .halt_check = BRANCH_HALT,
  3088. .clkr = {
  3089. .enable_reg = 0x8c028,
  3090. .enable_mask = BIT(0),
  3091. .hw.init = &(struct clk_init_data){
  3092. .name = "gcc_usb3_sec_clkref_clk",
  3093. .ops = &clk_branch2_ops,
  3094. },
  3095. },
  3096. };
  3097. static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
  3098. .halt_reg = 0x10050,
  3099. .halt_check = BRANCH_HALT,
  3100. .clkr = {
  3101. .enable_reg = 0x10050,
  3102. .enable_mask = BIT(0),
  3103. .hw.init = &(struct clk_init_data){
  3104. .name = "gcc_usb3_sec_phy_aux_clk",
  3105. .parent_hws = (const struct clk_hw *[]){
  3106. &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
  3107. .num_parents = 1,
  3108. .flags = CLK_SET_RATE_PARENT,
  3109. .ops = &clk_branch2_ops,
  3110. },
  3111. },
  3112. };
  3113. static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
  3114. .halt_reg = 0x10054,
  3115. .halt_check = BRANCH_HALT,
  3116. .clkr = {
  3117. .enable_reg = 0x10054,
  3118. .enable_mask = BIT(0),
  3119. .hw.init = &(struct clk_init_data){
  3120. .name = "gcc_usb3_sec_phy_com_aux_clk",
  3121. .parent_hws = (const struct clk_hw *[]){
  3122. &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
  3123. .num_parents = 1,
  3124. .flags = CLK_SET_RATE_PARENT,
  3125. .ops = &clk_branch2_ops,
  3126. },
  3127. },
  3128. };
  3129. static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
  3130. .halt_check = BRANCH_HALT_SKIP,
  3131. .clkr = {
  3132. .enable_reg = 0x10058,
  3133. .enable_mask = BIT(0),
  3134. .hw.init = &(struct clk_init_data){
  3135. .name = "gcc_usb3_sec_phy_pipe_clk",
  3136. .ops = &clk_branch2_ops,
  3137. },
  3138. },
  3139. };
  3140. /*
  3141. * Clock ON depends on external parent 'config noc', so cant poll
  3142. * delay and also mark as crtitical for video boot
  3143. */
  3144. static struct clk_branch gcc_video_ahb_clk = {
  3145. .halt_reg = 0xb004,
  3146. .halt_check = BRANCH_HALT_DELAY,
  3147. .hwcg_reg = 0xb004,
  3148. .hwcg_bit = 1,
  3149. .clkr = {
  3150. .enable_reg = 0xb004,
  3151. .enable_mask = BIT(0),
  3152. .hw.init = &(struct clk_init_data){
  3153. .name = "gcc_video_ahb_clk",
  3154. .flags = CLK_IS_CRITICAL,
  3155. .ops = &clk_branch2_ops,
  3156. },
  3157. },
  3158. };
  3159. static struct clk_branch gcc_video_axi0_clk = {
  3160. .halt_reg = 0xb024,
  3161. .halt_check = BRANCH_HALT,
  3162. .clkr = {
  3163. .enable_reg = 0xb024,
  3164. .enable_mask = BIT(0),
  3165. .hw.init = &(struct clk_init_data){
  3166. .name = "gcc_video_axi0_clk",
  3167. .ops = &clk_branch2_ops,
  3168. },
  3169. },
  3170. };
  3171. static struct clk_branch gcc_video_axi1_clk = {
  3172. .halt_reg = 0xb028,
  3173. .halt_check = BRANCH_HALT,
  3174. .clkr = {
  3175. .enable_reg = 0xb028,
  3176. .enable_mask = BIT(0),
  3177. .hw.init = &(struct clk_init_data){
  3178. .name = "gcc_video_axi1_clk",
  3179. .ops = &clk_branch2_ops,
  3180. },
  3181. },
  3182. };
  3183. static struct clk_branch gcc_video_axic_clk = {
  3184. .halt_reg = 0xb02c,
  3185. .halt_check = BRANCH_HALT,
  3186. .clkr = {
  3187. .enable_reg = 0xb02c,
  3188. .enable_mask = BIT(0),
  3189. .hw.init = &(struct clk_init_data){
  3190. .name = "gcc_video_axic_clk",
  3191. .ops = &clk_branch2_ops,
  3192. },
  3193. },
  3194. };
  3195. /* XO critical input to video, so no need to poll */
  3196. static struct clk_branch gcc_video_xo_clk = {
  3197. .halt_reg = 0xb040,
  3198. .halt_check = BRANCH_HALT_DELAY,
  3199. .clkr = {
  3200. .enable_reg = 0xb040,
  3201. .enable_mask = BIT(0),
  3202. .hw.init = &(struct clk_init_data){
  3203. .name = "gcc_video_xo_clk",
  3204. .flags = CLK_IS_CRITICAL,
  3205. .ops = &clk_branch2_ops,
  3206. },
  3207. },
  3208. };
  3209. static struct gdsc usb30_prim_gdsc = {
  3210. .gdscr = 0xf004,
  3211. .pd = {
  3212. .name = "usb30_prim_gdsc",
  3213. },
  3214. .pwrsts = PWRSTS_OFF_ON,
  3215. .flags = POLL_CFG_GDSCR,
  3216. };
  3217. static struct gdsc usb30_sec_gdsc = {
  3218. .gdscr = 0x10004,
  3219. .pd = {
  3220. .name = "usb30_sec_gdsc",
  3221. },
  3222. .pwrsts = PWRSTS_OFF_ON,
  3223. .flags = POLL_CFG_GDSCR,
  3224. };
  3225. static struct clk_regmap *gcc_sm8150_clocks[] = {
  3226. [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
  3227. [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
  3228. [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] =
  3229. &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
  3230. [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
  3231. [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
  3232. &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
  3233. [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
  3234. [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
  3235. [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
  3236. [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
  3237. [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
  3238. [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
  3239. [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
  3240. [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
  3241. [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
  3242. [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
  3243. [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
  3244. [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
  3245. [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
  3246. [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
  3247. [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
  3248. [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
  3249. [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
  3250. [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
  3251. [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
  3252. [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
  3253. [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
  3254. [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
  3255. [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
  3256. [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
  3257. [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
  3258. [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
  3259. [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
  3260. [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
  3261. [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
  3262. [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
  3263. [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
  3264. [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
  3265. [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
  3266. [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
  3267. [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
  3268. [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
  3269. [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
  3270. [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
  3271. [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
  3272. [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
  3273. [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
  3274. [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
  3275. [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
  3276. [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
  3277. [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
  3278. [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
  3279. [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
  3280. [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
  3281. [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
  3282. [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
  3283. [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
  3284. [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
  3285. [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
  3286. [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
  3287. [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
  3288. [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
  3289. [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
  3290. [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
  3291. [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
  3292. [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
  3293. [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
  3294. [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
  3295. [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
  3296. [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
  3297. [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
  3298. [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
  3299. [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
  3300. [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
  3301. [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
  3302. [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
  3303. [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
  3304. [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
  3305. [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
  3306. [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
  3307. [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
  3308. [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
  3309. [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
  3310. [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
  3311. [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
  3312. [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
  3313. [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
  3314. [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
  3315. [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
  3316. [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
  3317. [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
  3318. [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
  3319. [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
  3320. [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
  3321. [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
  3322. [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
  3323. [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
  3324. [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
  3325. [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
  3326. [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
  3327. [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
  3328. [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
  3329. [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
  3330. [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
  3331. [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
  3332. [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
  3333. [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
  3334. [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
  3335. [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
  3336. [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
  3337. [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
  3338. [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
  3339. [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
  3340. [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
  3341. [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
  3342. [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
  3343. [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
  3344. [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
  3345. [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
  3346. [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
  3347. [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
  3348. [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
  3349. [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
  3350. [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
  3351. [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
  3352. [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
  3353. [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
  3354. [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
  3355. [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
  3356. [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
  3357. [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
  3358. [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
  3359. [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
  3360. [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
  3361. [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
  3362. [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
  3363. [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
  3364. [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
  3365. [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
  3366. [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
  3367. [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
  3368. [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
  3369. [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
  3370. [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
  3371. [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
  3372. [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
  3373. [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] =
  3374. &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
  3375. [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
  3376. [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
  3377. [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
  3378. &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
  3379. [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
  3380. [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
  3381. [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
  3382. [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
  3383. [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
  3384. &gcc_ufs_card_unipro_core_clk_src.clkr,
  3385. [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =
  3386. &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
  3387. [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
  3388. [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
  3389. [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
  3390. [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
  3391. [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
  3392. [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
  3393. [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
  3394. [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
  3395. &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
  3396. [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
  3397. [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
  3398. [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
  3399. [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
  3400. [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
  3401. [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
  3402. [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
  3403. [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
  3404. &gcc_ufs_phy_unipro_core_clk_src.clkr,
  3405. [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
  3406. &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
  3407. [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
  3408. [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
  3409. [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
  3410. [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
  3411. &gcc_usb30_prim_mock_utmi_clk_src.clkr,
  3412. [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
  3413. [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
  3414. [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
  3415. [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
  3416. [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
  3417. &gcc_usb30_sec_mock_utmi_clk_src.clkr,
  3418. [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
  3419. [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
  3420. [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
  3421. [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
  3422. [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
  3423. [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
  3424. [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
  3425. [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
  3426. [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
  3427. [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
  3428. [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
  3429. [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
  3430. [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
  3431. [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
  3432. [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
  3433. [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
  3434. [GPLL0] = &gpll0.clkr,
  3435. [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
  3436. [GPLL7] = &gpll7.clkr,
  3437. [GPLL9] = &gpll9.clkr,
  3438. };
  3439. static const struct qcom_reset_map gcc_sm8150_resets[] = {
  3440. [GCC_EMAC_BCR] = { 0x6000 },
  3441. [GCC_GPU_BCR] = { 0x71000 },
  3442. [GCC_MMSS_BCR] = { 0xb000 },
  3443. [GCC_NPU_BCR] = { 0x4d000 },
  3444. [GCC_PCIE_0_BCR] = { 0x6b000 },
  3445. [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
  3446. [GCC_PCIE_1_BCR] = { 0x8d000 },
  3447. [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
  3448. [GCC_PCIE_PHY_BCR] = { 0x6f000 },
  3449. [GCC_PDM_BCR] = { 0x33000 },
  3450. [GCC_PRNG_BCR] = { 0x34000 },
  3451. [GCC_QSPI_BCR] = { 0x24008 },
  3452. [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
  3453. [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
  3454. [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
  3455. [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
  3456. [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
  3457. [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
  3458. [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
  3459. [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
  3460. [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
  3461. [GCC_SDCC2_BCR] = { 0x14000 },
  3462. [GCC_SDCC4_BCR] = { 0x16000 },
  3463. [GCC_TSIF_BCR] = { 0x36000 },
  3464. [GCC_UFS_CARD_BCR] = { 0x75000 },
  3465. [GCC_UFS_PHY_BCR] = { 0x77000 },
  3466. [GCC_USB30_PRIM_BCR] = { 0xf000 },
  3467. [GCC_USB30_SEC_BCR] = { 0x10000 },
  3468. [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
  3469. };
  3470. static struct gdsc *gcc_sm8150_gdscs[] = {
  3471. [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
  3472. [USB30_SEC_GDSC] = &usb30_sec_gdsc,
  3473. };
  3474. static const struct regmap_config gcc_sm8150_regmap_config = {
  3475. .reg_bits = 32,
  3476. .reg_stride = 4,
  3477. .val_bits = 32,
  3478. .max_register = 0x9c040,
  3479. .fast_io = true,
  3480. };
  3481. static const struct qcom_cc_desc gcc_sm8150_desc = {
  3482. .config = &gcc_sm8150_regmap_config,
  3483. .clks = gcc_sm8150_clocks,
  3484. .num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
  3485. .resets = gcc_sm8150_resets,
  3486. .num_resets = ARRAY_SIZE(gcc_sm8150_resets),
  3487. .gdscs = gcc_sm8150_gdscs,
  3488. .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),
  3489. };
  3490. static const struct of_device_id gcc_sm8150_match_table[] = {
  3491. { .compatible = "qcom,gcc-sm8150" },
  3492. { }
  3493. };
  3494. MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
  3495. static int gcc_sm8150_probe(struct platform_device *pdev)
  3496. {
  3497. struct regmap *regmap;
  3498. regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
  3499. if (IS_ERR(regmap))
  3500. return PTR_ERR(regmap);
  3501. /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
  3502. regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
  3503. regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
  3504. return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
  3505. }
  3506. static struct platform_driver gcc_sm8150_driver = {
  3507. .probe = gcc_sm8150_probe,
  3508. .driver = {
  3509. .name = "gcc-sm8150",
  3510. .of_match_table = gcc_sm8150_match_table,
  3511. },
  3512. };
  3513. static int __init gcc_sm8150_init(void)
  3514. {
  3515. return platform_driver_register(&gcc_sm8150_driver);
  3516. }
  3517. subsys_initcall(gcc_sm8150_init);
  3518. static void __exit gcc_sm8150_exit(void)
  3519. {
  3520. platform_driver_unregister(&gcc_sm8150_driver);
  3521. }
  3522. module_exit(gcc_sm8150_exit);
  3523. MODULE_DESCRIPTION("QTI GCC SM8150 Driver");
  3524. MODULE_LICENSE("GPL v2");