gcc-msm8960.c 79 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/bitops.h>
  7. #include <linux/err.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/regmap.h>
  14. #include <linux/reset-controller.h>
  15. #include <dt-bindings/clock/qcom,gcc-msm8960.h>
  16. #include <dt-bindings/reset/qcom,gcc-msm8960.h>
  17. #include "common.h"
  18. #include "clk-regmap.h"
  19. #include "clk-pll.h"
  20. #include "clk-rcg.h"
  21. #include "clk-branch.h"
  22. #include "clk-hfpll.h"
  23. #include "reset.h"
  24. static struct clk_pll pll3 = {
  25. .l_reg = 0x3164,
  26. .m_reg = 0x3168,
  27. .n_reg = 0x316c,
  28. .config_reg = 0x3174,
  29. .mode_reg = 0x3160,
  30. .status_reg = 0x3178,
  31. .status_bit = 16,
  32. .clkr.hw.init = &(struct clk_init_data){
  33. .name = "pll3",
  34. .parent_names = (const char *[]){ "pxo" },
  35. .num_parents = 1,
  36. .ops = &clk_pll_ops,
  37. },
  38. };
  39. static struct clk_regmap pll4_vote = {
  40. .enable_reg = 0x34c0,
  41. .enable_mask = BIT(4),
  42. .hw.init = &(struct clk_init_data){
  43. .name = "pll4_vote",
  44. .parent_names = (const char *[]){ "pll4" },
  45. .num_parents = 1,
  46. .ops = &clk_pll_vote_ops,
  47. },
  48. };
  49. static struct clk_pll pll8 = {
  50. .l_reg = 0x3144,
  51. .m_reg = 0x3148,
  52. .n_reg = 0x314c,
  53. .config_reg = 0x3154,
  54. .mode_reg = 0x3140,
  55. .status_reg = 0x3158,
  56. .status_bit = 16,
  57. .clkr.hw.init = &(struct clk_init_data){
  58. .name = "pll8",
  59. .parent_names = (const char *[]){ "pxo" },
  60. .num_parents = 1,
  61. .ops = &clk_pll_ops,
  62. },
  63. };
  64. static struct clk_regmap pll8_vote = {
  65. .enable_reg = 0x34c0,
  66. .enable_mask = BIT(8),
  67. .hw.init = &(struct clk_init_data){
  68. .name = "pll8_vote",
  69. .parent_names = (const char *[]){ "pll8" },
  70. .num_parents = 1,
  71. .ops = &clk_pll_vote_ops,
  72. },
  73. };
  74. static struct hfpll_data hfpll0_data = {
  75. .mode_reg = 0x3200,
  76. .l_reg = 0x3208,
  77. .m_reg = 0x320c,
  78. .n_reg = 0x3210,
  79. .config_reg = 0x3204,
  80. .status_reg = 0x321c,
  81. .config_val = 0x7845c665,
  82. .droop_reg = 0x3214,
  83. .droop_val = 0x0108c000,
  84. .min_rate = 600000000UL,
  85. .max_rate = 1800000000UL,
  86. };
  87. static struct clk_hfpll hfpll0 = {
  88. .d = &hfpll0_data,
  89. .clkr.hw.init = &(struct clk_init_data){
  90. .parent_names = (const char *[]){ "pxo" },
  91. .num_parents = 1,
  92. .name = "hfpll0",
  93. .ops = &clk_ops_hfpll,
  94. .flags = CLK_IGNORE_UNUSED,
  95. },
  96. .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
  97. };
  98. static struct hfpll_data hfpll1_8064_data = {
  99. .mode_reg = 0x3240,
  100. .l_reg = 0x3248,
  101. .m_reg = 0x324c,
  102. .n_reg = 0x3250,
  103. .config_reg = 0x3244,
  104. .status_reg = 0x325c,
  105. .config_val = 0x7845c665,
  106. .droop_reg = 0x3254,
  107. .droop_val = 0x0108c000,
  108. .min_rate = 600000000UL,
  109. .max_rate = 1800000000UL,
  110. };
  111. static struct hfpll_data hfpll1_data = {
  112. .mode_reg = 0x3300,
  113. .l_reg = 0x3308,
  114. .m_reg = 0x330c,
  115. .n_reg = 0x3310,
  116. .config_reg = 0x3304,
  117. .status_reg = 0x331c,
  118. .config_val = 0x7845c665,
  119. .droop_reg = 0x3314,
  120. .droop_val = 0x0108c000,
  121. .min_rate = 600000000UL,
  122. .max_rate = 1800000000UL,
  123. };
  124. static struct clk_hfpll hfpll1 = {
  125. .d = &hfpll1_data,
  126. .clkr.hw.init = &(struct clk_init_data){
  127. .parent_names = (const char *[]){ "pxo" },
  128. .num_parents = 1,
  129. .name = "hfpll1",
  130. .ops = &clk_ops_hfpll,
  131. .flags = CLK_IGNORE_UNUSED,
  132. },
  133. .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
  134. };
  135. static struct hfpll_data hfpll2_data = {
  136. .mode_reg = 0x3280,
  137. .l_reg = 0x3288,
  138. .m_reg = 0x328c,
  139. .n_reg = 0x3290,
  140. .config_reg = 0x3284,
  141. .status_reg = 0x329c,
  142. .config_val = 0x7845c665,
  143. .droop_reg = 0x3294,
  144. .droop_val = 0x0108c000,
  145. .min_rate = 600000000UL,
  146. .max_rate = 1800000000UL,
  147. };
  148. static struct clk_hfpll hfpll2 = {
  149. .d = &hfpll2_data,
  150. .clkr.hw.init = &(struct clk_init_data){
  151. .parent_names = (const char *[]){ "pxo" },
  152. .num_parents = 1,
  153. .name = "hfpll2",
  154. .ops = &clk_ops_hfpll,
  155. .flags = CLK_IGNORE_UNUSED,
  156. },
  157. .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
  158. };
  159. static struct hfpll_data hfpll3_data = {
  160. .mode_reg = 0x32c0,
  161. .l_reg = 0x32c8,
  162. .m_reg = 0x32cc,
  163. .n_reg = 0x32d0,
  164. .config_reg = 0x32c4,
  165. .status_reg = 0x32dc,
  166. .config_val = 0x7845c665,
  167. .droop_reg = 0x32d4,
  168. .droop_val = 0x0108c000,
  169. .min_rate = 600000000UL,
  170. .max_rate = 1800000000UL,
  171. };
  172. static struct clk_hfpll hfpll3 = {
  173. .d = &hfpll3_data,
  174. .clkr.hw.init = &(struct clk_init_data){
  175. .parent_names = (const char *[]){ "pxo" },
  176. .num_parents = 1,
  177. .name = "hfpll3",
  178. .ops = &clk_ops_hfpll,
  179. .flags = CLK_IGNORE_UNUSED,
  180. },
  181. .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
  182. };
  183. static struct hfpll_data hfpll_l2_8064_data = {
  184. .mode_reg = 0x3300,
  185. .l_reg = 0x3308,
  186. .m_reg = 0x330c,
  187. .n_reg = 0x3310,
  188. .config_reg = 0x3304,
  189. .status_reg = 0x331c,
  190. .config_val = 0x7845c665,
  191. .droop_reg = 0x3314,
  192. .droop_val = 0x0108c000,
  193. .min_rate = 600000000UL,
  194. .max_rate = 1800000000UL,
  195. };
  196. static struct hfpll_data hfpll_l2_data = {
  197. .mode_reg = 0x3400,
  198. .l_reg = 0x3408,
  199. .m_reg = 0x340c,
  200. .n_reg = 0x3410,
  201. .config_reg = 0x3404,
  202. .status_reg = 0x341c,
  203. .config_val = 0x7845c665,
  204. .droop_reg = 0x3414,
  205. .droop_val = 0x0108c000,
  206. .min_rate = 600000000UL,
  207. .max_rate = 1800000000UL,
  208. };
  209. static struct clk_hfpll hfpll_l2 = {
  210. .d = &hfpll_l2_data,
  211. .clkr.hw.init = &(struct clk_init_data){
  212. .parent_names = (const char *[]){ "pxo" },
  213. .num_parents = 1,
  214. .name = "hfpll_l2",
  215. .ops = &clk_ops_hfpll,
  216. .flags = CLK_IGNORE_UNUSED,
  217. },
  218. .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
  219. };
  220. static struct clk_pll pll14 = {
  221. .l_reg = 0x31c4,
  222. .m_reg = 0x31c8,
  223. .n_reg = 0x31cc,
  224. .config_reg = 0x31d4,
  225. .mode_reg = 0x31c0,
  226. .status_reg = 0x31d8,
  227. .status_bit = 16,
  228. .clkr.hw.init = &(struct clk_init_data){
  229. .name = "pll14",
  230. .parent_names = (const char *[]){ "pxo" },
  231. .num_parents = 1,
  232. .ops = &clk_pll_ops,
  233. },
  234. };
  235. static struct clk_regmap pll14_vote = {
  236. .enable_reg = 0x34c0,
  237. .enable_mask = BIT(14),
  238. .hw.init = &(struct clk_init_data){
  239. .name = "pll14_vote",
  240. .parent_names = (const char *[]){ "pll14" },
  241. .num_parents = 1,
  242. .ops = &clk_pll_vote_ops,
  243. },
  244. };
  245. enum {
  246. P_PXO,
  247. P_PLL8,
  248. P_PLL3,
  249. P_CXO,
  250. };
  251. static const struct parent_map gcc_pxo_pll8_map[] = {
  252. { P_PXO, 0 },
  253. { P_PLL8, 3 }
  254. };
  255. static const char * const gcc_pxo_pll8[] = {
  256. "pxo",
  257. "pll8_vote",
  258. };
  259. static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
  260. { P_PXO, 0 },
  261. { P_PLL8, 3 },
  262. { P_CXO, 5 }
  263. };
  264. static const char * const gcc_pxo_pll8_cxo[] = {
  265. "pxo",
  266. "pll8_vote",
  267. "cxo",
  268. };
  269. static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
  270. { P_PXO, 0 },
  271. { P_PLL8, 3 },
  272. { P_PLL3, 6 }
  273. };
  274. static const char * const gcc_pxo_pll8_pll3[] = {
  275. "pxo",
  276. "pll8_vote",
  277. "pll3",
  278. };
  279. static struct freq_tbl clk_tbl_gsbi_uart[] = {
  280. { 1843200, P_PLL8, 2, 6, 625 },
  281. { 3686400, P_PLL8, 2, 12, 625 },
  282. { 7372800, P_PLL8, 2, 24, 625 },
  283. { 14745600, P_PLL8, 2, 48, 625 },
  284. { 16000000, P_PLL8, 4, 1, 6 },
  285. { 24000000, P_PLL8, 4, 1, 4 },
  286. { 32000000, P_PLL8, 4, 1, 3 },
  287. { 40000000, P_PLL8, 1, 5, 48 },
  288. { 46400000, P_PLL8, 1, 29, 240 },
  289. { 48000000, P_PLL8, 4, 1, 2 },
  290. { 51200000, P_PLL8, 1, 2, 15 },
  291. { 56000000, P_PLL8, 1, 7, 48 },
  292. { 58982400, P_PLL8, 1, 96, 625 },
  293. { 64000000, P_PLL8, 2, 1, 3 },
  294. { }
  295. };
  296. static struct clk_rcg gsbi1_uart_src = {
  297. .ns_reg = 0x29d4,
  298. .md_reg = 0x29d0,
  299. .mn = {
  300. .mnctr_en_bit = 8,
  301. .mnctr_reset_bit = 7,
  302. .mnctr_mode_shift = 5,
  303. .n_val_shift = 16,
  304. .m_val_shift = 16,
  305. .width = 16,
  306. },
  307. .p = {
  308. .pre_div_shift = 3,
  309. .pre_div_width = 2,
  310. },
  311. .s = {
  312. .src_sel_shift = 0,
  313. .parent_map = gcc_pxo_pll8_map,
  314. },
  315. .freq_tbl = clk_tbl_gsbi_uart,
  316. .clkr = {
  317. .enable_reg = 0x29d4,
  318. .enable_mask = BIT(11),
  319. .hw.init = &(struct clk_init_data){
  320. .name = "gsbi1_uart_src",
  321. .parent_names = gcc_pxo_pll8,
  322. .num_parents = 2,
  323. .ops = &clk_rcg_ops,
  324. .flags = CLK_SET_PARENT_GATE,
  325. },
  326. },
  327. };
  328. static struct clk_branch gsbi1_uart_clk = {
  329. .halt_reg = 0x2fcc,
  330. .halt_bit = 10,
  331. .clkr = {
  332. .enable_reg = 0x29d4,
  333. .enable_mask = BIT(9),
  334. .hw.init = &(struct clk_init_data){
  335. .name = "gsbi1_uart_clk",
  336. .parent_names = (const char *[]){
  337. "gsbi1_uart_src",
  338. },
  339. .num_parents = 1,
  340. .ops = &clk_branch_ops,
  341. .flags = CLK_SET_RATE_PARENT,
  342. },
  343. },
  344. };
  345. static struct clk_rcg gsbi2_uart_src = {
  346. .ns_reg = 0x29f4,
  347. .md_reg = 0x29f0,
  348. .mn = {
  349. .mnctr_en_bit = 8,
  350. .mnctr_reset_bit = 7,
  351. .mnctr_mode_shift = 5,
  352. .n_val_shift = 16,
  353. .m_val_shift = 16,
  354. .width = 16,
  355. },
  356. .p = {
  357. .pre_div_shift = 3,
  358. .pre_div_width = 2,
  359. },
  360. .s = {
  361. .src_sel_shift = 0,
  362. .parent_map = gcc_pxo_pll8_map,
  363. },
  364. .freq_tbl = clk_tbl_gsbi_uart,
  365. .clkr = {
  366. .enable_reg = 0x29f4,
  367. .enable_mask = BIT(11),
  368. .hw.init = &(struct clk_init_data){
  369. .name = "gsbi2_uart_src",
  370. .parent_names = gcc_pxo_pll8,
  371. .num_parents = 2,
  372. .ops = &clk_rcg_ops,
  373. .flags = CLK_SET_PARENT_GATE,
  374. },
  375. },
  376. };
  377. static struct clk_branch gsbi2_uart_clk = {
  378. .halt_reg = 0x2fcc,
  379. .halt_bit = 6,
  380. .clkr = {
  381. .enable_reg = 0x29f4,
  382. .enable_mask = BIT(9),
  383. .hw.init = &(struct clk_init_data){
  384. .name = "gsbi2_uart_clk",
  385. .parent_names = (const char *[]){
  386. "gsbi2_uart_src",
  387. },
  388. .num_parents = 1,
  389. .ops = &clk_branch_ops,
  390. .flags = CLK_SET_RATE_PARENT,
  391. },
  392. },
  393. };
  394. static struct clk_rcg gsbi3_uart_src = {
  395. .ns_reg = 0x2a14,
  396. .md_reg = 0x2a10,
  397. .mn = {
  398. .mnctr_en_bit = 8,
  399. .mnctr_reset_bit = 7,
  400. .mnctr_mode_shift = 5,
  401. .n_val_shift = 16,
  402. .m_val_shift = 16,
  403. .width = 16,
  404. },
  405. .p = {
  406. .pre_div_shift = 3,
  407. .pre_div_width = 2,
  408. },
  409. .s = {
  410. .src_sel_shift = 0,
  411. .parent_map = gcc_pxo_pll8_map,
  412. },
  413. .freq_tbl = clk_tbl_gsbi_uart,
  414. .clkr = {
  415. .enable_reg = 0x2a14,
  416. .enable_mask = BIT(11),
  417. .hw.init = &(struct clk_init_data){
  418. .name = "gsbi3_uart_src",
  419. .parent_names = gcc_pxo_pll8,
  420. .num_parents = 2,
  421. .ops = &clk_rcg_ops,
  422. .flags = CLK_SET_PARENT_GATE,
  423. },
  424. },
  425. };
  426. static struct clk_branch gsbi3_uart_clk = {
  427. .halt_reg = 0x2fcc,
  428. .halt_bit = 2,
  429. .clkr = {
  430. .enable_reg = 0x2a14,
  431. .enable_mask = BIT(9),
  432. .hw.init = &(struct clk_init_data){
  433. .name = "gsbi3_uart_clk",
  434. .parent_names = (const char *[]){
  435. "gsbi3_uart_src",
  436. },
  437. .num_parents = 1,
  438. .ops = &clk_branch_ops,
  439. .flags = CLK_SET_RATE_PARENT,
  440. },
  441. },
  442. };
  443. static struct clk_rcg gsbi4_uart_src = {
  444. .ns_reg = 0x2a34,
  445. .md_reg = 0x2a30,
  446. .mn = {
  447. .mnctr_en_bit = 8,
  448. .mnctr_reset_bit = 7,
  449. .mnctr_mode_shift = 5,
  450. .n_val_shift = 16,
  451. .m_val_shift = 16,
  452. .width = 16,
  453. },
  454. .p = {
  455. .pre_div_shift = 3,
  456. .pre_div_width = 2,
  457. },
  458. .s = {
  459. .src_sel_shift = 0,
  460. .parent_map = gcc_pxo_pll8_map,
  461. },
  462. .freq_tbl = clk_tbl_gsbi_uart,
  463. .clkr = {
  464. .enable_reg = 0x2a34,
  465. .enable_mask = BIT(11),
  466. .hw.init = &(struct clk_init_data){
  467. .name = "gsbi4_uart_src",
  468. .parent_names = gcc_pxo_pll8,
  469. .num_parents = 2,
  470. .ops = &clk_rcg_ops,
  471. .flags = CLK_SET_PARENT_GATE,
  472. },
  473. },
  474. };
  475. static struct clk_branch gsbi4_uart_clk = {
  476. .halt_reg = 0x2fd0,
  477. .halt_bit = 26,
  478. .clkr = {
  479. .enable_reg = 0x2a34,
  480. .enable_mask = BIT(9),
  481. .hw.init = &(struct clk_init_data){
  482. .name = "gsbi4_uart_clk",
  483. .parent_names = (const char *[]){
  484. "gsbi4_uart_src",
  485. },
  486. .num_parents = 1,
  487. .ops = &clk_branch_ops,
  488. .flags = CLK_SET_RATE_PARENT,
  489. },
  490. },
  491. };
  492. static struct clk_rcg gsbi5_uart_src = {
  493. .ns_reg = 0x2a54,
  494. .md_reg = 0x2a50,
  495. .mn = {
  496. .mnctr_en_bit = 8,
  497. .mnctr_reset_bit = 7,
  498. .mnctr_mode_shift = 5,
  499. .n_val_shift = 16,
  500. .m_val_shift = 16,
  501. .width = 16,
  502. },
  503. .p = {
  504. .pre_div_shift = 3,
  505. .pre_div_width = 2,
  506. },
  507. .s = {
  508. .src_sel_shift = 0,
  509. .parent_map = gcc_pxo_pll8_map,
  510. },
  511. .freq_tbl = clk_tbl_gsbi_uart,
  512. .clkr = {
  513. .enable_reg = 0x2a54,
  514. .enable_mask = BIT(11),
  515. .hw.init = &(struct clk_init_data){
  516. .name = "gsbi5_uart_src",
  517. .parent_names = gcc_pxo_pll8,
  518. .num_parents = 2,
  519. .ops = &clk_rcg_ops,
  520. .flags = CLK_SET_PARENT_GATE,
  521. },
  522. },
  523. };
  524. static struct clk_branch gsbi5_uart_clk = {
  525. .halt_reg = 0x2fd0,
  526. .halt_bit = 22,
  527. .clkr = {
  528. .enable_reg = 0x2a54,
  529. .enable_mask = BIT(9),
  530. .hw.init = &(struct clk_init_data){
  531. .name = "gsbi5_uart_clk",
  532. .parent_names = (const char *[]){
  533. "gsbi5_uart_src",
  534. },
  535. .num_parents = 1,
  536. .ops = &clk_branch_ops,
  537. .flags = CLK_SET_RATE_PARENT,
  538. },
  539. },
  540. };
  541. static struct clk_rcg gsbi6_uart_src = {
  542. .ns_reg = 0x2a74,
  543. .md_reg = 0x2a70,
  544. .mn = {
  545. .mnctr_en_bit = 8,
  546. .mnctr_reset_bit = 7,
  547. .mnctr_mode_shift = 5,
  548. .n_val_shift = 16,
  549. .m_val_shift = 16,
  550. .width = 16,
  551. },
  552. .p = {
  553. .pre_div_shift = 3,
  554. .pre_div_width = 2,
  555. },
  556. .s = {
  557. .src_sel_shift = 0,
  558. .parent_map = gcc_pxo_pll8_map,
  559. },
  560. .freq_tbl = clk_tbl_gsbi_uart,
  561. .clkr = {
  562. .enable_reg = 0x2a74,
  563. .enable_mask = BIT(11),
  564. .hw.init = &(struct clk_init_data){
  565. .name = "gsbi6_uart_src",
  566. .parent_names = gcc_pxo_pll8,
  567. .num_parents = 2,
  568. .ops = &clk_rcg_ops,
  569. .flags = CLK_SET_PARENT_GATE,
  570. },
  571. },
  572. };
  573. static struct clk_branch gsbi6_uart_clk = {
  574. .halt_reg = 0x2fd0,
  575. .halt_bit = 18,
  576. .clkr = {
  577. .enable_reg = 0x2a74,
  578. .enable_mask = BIT(9),
  579. .hw.init = &(struct clk_init_data){
  580. .name = "gsbi6_uart_clk",
  581. .parent_names = (const char *[]){
  582. "gsbi6_uart_src",
  583. },
  584. .num_parents = 1,
  585. .ops = &clk_branch_ops,
  586. .flags = CLK_SET_RATE_PARENT,
  587. },
  588. },
  589. };
  590. static struct clk_rcg gsbi7_uart_src = {
  591. .ns_reg = 0x2a94,
  592. .md_reg = 0x2a90,
  593. .mn = {
  594. .mnctr_en_bit = 8,
  595. .mnctr_reset_bit = 7,
  596. .mnctr_mode_shift = 5,
  597. .n_val_shift = 16,
  598. .m_val_shift = 16,
  599. .width = 16,
  600. },
  601. .p = {
  602. .pre_div_shift = 3,
  603. .pre_div_width = 2,
  604. },
  605. .s = {
  606. .src_sel_shift = 0,
  607. .parent_map = gcc_pxo_pll8_map,
  608. },
  609. .freq_tbl = clk_tbl_gsbi_uart,
  610. .clkr = {
  611. .enable_reg = 0x2a94,
  612. .enable_mask = BIT(11),
  613. .hw.init = &(struct clk_init_data){
  614. .name = "gsbi7_uart_src",
  615. .parent_names = gcc_pxo_pll8,
  616. .num_parents = 2,
  617. .ops = &clk_rcg_ops,
  618. .flags = CLK_SET_PARENT_GATE,
  619. },
  620. },
  621. };
  622. static struct clk_branch gsbi7_uart_clk = {
  623. .halt_reg = 0x2fd0,
  624. .halt_bit = 14,
  625. .clkr = {
  626. .enable_reg = 0x2a94,
  627. .enable_mask = BIT(9),
  628. .hw.init = &(struct clk_init_data){
  629. .name = "gsbi7_uart_clk",
  630. .parent_names = (const char *[]){
  631. "gsbi7_uart_src",
  632. },
  633. .num_parents = 1,
  634. .ops = &clk_branch_ops,
  635. .flags = CLK_SET_RATE_PARENT,
  636. },
  637. },
  638. };
  639. static struct clk_rcg gsbi8_uart_src = {
  640. .ns_reg = 0x2ab4,
  641. .md_reg = 0x2ab0,
  642. .mn = {
  643. .mnctr_en_bit = 8,
  644. .mnctr_reset_bit = 7,
  645. .mnctr_mode_shift = 5,
  646. .n_val_shift = 16,
  647. .m_val_shift = 16,
  648. .width = 16,
  649. },
  650. .p = {
  651. .pre_div_shift = 3,
  652. .pre_div_width = 2,
  653. },
  654. .s = {
  655. .src_sel_shift = 0,
  656. .parent_map = gcc_pxo_pll8_map,
  657. },
  658. .freq_tbl = clk_tbl_gsbi_uart,
  659. .clkr = {
  660. .enable_reg = 0x2ab4,
  661. .enable_mask = BIT(11),
  662. .hw.init = &(struct clk_init_data){
  663. .name = "gsbi8_uart_src",
  664. .parent_names = gcc_pxo_pll8,
  665. .num_parents = 2,
  666. .ops = &clk_rcg_ops,
  667. .flags = CLK_SET_PARENT_GATE,
  668. },
  669. },
  670. };
  671. static struct clk_branch gsbi8_uart_clk = {
  672. .halt_reg = 0x2fd0,
  673. .halt_bit = 10,
  674. .clkr = {
  675. .enable_reg = 0x2ab4,
  676. .enable_mask = BIT(9),
  677. .hw.init = &(struct clk_init_data){
  678. .name = "gsbi8_uart_clk",
  679. .parent_names = (const char *[]){ "gsbi8_uart_src" },
  680. .num_parents = 1,
  681. .ops = &clk_branch_ops,
  682. .flags = CLK_SET_RATE_PARENT,
  683. },
  684. },
  685. };
  686. static struct clk_rcg gsbi9_uart_src = {
  687. .ns_reg = 0x2ad4,
  688. .md_reg = 0x2ad0,
  689. .mn = {
  690. .mnctr_en_bit = 8,
  691. .mnctr_reset_bit = 7,
  692. .mnctr_mode_shift = 5,
  693. .n_val_shift = 16,
  694. .m_val_shift = 16,
  695. .width = 16,
  696. },
  697. .p = {
  698. .pre_div_shift = 3,
  699. .pre_div_width = 2,
  700. },
  701. .s = {
  702. .src_sel_shift = 0,
  703. .parent_map = gcc_pxo_pll8_map,
  704. },
  705. .freq_tbl = clk_tbl_gsbi_uart,
  706. .clkr = {
  707. .enable_reg = 0x2ad4,
  708. .enable_mask = BIT(11),
  709. .hw.init = &(struct clk_init_data){
  710. .name = "gsbi9_uart_src",
  711. .parent_names = gcc_pxo_pll8,
  712. .num_parents = 2,
  713. .ops = &clk_rcg_ops,
  714. .flags = CLK_SET_PARENT_GATE,
  715. },
  716. },
  717. };
  718. static struct clk_branch gsbi9_uart_clk = {
  719. .halt_reg = 0x2fd0,
  720. .halt_bit = 6,
  721. .clkr = {
  722. .enable_reg = 0x2ad4,
  723. .enable_mask = BIT(9),
  724. .hw.init = &(struct clk_init_data){
  725. .name = "gsbi9_uart_clk",
  726. .parent_names = (const char *[]){ "gsbi9_uart_src" },
  727. .num_parents = 1,
  728. .ops = &clk_branch_ops,
  729. .flags = CLK_SET_RATE_PARENT,
  730. },
  731. },
  732. };
  733. static struct clk_rcg gsbi10_uart_src = {
  734. .ns_reg = 0x2af4,
  735. .md_reg = 0x2af0,
  736. .mn = {
  737. .mnctr_en_bit = 8,
  738. .mnctr_reset_bit = 7,
  739. .mnctr_mode_shift = 5,
  740. .n_val_shift = 16,
  741. .m_val_shift = 16,
  742. .width = 16,
  743. },
  744. .p = {
  745. .pre_div_shift = 3,
  746. .pre_div_width = 2,
  747. },
  748. .s = {
  749. .src_sel_shift = 0,
  750. .parent_map = gcc_pxo_pll8_map,
  751. },
  752. .freq_tbl = clk_tbl_gsbi_uart,
  753. .clkr = {
  754. .enable_reg = 0x2af4,
  755. .enable_mask = BIT(11),
  756. .hw.init = &(struct clk_init_data){
  757. .name = "gsbi10_uart_src",
  758. .parent_names = gcc_pxo_pll8,
  759. .num_parents = 2,
  760. .ops = &clk_rcg_ops,
  761. .flags = CLK_SET_PARENT_GATE,
  762. },
  763. },
  764. };
  765. static struct clk_branch gsbi10_uart_clk = {
  766. .halt_reg = 0x2fd0,
  767. .halt_bit = 2,
  768. .clkr = {
  769. .enable_reg = 0x2af4,
  770. .enable_mask = BIT(9),
  771. .hw.init = &(struct clk_init_data){
  772. .name = "gsbi10_uart_clk",
  773. .parent_names = (const char *[]){ "gsbi10_uart_src" },
  774. .num_parents = 1,
  775. .ops = &clk_branch_ops,
  776. .flags = CLK_SET_RATE_PARENT,
  777. },
  778. },
  779. };
  780. static struct clk_rcg gsbi11_uart_src = {
  781. .ns_reg = 0x2b14,
  782. .md_reg = 0x2b10,
  783. .mn = {
  784. .mnctr_en_bit = 8,
  785. .mnctr_reset_bit = 7,
  786. .mnctr_mode_shift = 5,
  787. .n_val_shift = 16,
  788. .m_val_shift = 16,
  789. .width = 16,
  790. },
  791. .p = {
  792. .pre_div_shift = 3,
  793. .pre_div_width = 2,
  794. },
  795. .s = {
  796. .src_sel_shift = 0,
  797. .parent_map = gcc_pxo_pll8_map,
  798. },
  799. .freq_tbl = clk_tbl_gsbi_uart,
  800. .clkr = {
  801. .enable_reg = 0x2b14,
  802. .enable_mask = BIT(11),
  803. .hw.init = &(struct clk_init_data){
  804. .name = "gsbi11_uart_src",
  805. .parent_names = gcc_pxo_pll8,
  806. .num_parents = 2,
  807. .ops = &clk_rcg_ops,
  808. .flags = CLK_SET_PARENT_GATE,
  809. },
  810. },
  811. };
  812. static struct clk_branch gsbi11_uart_clk = {
  813. .halt_reg = 0x2fd4,
  814. .halt_bit = 17,
  815. .clkr = {
  816. .enable_reg = 0x2b14,
  817. .enable_mask = BIT(9),
  818. .hw.init = &(struct clk_init_data){
  819. .name = "gsbi11_uart_clk",
  820. .parent_names = (const char *[]){ "gsbi11_uart_src" },
  821. .num_parents = 1,
  822. .ops = &clk_branch_ops,
  823. .flags = CLK_SET_RATE_PARENT,
  824. },
  825. },
  826. };
  827. static struct clk_rcg gsbi12_uart_src = {
  828. .ns_reg = 0x2b34,
  829. .md_reg = 0x2b30,
  830. .mn = {
  831. .mnctr_en_bit = 8,
  832. .mnctr_reset_bit = 7,
  833. .mnctr_mode_shift = 5,
  834. .n_val_shift = 16,
  835. .m_val_shift = 16,
  836. .width = 16,
  837. },
  838. .p = {
  839. .pre_div_shift = 3,
  840. .pre_div_width = 2,
  841. },
  842. .s = {
  843. .src_sel_shift = 0,
  844. .parent_map = gcc_pxo_pll8_map,
  845. },
  846. .freq_tbl = clk_tbl_gsbi_uart,
  847. .clkr = {
  848. .enable_reg = 0x2b34,
  849. .enable_mask = BIT(11),
  850. .hw.init = &(struct clk_init_data){
  851. .name = "gsbi12_uart_src",
  852. .parent_names = gcc_pxo_pll8,
  853. .num_parents = 2,
  854. .ops = &clk_rcg_ops,
  855. .flags = CLK_SET_PARENT_GATE,
  856. },
  857. },
  858. };
  859. static struct clk_branch gsbi12_uart_clk = {
  860. .halt_reg = 0x2fd4,
  861. .halt_bit = 13,
  862. .clkr = {
  863. .enable_reg = 0x2b34,
  864. .enable_mask = BIT(9),
  865. .hw.init = &(struct clk_init_data){
  866. .name = "gsbi12_uart_clk",
  867. .parent_names = (const char *[]){ "gsbi12_uart_src" },
  868. .num_parents = 1,
  869. .ops = &clk_branch_ops,
  870. .flags = CLK_SET_RATE_PARENT,
  871. },
  872. },
  873. };
  874. static struct freq_tbl clk_tbl_gsbi_qup[] = {
  875. { 1100000, P_PXO, 1, 2, 49 },
  876. { 5400000, P_PXO, 1, 1, 5 },
  877. { 10800000, P_PXO, 1, 2, 5 },
  878. { 15060000, P_PLL8, 1, 2, 51 },
  879. { 24000000, P_PLL8, 4, 1, 4 },
  880. { 25600000, P_PLL8, 1, 1, 15 },
  881. { 27000000, P_PXO, 1, 0, 0 },
  882. { 48000000, P_PLL8, 4, 1, 2 },
  883. { 51200000, P_PLL8, 1, 2, 15 },
  884. { }
  885. };
  886. static struct clk_rcg gsbi1_qup_src = {
  887. .ns_reg = 0x29cc,
  888. .md_reg = 0x29c8,
  889. .mn = {
  890. .mnctr_en_bit = 8,
  891. .mnctr_reset_bit = 7,
  892. .mnctr_mode_shift = 5,
  893. .n_val_shift = 16,
  894. .m_val_shift = 16,
  895. .width = 8,
  896. },
  897. .p = {
  898. .pre_div_shift = 3,
  899. .pre_div_width = 2,
  900. },
  901. .s = {
  902. .src_sel_shift = 0,
  903. .parent_map = gcc_pxo_pll8_map,
  904. },
  905. .freq_tbl = clk_tbl_gsbi_qup,
  906. .clkr = {
  907. .enable_reg = 0x29cc,
  908. .enable_mask = BIT(11),
  909. .hw.init = &(struct clk_init_data){
  910. .name = "gsbi1_qup_src",
  911. .parent_names = gcc_pxo_pll8,
  912. .num_parents = 2,
  913. .ops = &clk_rcg_ops,
  914. .flags = CLK_SET_PARENT_GATE,
  915. },
  916. },
  917. };
  918. static struct clk_branch gsbi1_qup_clk = {
  919. .halt_reg = 0x2fcc,
  920. .halt_bit = 9,
  921. .clkr = {
  922. .enable_reg = 0x29cc,
  923. .enable_mask = BIT(9),
  924. .hw.init = &(struct clk_init_data){
  925. .name = "gsbi1_qup_clk",
  926. .parent_names = (const char *[]){ "gsbi1_qup_src" },
  927. .num_parents = 1,
  928. .ops = &clk_branch_ops,
  929. .flags = CLK_SET_RATE_PARENT,
  930. },
  931. },
  932. };
  933. static struct clk_rcg gsbi2_qup_src = {
  934. .ns_reg = 0x29ec,
  935. .md_reg = 0x29e8,
  936. .mn = {
  937. .mnctr_en_bit = 8,
  938. .mnctr_reset_bit = 7,
  939. .mnctr_mode_shift = 5,
  940. .n_val_shift = 16,
  941. .m_val_shift = 16,
  942. .width = 8,
  943. },
  944. .p = {
  945. .pre_div_shift = 3,
  946. .pre_div_width = 2,
  947. },
  948. .s = {
  949. .src_sel_shift = 0,
  950. .parent_map = gcc_pxo_pll8_map,
  951. },
  952. .freq_tbl = clk_tbl_gsbi_qup,
  953. .clkr = {
  954. .enable_reg = 0x29ec,
  955. .enable_mask = BIT(11),
  956. .hw.init = &(struct clk_init_data){
  957. .name = "gsbi2_qup_src",
  958. .parent_names = gcc_pxo_pll8,
  959. .num_parents = 2,
  960. .ops = &clk_rcg_ops,
  961. .flags = CLK_SET_PARENT_GATE,
  962. },
  963. },
  964. };
  965. static struct clk_branch gsbi2_qup_clk = {
  966. .halt_reg = 0x2fcc,
  967. .halt_bit = 4,
  968. .clkr = {
  969. .enable_reg = 0x29ec,
  970. .enable_mask = BIT(9),
  971. .hw.init = &(struct clk_init_data){
  972. .name = "gsbi2_qup_clk",
  973. .parent_names = (const char *[]){ "gsbi2_qup_src" },
  974. .num_parents = 1,
  975. .ops = &clk_branch_ops,
  976. .flags = CLK_SET_RATE_PARENT,
  977. },
  978. },
  979. };
  980. static struct clk_rcg gsbi3_qup_src = {
  981. .ns_reg = 0x2a0c,
  982. .md_reg = 0x2a08,
  983. .mn = {
  984. .mnctr_en_bit = 8,
  985. .mnctr_reset_bit = 7,
  986. .mnctr_mode_shift = 5,
  987. .n_val_shift = 16,
  988. .m_val_shift = 16,
  989. .width = 8,
  990. },
  991. .p = {
  992. .pre_div_shift = 3,
  993. .pre_div_width = 2,
  994. },
  995. .s = {
  996. .src_sel_shift = 0,
  997. .parent_map = gcc_pxo_pll8_map,
  998. },
  999. .freq_tbl = clk_tbl_gsbi_qup,
  1000. .clkr = {
  1001. .enable_reg = 0x2a0c,
  1002. .enable_mask = BIT(11),
  1003. .hw.init = &(struct clk_init_data){
  1004. .name = "gsbi3_qup_src",
  1005. .parent_names = gcc_pxo_pll8,
  1006. .num_parents = 2,
  1007. .ops = &clk_rcg_ops,
  1008. .flags = CLK_SET_PARENT_GATE,
  1009. },
  1010. },
  1011. };
  1012. static struct clk_branch gsbi3_qup_clk = {
  1013. .halt_reg = 0x2fcc,
  1014. .halt_bit = 0,
  1015. .clkr = {
  1016. .enable_reg = 0x2a0c,
  1017. .enable_mask = BIT(9),
  1018. .hw.init = &(struct clk_init_data){
  1019. .name = "gsbi3_qup_clk",
  1020. .parent_names = (const char *[]){ "gsbi3_qup_src" },
  1021. .num_parents = 1,
  1022. .ops = &clk_branch_ops,
  1023. .flags = CLK_SET_RATE_PARENT,
  1024. },
  1025. },
  1026. };
  1027. static struct clk_rcg gsbi4_qup_src = {
  1028. .ns_reg = 0x2a2c,
  1029. .md_reg = 0x2a28,
  1030. .mn = {
  1031. .mnctr_en_bit = 8,
  1032. .mnctr_reset_bit = 7,
  1033. .mnctr_mode_shift = 5,
  1034. .n_val_shift = 16,
  1035. .m_val_shift = 16,
  1036. .width = 8,
  1037. },
  1038. .p = {
  1039. .pre_div_shift = 3,
  1040. .pre_div_width = 2,
  1041. },
  1042. .s = {
  1043. .src_sel_shift = 0,
  1044. .parent_map = gcc_pxo_pll8_map,
  1045. },
  1046. .freq_tbl = clk_tbl_gsbi_qup,
  1047. .clkr = {
  1048. .enable_reg = 0x2a2c,
  1049. .enable_mask = BIT(11),
  1050. .hw.init = &(struct clk_init_data){
  1051. .name = "gsbi4_qup_src",
  1052. .parent_names = gcc_pxo_pll8,
  1053. .num_parents = 2,
  1054. .ops = &clk_rcg_ops,
  1055. .flags = CLK_SET_PARENT_GATE,
  1056. },
  1057. },
  1058. };
  1059. static struct clk_branch gsbi4_qup_clk = {
  1060. .halt_reg = 0x2fd0,
  1061. .halt_bit = 24,
  1062. .clkr = {
  1063. .enable_reg = 0x2a2c,
  1064. .enable_mask = BIT(9),
  1065. .hw.init = &(struct clk_init_data){
  1066. .name = "gsbi4_qup_clk",
  1067. .parent_names = (const char *[]){ "gsbi4_qup_src" },
  1068. .num_parents = 1,
  1069. .ops = &clk_branch_ops,
  1070. .flags = CLK_SET_RATE_PARENT,
  1071. },
  1072. },
  1073. };
  1074. static struct clk_rcg gsbi5_qup_src = {
  1075. .ns_reg = 0x2a4c,
  1076. .md_reg = 0x2a48,
  1077. .mn = {
  1078. .mnctr_en_bit = 8,
  1079. .mnctr_reset_bit = 7,
  1080. .mnctr_mode_shift = 5,
  1081. .n_val_shift = 16,
  1082. .m_val_shift = 16,
  1083. .width = 8,
  1084. },
  1085. .p = {
  1086. .pre_div_shift = 3,
  1087. .pre_div_width = 2,
  1088. },
  1089. .s = {
  1090. .src_sel_shift = 0,
  1091. .parent_map = gcc_pxo_pll8_map,
  1092. },
  1093. .freq_tbl = clk_tbl_gsbi_qup,
  1094. .clkr = {
  1095. .enable_reg = 0x2a4c,
  1096. .enable_mask = BIT(11),
  1097. .hw.init = &(struct clk_init_data){
  1098. .name = "gsbi5_qup_src",
  1099. .parent_names = gcc_pxo_pll8,
  1100. .num_parents = 2,
  1101. .ops = &clk_rcg_ops,
  1102. .flags = CLK_SET_PARENT_GATE,
  1103. },
  1104. },
  1105. };
  1106. static struct clk_branch gsbi5_qup_clk = {
  1107. .halt_reg = 0x2fd0,
  1108. .halt_bit = 20,
  1109. .clkr = {
  1110. .enable_reg = 0x2a4c,
  1111. .enable_mask = BIT(9),
  1112. .hw.init = &(struct clk_init_data){
  1113. .name = "gsbi5_qup_clk",
  1114. .parent_names = (const char *[]){ "gsbi5_qup_src" },
  1115. .num_parents = 1,
  1116. .ops = &clk_branch_ops,
  1117. .flags = CLK_SET_RATE_PARENT,
  1118. },
  1119. },
  1120. };
  1121. static struct clk_rcg gsbi6_qup_src = {
  1122. .ns_reg = 0x2a6c,
  1123. .md_reg = 0x2a68,
  1124. .mn = {
  1125. .mnctr_en_bit = 8,
  1126. .mnctr_reset_bit = 7,
  1127. .mnctr_mode_shift = 5,
  1128. .n_val_shift = 16,
  1129. .m_val_shift = 16,
  1130. .width = 8,
  1131. },
  1132. .p = {
  1133. .pre_div_shift = 3,
  1134. .pre_div_width = 2,
  1135. },
  1136. .s = {
  1137. .src_sel_shift = 0,
  1138. .parent_map = gcc_pxo_pll8_map,
  1139. },
  1140. .freq_tbl = clk_tbl_gsbi_qup,
  1141. .clkr = {
  1142. .enable_reg = 0x2a6c,
  1143. .enable_mask = BIT(11),
  1144. .hw.init = &(struct clk_init_data){
  1145. .name = "gsbi6_qup_src",
  1146. .parent_names = gcc_pxo_pll8,
  1147. .num_parents = 2,
  1148. .ops = &clk_rcg_ops,
  1149. .flags = CLK_SET_PARENT_GATE,
  1150. },
  1151. },
  1152. };
  1153. static struct clk_branch gsbi6_qup_clk = {
  1154. .halt_reg = 0x2fd0,
  1155. .halt_bit = 16,
  1156. .clkr = {
  1157. .enable_reg = 0x2a6c,
  1158. .enable_mask = BIT(9),
  1159. .hw.init = &(struct clk_init_data){
  1160. .name = "gsbi6_qup_clk",
  1161. .parent_names = (const char *[]){ "gsbi6_qup_src" },
  1162. .num_parents = 1,
  1163. .ops = &clk_branch_ops,
  1164. .flags = CLK_SET_RATE_PARENT,
  1165. },
  1166. },
  1167. };
  1168. static struct clk_rcg gsbi7_qup_src = {
  1169. .ns_reg = 0x2a8c,
  1170. .md_reg = 0x2a88,
  1171. .mn = {
  1172. .mnctr_en_bit = 8,
  1173. .mnctr_reset_bit = 7,
  1174. .mnctr_mode_shift = 5,
  1175. .n_val_shift = 16,
  1176. .m_val_shift = 16,
  1177. .width = 8,
  1178. },
  1179. .p = {
  1180. .pre_div_shift = 3,
  1181. .pre_div_width = 2,
  1182. },
  1183. .s = {
  1184. .src_sel_shift = 0,
  1185. .parent_map = gcc_pxo_pll8_map,
  1186. },
  1187. .freq_tbl = clk_tbl_gsbi_qup,
  1188. .clkr = {
  1189. .enable_reg = 0x2a8c,
  1190. .enable_mask = BIT(11),
  1191. .hw.init = &(struct clk_init_data){
  1192. .name = "gsbi7_qup_src",
  1193. .parent_names = gcc_pxo_pll8,
  1194. .num_parents = 2,
  1195. .ops = &clk_rcg_ops,
  1196. .flags = CLK_SET_PARENT_GATE,
  1197. },
  1198. },
  1199. };
  1200. static struct clk_branch gsbi7_qup_clk = {
  1201. .halt_reg = 0x2fd0,
  1202. .halt_bit = 12,
  1203. .clkr = {
  1204. .enable_reg = 0x2a8c,
  1205. .enable_mask = BIT(9),
  1206. .hw.init = &(struct clk_init_data){
  1207. .name = "gsbi7_qup_clk",
  1208. .parent_names = (const char *[]){ "gsbi7_qup_src" },
  1209. .num_parents = 1,
  1210. .ops = &clk_branch_ops,
  1211. .flags = CLK_SET_RATE_PARENT,
  1212. },
  1213. },
  1214. };
  1215. static struct clk_rcg gsbi8_qup_src = {
  1216. .ns_reg = 0x2aac,
  1217. .md_reg = 0x2aa8,
  1218. .mn = {
  1219. .mnctr_en_bit = 8,
  1220. .mnctr_reset_bit = 7,
  1221. .mnctr_mode_shift = 5,
  1222. .n_val_shift = 16,
  1223. .m_val_shift = 16,
  1224. .width = 8,
  1225. },
  1226. .p = {
  1227. .pre_div_shift = 3,
  1228. .pre_div_width = 2,
  1229. },
  1230. .s = {
  1231. .src_sel_shift = 0,
  1232. .parent_map = gcc_pxo_pll8_map,
  1233. },
  1234. .freq_tbl = clk_tbl_gsbi_qup,
  1235. .clkr = {
  1236. .enable_reg = 0x2aac,
  1237. .enable_mask = BIT(11),
  1238. .hw.init = &(struct clk_init_data){
  1239. .name = "gsbi8_qup_src",
  1240. .parent_names = gcc_pxo_pll8,
  1241. .num_parents = 2,
  1242. .ops = &clk_rcg_ops,
  1243. .flags = CLK_SET_PARENT_GATE,
  1244. },
  1245. },
  1246. };
  1247. static struct clk_branch gsbi8_qup_clk = {
  1248. .halt_reg = 0x2fd0,
  1249. .halt_bit = 8,
  1250. .clkr = {
  1251. .enable_reg = 0x2aac,
  1252. .enable_mask = BIT(9),
  1253. .hw.init = &(struct clk_init_data){
  1254. .name = "gsbi8_qup_clk",
  1255. .parent_names = (const char *[]){ "gsbi8_qup_src" },
  1256. .num_parents = 1,
  1257. .ops = &clk_branch_ops,
  1258. .flags = CLK_SET_RATE_PARENT,
  1259. },
  1260. },
  1261. };
  1262. static struct clk_rcg gsbi9_qup_src = {
  1263. .ns_reg = 0x2acc,
  1264. .md_reg = 0x2ac8,
  1265. .mn = {
  1266. .mnctr_en_bit = 8,
  1267. .mnctr_reset_bit = 7,
  1268. .mnctr_mode_shift = 5,
  1269. .n_val_shift = 16,
  1270. .m_val_shift = 16,
  1271. .width = 8,
  1272. },
  1273. .p = {
  1274. .pre_div_shift = 3,
  1275. .pre_div_width = 2,
  1276. },
  1277. .s = {
  1278. .src_sel_shift = 0,
  1279. .parent_map = gcc_pxo_pll8_map,
  1280. },
  1281. .freq_tbl = clk_tbl_gsbi_qup,
  1282. .clkr = {
  1283. .enable_reg = 0x2acc,
  1284. .enable_mask = BIT(11),
  1285. .hw.init = &(struct clk_init_data){
  1286. .name = "gsbi9_qup_src",
  1287. .parent_names = gcc_pxo_pll8,
  1288. .num_parents = 2,
  1289. .ops = &clk_rcg_ops,
  1290. .flags = CLK_SET_PARENT_GATE,
  1291. },
  1292. },
  1293. };
  1294. static struct clk_branch gsbi9_qup_clk = {
  1295. .halt_reg = 0x2fd0,
  1296. .halt_bit = 4,
  1297. .clkr = {
  1298. .enable_reg = 0x2acc,
  1299. .enable_mask = BIT(9),
  1300. .hw.init = &(struct clk_init_data){
  1301. .name = "gsbi9_qup_clk",
  1302. .parent_names = (const char *[]){ "gsbi9_qup_src" },
  1303. .num_parents = 1,
  1304. .ops = &clk_branch_ops,
  1305. .flags = CLK_SET_RATE_PARENT,
  1306. },
  1307. },
  1308. };
  1309. static struct clk_rcg gsbi10_qup_src = {
  1310. .ns_reg = 0x2aec,
  1311. .md_reg = 0x2ae8,
  1312. .mn = {
  1313. .mnctr_en_bit = 8,
  1314. .mnctr_reset_bit = 7,
  1315. .mnctr_mode_shift = 5,
  1316. .n_val_shift = 16,
  1317. .m_val_shift = 16,
  1318. .width = 8,
  1319. },
  1320. .p = {
  1321. .pre_div_shift = 3,
  1322. .pre_div_width = 2,
  1323. },
  1324. .s = {
  1325. .src_sel_shift = 0,
  1326. .parent_map = gcc_pxo_pll8_map,
  1327. },
  1328. .freq_tbl = clk_tbl_gsbi_qup,
  1329. .clkr = {
  1330. .enable_reg = 0x2aec,
  1331. .enable_mask = BIT(11),
  1332. .hw.init = &(struct clk_init_data){
  1333. .name = "gsbi10_qup_src",
  1334. .parent_names = gcc_pxo_pll8,
  1335. .num_parents = 2,
  1336. .ops = &clk_rcg_ops,
  1337. .flags = CLK_SET_PARENT_GATE,
  1338. },
  1339. },
  1340. };
  1341. static struct clk_branch gsbi10_qup_clk = {
  1342. .halt_reg = 0x2fd0,
  1343. .halt_bit = 0,
  1344. .clkr = {
  1345. .enable_reg = 0x2aec,
  1346. .enable_mask = BIT(9),
  1347. .hw.init = &(struct clk_init_data){
  1348. .name = "gsbi10_qup_clk",
  1349. .parent_names = (const char *[]){ "gsbi10_qup_src" },
  1350. .num_parents = 1,
  1351. .ops = &clk_branch_ops,
  1352. .flags = CLK_SET_RATE_PARENT,
  1353. },
  1354. },
  1355. };
  1356. static struct clk_rcg gsbi11_qup_src = {
  1357. .ns_reg = 0x2b0c,
  1358. .md_reg = 0x2b08,
  1359. .mn = {
  1360. .mnctr_en_bit = 8,
  1361. .mnctr_reset_bit = 7,
  1362. .mnctr_mode_shift = 5,
  1363. .n_val_shift = 16,
  1364. .m_val_shift = 16,
  1365. .width = 8,
  1366. },
  1367. .p = {
  1368. .pre_div_shift = 3,
  1369. .pre_div_width = 2,
  1370. },
  1371. .s = {
  1372. .src_sel_shift = 0,
  1373. .parent_map = gcc_pxo_pll8_map,
  1374. },
  1375. .freq_tbl = clk_tbl_gsbi_qup,
  1376. .clkr = {
  1377. .enable_reg = 0x2b0c,
  1378. .enable_mask = BIT(11),
  1379. .hw.init = &(struct clk_init_data){
  1380. .name = "gsbi11_qup_src",
  1381. .parent_names = gcc_pxo_pll8,
  1382. .num_parents = 2,
  1383. .ops = &clk_rcg_ops,
  1384. .flags = CLK_SET_PARENT_GATE,
  1385. },
  1386. },
  1387. };
  1388. static struct clk_branch gsbi11_qup_clk = {
  1389. .halt_reg = 0x2fd4,
  1390. .halt_bit = 15,
  1391. .clkr = {
  1392. .enable_reg = 0x2b0c,
  1393. .enable_mask = BIT(9),
  1394. .hw.init = &(struct clk_init_data){
  1395. .name = "gsbi11_qup_clk",
  1396. .parent_names = (const char *[]){ "gsbi11_qup_src" },
  1397. .num_parents = 1,
  1398. .ops = &clk_branch_ops,
  1399. .flags = CLK_SET_RATE_PARENT,
  1400. },
  1401. },
  1402. };
  1403. static struct clk_rcg gsbi12_qup_src = {
  1404. .ns_reg = 0x2b2c,
  1405. .md_reg = 0x2b28,
  1406. .mn = {
  1407. .mnctr_en_bit = 8,
  1408. .mnctr_reset_bit = 7,
  1409. .mnctr_mode_shift = 5,
  1410. .n_val_shift = 16,
  1411. .m_val_shift = 16,
  1412. .width = 8,
  1413. },
  1414. .p = {
  1415. .pre_div_shift = 3,
  1416. .pre_div_width = 2,
  1417. },
  1418. .s = {
  1419. .src_sel_shift = 0,
  1420. .parent_map = gcc_pxo_pll8_map,
  1421. },
  1422. .freq_tbl = clk_tbl_gsbi_qup,
  1423. .clkr = {
  1424. .enable_reg = 0x2b2c,
  1425. .enable_mask = BIT(11),
  1426. .hw.init = &(struct clk_init_data){
  1427. .name = "gsbi12_qup_src",
  1428. .parent_names = gcc_pxo_pll8,
  1429. .num_parents = 2,
  1430. .ops = &clk_rcg_ops,
  1431. .flags = CLK_SET_PARENT_GATE,
  1432. },
  1433. },
  1434. };
  1435. static struct clk_branch gsbi12_qup_clk = {
  1436. .halt_reg = 0x2fd4,
  1437. .halt_bit = 11,
  1438. .clkr = {
  1439. .enable_reg = 0x2b2c,
  1440. .enable_mask = BIT(9),
  1441. .hw.init = &(struct clk_init_data){
  1442. .name = "gsbi12_qup_clk",
  1443. .parent_names = (const char *[]){ "gsbi12_qup_src" },
  1444. .num_parents = 1,
  1445. .ops = &clk_branch_ops,
  1446. .flags = CLK_SET_RATE_PARENT,
  1447. },
  1448. },
  1449. };
  1450. static const struct freq_tbl clk_tbl_gp[] = {
  1451. { 9600000, P_CXO, 2, 0, 0 },
  1452. { 13500000, P_PXO, 2, 0, 0 },
  1453. { 19200000, P_CXO, 1, 0, 0 },
  1454. { 27000000, P_PXO, 1, 0, 0 },
  1455. { 64000000, P_PLL8, 2, 1, 3 },
  1456. { 76800000, P_PLL8, 1, 1, 5 },
  1457. { 96000000, P_PLL8, 4, 0, 0 },
  1458. { 128000000, P_PLL8, 3, 0, 0 },
  1459. { 192000000, P_PLL8, 2, 0, 0 },
  1460. { }
  1461. };
  1462. static struct clk_rcg gp0_src = {
  1463. .ns_reg = 0x2d24,
  1464. .md_reg = 0x2d00,
  1465. .mn = {
  1466. .mnctr_en_bit = 8,
  1467. .mnctr_reset_bit = 7,
  1468. .mnctr_mode_shift = 5,
  1469. .n_val_shift = 16,
  1470. .m_val_shift = 16,
  1471. .width = 8,
  1472. },
  1473. .p = {
  1474. .pre_div_shift = 3,
  1475. .pre_div_width = 2,
  1476. },
  1477. .s = {
  1478. .src_sel_shift = 0,
  1479. .parent_map = gcc_pxo_pll8_cxo_map,
  1480. },
  1481. .freq_tbl = clk_tbl_gp,
  1482. .clkr = {
  1483. .enable_reg = 0x2d24,
  1484. .enable_mask = BIT(11),
  1485. .hw.init = &(struct clk_init_data){
  1486. .name = "gp0_src",
  1487. .parent_names = gcc_pxo_pll8_cxo,
  1488. .num_parents = 3,
  1489. .ops = &clk_rcg_ops,
  1490. .flags = CLK_SET_PARENT_GATE,
  1491. },
  1492. }
  1493. };
  1494. static struct clk_branch gp0_clk = {
  1495. .halt_reg = 0x2fd8,
  1496. .halt_bit = 7,
  1497. .clkr = {
  1498. .enable_reg = 0x2d24,
  1499. .enable_mask = BIT(9),
  1500. .hw.init = &(struct clk_init_data){
  1501. .name = "gp0_clk",
  1502. .parent_names = (const char *[]){ "gp0_src" },
  1503. .num_parents = 1,
  1504. .ops = &clk_branch_ops,
  1505. .flags = CLK_SET_RATE_PARENT,
  1506. },
  1507. },
  1508. };
  1509. static struct clk_rcg gp1_src = {
  1510. .ns_reg = 0x2d44,
  1511. .md_reg = 0x2d40,
  1512. .mn = {
  1513. .mnctr_en_bit = 8,
  1514. .mnctr_reset_bit = 7,
  1515. .mnctr_mode_shift = 5,
  1516. .n_val_shift = 16,
  1517. .m_val_shift = 16,
  1518. .width = 8,
  1519. },
  1520. .p = {
  1521. .pre_div_shift = 3,
  1522. .pre_div_width = 2,
  1523. },
  1524. .s = {
  1525. .src_sel_shift = 0,
  1526. .parent_map = gcc_pxo_pll8_cxo_map,
  1527. },
  1528. .freq_tbl = clk_tbl_gp,
  1529. .clkr = {
  1530. .enable_reg = 0x2d44,
  1531. .enable_mask = BIT(11),
  1532. .hw.init = &(struct clk_init_data){
  1533. .name = "gp1_src",
  1534. .parent_names = gcc_pxo_pll8_cxo,
  1535. .num_parents = 3,
  1536. .ops = &clk_rcg_ops,
  1537. .flags = CLK_SET_RATE_GATE,
  1538. },
  1539. }
  1540. };
  1541. static struct clk_branch gp1_clk = {
  1542. .halt_reg = 0x2fd8,
  1543. .halt_bit = 6,
  1544. .clkr = {
  1545. .enable_reg = 0x2d44,
  1546. .enable_mask = BIT(9),
  1547. .hw.init = &(struct clk_init_data){
  1548. .name = "gp1_clk",
  1549. .parent_names = (const char *[]){ "gp1_src" },
  1550. .num_parents = 1,
  1551. .ops = &clk_branch_ops,
  1552. .flags = CLK_SET_RATE_PARENT,
  1553. },
  1554. },
  1555. };
  1556. static struct clk_rcg gp2_src = {
  1557. .ns_reg = 0x2d64,
  1558. .md_reg = 0x2d60,
  1559. .mn = {
  1560. .mnctr_en_bit = 8,
  1561. .mnctr_reset_bit = 7,
  1562. .mnctr_mode_shift = 5,
  1563. .n_val_shift = 16,
  1564. .m_val_shift = 16,
  1565. .width = 8,
  1566. },
  1567. .p = {
  1568. .pre_div_shift = 3,
  1569. .pre_div_width = 2,
  1570. },
  1571. .s = {
  1572. .src_sel_shift = 0,
  1573. .parent_map = gcc_pxo_pll8_cxo_map,
  1574. },
  1575. .freq_tbl = clk_tbl_gp,
  1576. .clkr = {
  1577. .enable_reg = 0x2d64,
  1578. .enable_mask = BIT(11),
  1579. .hw.init = &(struct clk_init_data){
  1580. .name = "gp2_src",
  1581. .parent_names = gcc_pxo_pll8_cxo,
  1582. .num_parents = 3,
  1583. .ops = &clk_rcg_ops,
  1584. .flags = CLK_SET_RATE_GATE,
  1585. },
  1586. }
  1587. };
  1588. static struct clk_branch gp2_clk = {
  1589. .halt_reg = 0x2fd8,
  1590. .halt_bit = 5,
  1591. .clkr = {
  1592. .enable_reg = 0x2d64,
  1593. .enable_mask = BIT(9),
  1594. .hw.init = &(struct clk_init_data){
  1595. .name = "gp2_clk",
  1596. .parent_names = (const char *[]){ "gp2_src" },
  1597. .num_parents = 1,
  1598. .ops = &clk_branch_ops,
  1599. .flags = CLK_SET_RATE_PARENT,
  1600. },
  1601. },
  1602. };
  1603. static struct clk_branch pmem_clk = {
  1604. .hwcg_reg = 0x25a0,
  1605. .hwcg_bit = 6,
  1606. .halt_reg = 0x2fc8,
  1607. .halt_bit = 20,
  1608. .clkr = {
  1609. .enable_reg = 0x25a0,
  1610. .enable_mask = BIT(4),
  1611. .hw.init = &(struct clk_init_data){
  1612. .name = "pmem_clk",
  1613. .ops = &clk_branch_ops,
  1614. },
  1615. },
  1616. };
  1617. static struct clk_rcg prng_src = {
  1618. .ns_reg = 0x2e80,
  1619. .p = {
  1620. .pre_div_shift = 3,
  1621. .pre_div_width = 4,
  1622. },
  1623. .s = {
  1624. .src_sel_shift = 0,
  1625. .parent_map = gcc_pxo_pll8_map,
  1626. },
  1627. .clkr = {
  1628. .hw.init = &(struct clk_init_data){
  1629. .name = "prng_src",
  1630. .parent_names = gcc_pxo_pll8,
  1631. .num_parents = 2,
  1632. .ops = &clk_rcg_ops,
  1633. },
  1634. },
  1635. };
  1636. static struct clk_branch prng_clk = {
  1637. .halt_reg = 0x2fd8,
  1638. .halt_check = BRANCH_HALT_VOTED,
  1639. .halt_bit = 10,
  1640. .clkr = {
  1641. .enable_reg = 0x3080,
  1642. .enable_mask = BIT(10),
  1643. .hw.init = &(struct clk_init_data){
  1644. .name = "prng_clk",
  1645. .parent_names = (const char *[]){ "prng_src" },
  1646. .num_parents = 1,
  1647. .ops = &clk_branch_ops,
  1648. },
  1649. },
  1650. };
  1651. static const struct freq_tbl clk_tbl_sdc[] = {
  1652. { 144000, P_PXO, 3, 2, 125 },
  1653. { 400000, P_PLL8, 4, 1, 240 },
  1654. { 16000000, P_PLL8, 4, 1, 6 },
  1655. { 17070000, P_PLL8, 1, 2, 45 },
  1656. { 20210000, P_PLL8, 1, 1, 19 },
  1657. { 24000000, P_PLL8, 4, 1, 4 },
  1658. { 48000000, P_PLL8, 4, 1, 2 },
  1659. { 64000000, P_PLL8, 3, 1, 2 },
  1660. { 96000000, P_PLL8, 4, 0, 0 },
  1661. { 192000000, P_PLL8, 2, 0, 0 },
  1662. { }
  1663. };
  1664. static struct clk_rcg sdc1_src = {
  1665. .ns_reg = 0x282c,
  1666. .md_reg = 0x2828,
  1667. .mn = {
  1668. .mnctr_en_bit = 8,
  1669. .mnctr_reset_bit = 7,
  1670. .mnctr_mode_shift = 5,
  1671. .n_val_shift = 16,
  1672. .m_val_shift = 16,
  1673. .width = 8,
  1674. },
  1675. .p = {
  1676. .pre_div_shift = 3,
  1677. .pre_div_width = 2,
  1678. },
  1679. .s = {
  1680. .src_sel_shift = 0,
  1681. .parent_map = gcc_pxo_pll8_map,
  1682. },
  1683. .freq_tbl = clk_tbl_sdc,
  1684. .clkr = {
  1685. .enable_reg = 0x282c,
  1686. .enable_mask = BIT(11),
  1687. .hw.init = &(struct clk_init_data){
  1688. .name = "sdc1_src",
  1689. .parent_names = gcc_pxo_pll8,
  1690. .num_parents = 2,
  1691. .ops = &clk_rcg_ops,
  1692. },
  1693. }
  1694. };
  1695. static struct clk_branch sdc1_clk = {
  1696. .halt_reg = 0x2fc8,
  1697. .halt_bit = 6,
  1698. .clkr = {
  1699. .enable_reg = 0x282c,
  1700. .enable_mask = BIT(9),
  1701. .hw.init = &(struct clk_init_data){
  1702. .name = "sdc1_clk",
  1703. .parent_names = (const char *[]){ "sdc1_src" },
  1704. .num_parents = 1,
  1705. .ops = &clk_branch_ops,
  1706. .flags = CLK_SET_RATE_PARENT,
  1707. },
  1708. },
  1709. };
  1710. static struct clk_rcg sdc2_src = {
  1711. .ns_reg = 0x284c,
  1712. .md_reg = 0x2848,
  1713. .mn = {
  1714. .mnctr_en_bit = 8,
  1715. .mnctr_reset_bit = 7,
  1716. .mnctr_mode_shift = 5,
  1717. .n_val_shift = 16,
  1718. .m_val_shift = 16,
  1719. .width = 8,
  1720. },
  1721. .p = {
  1722. .pre_div_shift = 3,
  1723. .pre_div_width = 2,
  1724. },
  1725. .s = {
  1726. .src_sel_shift = 0,
  1727. .parent_map = gcc_pxo_pll8_map,
  1728. },
  1729. .freq_tbl = clk_tbl_sdc,
  1730. .clkr = {
  1731. .enable_reg = 0x284c,
  1732. .enable_mask = BIT(11),
  1733. .hw.init = &(struct clk_init_data){
  1734. .name = "sdc2_src",
  1735. .parent_names = gcc_pxo_pll8,
  1736. .num_parents = 2,
  1737. .ops = &clk_rcg_ops,
  1738. },
  1739. }
  1740. };
  1741. static struct clk_branch sdc2_clk = {
  1742. .halt_reg = 0x2fc8,
  1743. .halt_bit = 5,
  1744. .clkr = {
  1745. .enable_reg = 0x284c,
  1746. .enable_mask = BIT(9),
  1747. .hw.init = &(struct clk_init_data){
  1748. .name = "sdc2_clk",
  1749. .parent_names = (const char *[]){ "sdc2_src" },
  1750. .num_parents = 1,
  1751. .ops = &clk_branch_ops,
  1752. .flags = CLK_SET_RATE_PARENT,
  1753. },
  1754. },
  1755. };
  1756. static struct clk_rcg sdc3_src = {
  1757. .ns_reg = 0x286c,
  1758. .md_reg = 0x2868,
  1759. .mn = {
  1760. .mnctr_en_bit = 8,
  1761. .mnctr_reset_bit = 7,
  1762. .mnctr_mode_shift = 5,
  1763. .n_val_shift = 16,
  1764. .m_val_shift = 16,
  1765. .width = 8,
  1766. },
  1767. .p = {
  1768. .pre_div_shift = 3,
  1769. .pre_div_width = 2,
  1770. },
  1771. .s = {
  1772. .src_sel_shift = 0,
  1773. .parent_map = gcc_pxo_pll8_map,
  1774. },
  1775. .freq_tbl = clk_tbl_sdc,
  1776. .clkr = {
  1777. .enable_reg = 0x286c,
  1778. .enable_mask = BIT(11),
  1779. .hw.init = &(struct clk_init_data){
  1780. .name = "sdc3_src",
  1781. .parent_names = gcc_pxo_pll8,
  1782. .num_parents = 2,
  1783. .ops = &clk_rcg_ops,
  1784. },
  1785. }
  1786. };
  1787. static struct clk_branch sdc3_clk = {
  1788. .halt_reg = 0x2fc8,
  1789. .halt_bit = 4,
  1790. .clkr = {
  1791. .enable_reg = 0x286c,
  1792. .enable_mask = BIT(9),
  1793. .hw.init = &(struct clk_init_data){
  1794. .name = "sdc3_clk",
  1795. .parent_names = (const char *[]){ "sdc3_src" },
  1796. .num_parents = 1,
  1797. .ops = &clk_branch_ops,
  1798. .flags = CLK_SET_RATE_PARENT,
  1799. },
  1800. },
  1801. };
  1802. static struct clk_rcg sdc4_src = {
  1803. .ns_reg = 0x288c,
  1804. .md_reg = 0x2888,
  1805. .mn = {
  1806. .mnctr_en_bit = 8,
  1807. .mnctr_reset_bit = 7,
  1808. .mnctr_mode_shift = 5,
  1809. .n_val_shift = 16,
  1810. .m_val_shift = 16,
  1811. .width = 8,
  1812. },
  1813. .p = {
  1814. .pre_div_shift = 3,
  1815. .pre_div_width = 2,
  1816. },
  1817. .s = {
  1818. .src_sel_shift = 0,
  1819. .parent_map = gcc_pxo_pll8_map,
  1820. },
  1821. .freq_tbl = clk_tbl_sdc,
  1822. .clkr = {
  1823. .enable_reg = 0x288c,
  1824. .enable_mask = BIT(11),
  1825. .hw.init = &(struct clk_init_data){
  1826. .name = "sdc4_src",
  1827. .parent_names = gcc_pxo_pll8,
  1828. .num_parents = 2,
  1829. .ops = &clk_rcg_ops,
  1830. },
  1831. }
  1832. };
  1833. static struct clk_branch sdc4_clk = {
  1834. .halt_reg = 0x2fc8,
  1835. .halt_bit = 3,
  1836. .clkr = {
  1837. .enable_reg = 0x288c,
  1838. .enable_mask = BIT(9),
  1839. .hw.init = &(struct clk_init_data){
  1840. .name = "sdc4_clk",
  1841. .parent_names = (const char *[]){ "sdc4_src" },
  1842. .num_parents = 1,
  1843. .ops = &clk_branch_ops,
  1844. .flags = CLK_SET_RATE_PARENT,
  1845. },
  1846. },
  1847. };
  1848. static struct clk_rcg sdc5_src = {
  1849. .ns_reg = 0x28ac,
  1850. .md_reg = 0x28a8,
  1851. .mn = {
  1852. .mnctr_en_bit = 8,
  1853. .mnctr_reset_bit = 7,
  1854. .mnctr_mode_shift = 5,
  1855. .n_val_shift = 16,
  1856. .m_val_shift = 16,
  1857. .width = 8,
  1858. },
  1859. .p = {
  1860. .pre_div_shift = 3,
  1861. .pre_div_width = 2,
  1862. },
  1863. .s = {
  1864. .src_sel_shift = 0,
  1865. .parent_map = gcc_pxo_pll8_map,
  1866. },
  1867. .freq_tbl = clk_tbl_sdc,
  1868. .clkr = {
  1869. .enable_reg = 0x28ac,
  1870. .enable_mask = BIT(11),
  1871. .hw.init = &(struct clk_init_data){
  1872. .name = "sdc5_src",
  1873. .parent_names = gcc_pxo_pll8,
  1874. .num_parents = 2,
  1875. .ops = &clk_rcg_ops,
  1876. },
  1877. }
  1878. };
  1879. static struct clk_branch sdc5_clk = {
  1880. .halt_reg = 0x2fc8,
  1881. .halt_bit = 2,
  1882. .clkr = {
  1883. .enable_reg = 0x28ac,
  1884. .enable_mask = BIT(9),
  1885. .hw.init = &(struct clk_init_data){
  1886. .name = "sdc5_clk",
  1887. .parent_names = (const char *[]){ "sdc5_src" },
  1888. .num_parents = 1,
  1889. .ops = &clk_branch_ops,
  1890. .flags = CLK_SET_RATE_PARENT,
  1891. },
  1892. },
  1893. };
  1894. static const struct freq_tbl clk_tbl_tsif_ref[] = {
  1895. { 105000, P_PXO, 1, 1, 256 },
  1896. { }
  1897. };
  1898. static struct clk_rcg tsif_ref_src = {
  1899. .ns_reg = 0x2710,
  1900. .md_reg = 0x270c,
  1901. .mn = {
  1902. .mnctr_en_bit = 8,
  1903. .mnctr_reset_bit = 7,
  1904. .mnctr_mode_shift = 5,
  1905. .n_val_shift = 16,
  1906. .m_val_shift = 16,
  1907. .width = 16,
  1908. },
  1909. .p = {
  1910. .pre_div_shift = 3,
  1911. .pre_div_width = 2,
  1912. },
  1913. .s = {
  1914. .src_sel_shift = 0,
  1915. .parent_map = gcc_pxo_pll8_map,
  1916. },
  1917. .freq_tbl = clk_tbl_tsif_ref,
  1918. .clkr = {
  1919. .enable_reg = 0x2710,
  1920. .enable_mask = BIT(11),
  1921. .hw.init = &(struct clk_init_data){
  1922. .name = "tsif_ref_src",
  1923. .parent_names = gcc_pxo_pll8,
  1924. .num_parents = 2,
  1925. .ops = &clk_rcg_ops,
  1926. .flags = CLK_SET_RATE_GATE,
  1927. },
  1928. }
  1929. };
  1930. static struct clk_branch tsif_ref_clk = {
  1931. .halt_reg = 0x2fd4,
  1932. .halt_bit = 5,
  1933. .clkr = {
  1934. .enable_reg = 0x2710,
  1935. .enable_mask = BIT(9),
  1936. .hw.init = &(struct clk_init_data){
  1937. .name = "tsif_ref_clk",
  1938. .parent_names = (const char *[]){ "tsif_ref_src" },
  1939. .num_parents = 1,
  1940. .ops = &clk_branch_ops,
  1941. .flags = CLK_SET_RATE_PARENT,
  1942. },
  1943. },
  1944. };
  1945. static const struct freq_tbl clk_tbl_usb[] = {
  1946. { 60000000, P_PLL8, 1, 5, 32 },
  1947. { }
  1948. };
  1949. static struct clk_rcg usb_hs1_xcvr_src = {
  1950. .ns_reg = 0x290c,
  1951. .md_reg = 0x2908,
  1952. .mn = {
  1953. .mnctr_en_bit = 8,
  1954. .mnctr_reset_bit = 7,
  1955. .mnctr_mode_shift = 5,
  1956. .n_val_shift = 16,
  1957. .m_val_shift = 16,
  1958. .width = 8,
  1959. },
  1960. .p = {
  1961. .pre_div_shift = 3,
  1962. .pre_div_width = 2,
  1963. },
  1964. .s = {
  1965. .src_sel_shift = 0,
  1966. .parent_map = gcc_pxo_pll8_map,
  1967. },
  1968. .freq_tbl = clk_tbl_usb,
  1969. .clkr = {
  1970. .enable_reg = 0x290c,
  1971. .enable_mask = BIT(11),
  1972. .hw.init = &(struct clk_init_data){
  1973. .name = "usb_hs1_xcvr_src",
  1974. .parent_names = gcc_pxo_pll8,
  1975. .num_parents = 2,
  1976. .ops = &clk_rcg_ops,
  1977. .flags = CLK_SET_RATE_GATE,
  1978. },
  1979. }
  1980. };
  1981. static struct clk_branch usb_hs1_xcvr_clk = {
  1982. .halt_reg = 0x2fc8,
  1983. .halt_bit = 0,
  1984. .clkr = {
  1985. .enable_reg = 0x290c,
  1986. .enable_mask = BIT(9),
  1987. .hw.init = &(struct clk_init_data){
  1988. .name = "usb_hs1_xcvr_clk",
  1989. .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
  1990. .num_parents = 1,
  1991. .ops = &clk_branch_ops,
  1992. .flags = CLK_SET_RATE_PARENT,
  1993. },
  1994. },
  1995. };
  1996. static struct clk_rcg usb_hs3_xcvr_src = {
  1997. .ns_reg = 0x370c,
  1998. .md_reg = 0x3708,
  1999. .mn = {
  2000. .mnctr_en_bit = 8,
  2001. .mnctr_reset_bit = 7,
  2002. .mnctr_mode_shift = 5,
  2003. .n_val_shift = 16,
  2004. .m_val_shift = 16,
  2005. .width = 8,
  2006. },
  2007. .p = {
  2008. .pre_div_shift = 3,
  2009. .pre_div_width = 2,
  2010. },
  2011. .s = {
  2012. .src_sel_shift = 0,
  2013. .parent_map = gcc_pxo_pll8_map,
  2014. },
  2015. .freq_tbl = clk_tbl_usb,
  2016. .clkr = {
  2017. .enable_reg = 0x370c,
  2018. .enable_mask = BIT(11),
  2019. .hw.init = &(struct clk_init_data){
  2020. .name = "usb_hs3_xcvr_src",
  2021. .parent_names = gcc_pxo_pll8,
  2022. .num_parents = 2,
  2023. .ops = &clk_rcg_ops,
  2024. .flags = CLK_SET_RATE_GATE,
  2025. },
  2026. }
  2027. };
  2028. static struct clk_branch usb_hs3_xcvr_clk = {
  2029. .halt_reg = 0x2fc8,
  2030. .halt_bit = 30,
  2031. .clkr = {
  2032. .enable_reg = 0x370c,
  2033. .enable_mask = BIT(9),
  2034. .hw.init = &(struct clk_init_data){
  2035. .name = "usb_hs3_xcvr_clk",
  2036. .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
  2037. .num_parents = 1,
  2038. .ops = &clk_branch_ops,
  2039. .flags = CLK_SET_RATE_PARENT,
  2040. },
  2041. },
  2042. };
  2043. static struct clk_rcg usb_hs4_xcvr_src = {
  2044. .ns_reg = 0x372c,
  2045. .md_reg = 0x3728,
  2046. .mn = {
  2047. .mnctr_en_bit = 8,
  2048. .mnctr_reset_bit = 7,
  2049. .mnctr_mode_shift = 5,
  2050. .n_val_shift = 16,
  2051. .m_val_shift = 16,
  2052. .width = 8,
  2053. },
  2054. .p = {
  2055. .pre_div_shift = 3,
  2056. .pre_div_width = 2,
  2057. },
  2058. .s = {
  2059. .src_sel_shift = 0,
  2060. .parent_map = gcc_pxo_pll8_map,
  2061. },
  2062. .freq_tbl = clk_tbl_usb,
  2063. .clkr = {
  2064. .enable_reg = 0x372c,
  2065. .enable_mask = BIT(11),
  2066. .hw.init = &(struct clk_init_data){
  2067. .name = "usb_hs4_xcvr_src",
  2068. .parent_names = gcc_pxo_pll8,
  2069. .num_parents = 2,
  2070. .ops = &clk_rcg_ops,
  2071. .flags = CLK_SET_RATE_GATE,
  2072. },
  2073. }
  2074. };
  2075. static struct clk_branch usb_hs4_xcvr_clk = {
  2076. .halt_reg = 0x2fc8,
  2077. .halt_bit = 2,
  2078. .clkr = {
  2079. .enable_reg = 0x372c,
  2080. .enable_mask = BIT(9),
  2081. .hw.init = &(struct clk_init_data){
  2082. .name = "usb_hs4_xcvr_clk",
  2083. .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
  2084. .num_parents = 1,
  2085. .ops = &clk_branch_ops,
  2086. .flags = CLK_SET_RATE_PARENT,
  2087. },
  2088. },
  2089. };
  2090. static struct clk_rcg usb_hsic_xcvr_fs_src = {
  2091. .ns_reg = 0x2928,
  2092. .md_reg = 0x2924,
  2093. .mn = {
  2094. .mnctr_en_bit = 8,
  2095. .mnctr_reset_bit = 7,
  2096. .mnctr_mode_shift = 5,
  2097. .n_val_shift = 16,
  2098. .m_val_shift = 16,
  2099. .width = 8,
  2100. },
  2101. .p = {
  2102. .pre_div_shift = 3,
  2103. .pre_div_width = 2,
  2104. },
  2105. .s = {
  2106. .src_sel_shift = 0,
  2107. .parent_map = gcc_pxo_pll8_map,
  2108. },
  2109. .freq_tbl = clk_tbl_usb,
  2110. .clkr = {
  2111. .enable_reg = 0x2928,
  2112. .enable_mask = BIT(11),
  2113. .hw.init = &(struct clk_init_data){
  2114. .name = "usb_hsic_xcvr_fs_src",
  2115. .parent_names = gcc_pxo_pll8,
  2116. .num_parents = 2,
  2117. .ops = &clk_rcg_ops,
  2118. .flags = CLK_SET_RATE_GATE,
  2119. },
  2120. }
  2121. };
  2122. static const char * const usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
  2123. static struct clk_branch usb_hsic_xcvr_fs_clk = {
  2124. .halt_reg = 0x2fc8,
  2125. .halt_bit = 2,
  2126. .clkr = {
  2127. .enable_reg = 0x2928,
  2128. .enable_mask = BIT(9),
  2129. .hw.init = &(struct clk_init_data){
  2130. .name = "usb_hsic_xcvr_fs_clk",
  2131. .parent_names = usb_hsic_xcvr_fs_src_p,
  2132. .num_parents = 1,
  2133. .ops = &clk_branch_ops,
  2134. .flags = CLK_SET_RATE_PARENT,
  2135. },
  2136. },
  2137. };
  2138. static struct clk_branch usb_hsic_system_clk = {
  2139. .halt_reg = 0x2fcc,
  2140. .halt_bit = 24,
  2141. .clkr = {
  2142. .enable_reg = 0x292c,
  2143. .enable_mask = BIT(4),
  2144. .hw.init = &(struct clk_init_data){
  2145. .parent_names = usb_hsic_xcvr_fs_src_p,
  2146. .num_parents = 1,
  2147. .name = "usb_hsic_system_clk",
  2148. .ops = &clk_branch_ops,
  2149. .flags = CLK_SET_RATE_PARENT,
  2150. },
  2151. },
  2152. };
  2153. static struct clk_branch usb_hsic_hsic_clk = {
  2154. .halt_reg = 0x2fcc,
  2155. .halt_bit = 19,
  2156. .clkr = {
  2157. .enable_reg = 0x2b44,
  2158. .enable_mask = BIT(0),
  2159. .hw.init = &(struct clk_init_data){
  2160. .parent_names = (const char *[]){ "pll14_vote" },
  2161. .num_parents = 1,
  2162. .name = "usb_hsic_hsic_clk",
  2163. .ops = &clk_branch_ops,
  2164. },
  2165. },
  2166. };
  2167. static struct clk_branch usb_hsic_hsio_cal_clk = {
  2168. .halt_reg = 0x2fcc,
  2169. .halt_bit = 23,
  2170. .clkr = {
  2171. .enable_reg = 0x2b48,
  2172. .enable_mask = BIT(0),
  2173. .hw.init = &(struct clk_init_data){
  2174. .name = "usb_hsic_hsio_cal_clk",
  2175. .ops = &clk_branch_ops,
  2176. },
  2177. },
  2178. };
  2179. static struct clk_rcg usb_fs1_xcvr_fs_src = {
  2180. .ns_reg = 0x2968,
  2181. .md_reg = 0x2964,
  2182. .mn = {
  2183. .mnctr_en_bit = 8,
  2184. .mnctr_reset_bit = 7,
  2185. .mnctr_mode_shift = 5,
  2186. .n_val_shift = 16,
  2187. .m_val_shift = 16,
  2188. .width = 8,
  2189. },
  2190. .p = {
  2191. .pre_div_shift = 3,
  2192. .pre_div_width = 2,
  2193. },
  2194. .s = {
  2195. .src_sel_shift = 0,
  2196. .parent_map = gcc_pxo_pll8_map,
  2197. },
  2198. .freq_tbl = clk_tbl_usb,
  2199. .clkr = {
  2200. .enable_reg = 0x2968,
  2201. .enable_mask = BIT(11),
  2202. .hw.init = &(struct clk_init_data){
  2203. .name = "usb_fs1_xcvr_fs_src",
  2204. .parent_names = gcc_pxo_pll8,
  2205. .num_parents = 2,
  2206. .ops = &clk_rcg_ops,
  2207. .flags = CLK_SET_RATE_GATE,
  2208. },
  2209. }
  2210. };
  2211. static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
  2212. static struct clk_branch usb_fs1_xcvr_fs_clk = {
  2213. .halt_reg = 0x2fcc,
  2214. .halt_bit = 15,
  2215. .clkr = {
  2216. .enable_reg = 0x2968,
  2217. .enable_mask = BIT(9),
  2218. .hw.init = &(struct clk_init_data){
  2219. .name = "usb_fs1_xcvr_fs_clk",
  2220. .parent_names = usb_fs1_xcvr_fs_src_p,
  2221. .num_parents = 1,
  2222. .ops = &clk_branch_ops,
  2223. .flags = CLK_SET_RATE_PARENT,
  2224. },
  2225. },
  2226. };
  2227. static struct clk_branch usb_fs1_system_clk = {
  2228. .halt_reg = 0x2fcc,
  2229. .halt_bit = 16,
  2230. .clkr = {
  2231. .enable_reg = 0x296c,
  2232. .enable_mask = BIT(4),
  2233. .hw.init = &(struct clk_init_data){
  2234. .parent_names = usb_fs1_xcvr_fs_src_p,
  2235. .num_parents = 1,
  2236. .name = "usb_fs1_system_clk",
  2237. .ops = &clk_branch_ops,
  2238. .flags = CLK_SET_RATE_PARENT,
  2239. },
  2240. },
  2241. };
  2242. static struct clk_rcg usb_fs2_xcvr_fs_src = {
  2243. .ns_reg = 0x2988,
  2244. .md_reg = 0x2984,
  2245. .mn = {
  2246. .mnctr_en_bit = 8,
  2247. .mnctr_reset_bit = 7,
  2248. .mnctr_mode_shift = 5,
  2249. .n_val_shift = 16,
  2250. .m_val_shift = 16,
  2251. .width = 8,
  2252. },
  2253. .p = {
  2254. .pre_div_shift = 3,
  2255. .pre_div_width = 2,
  2256. },
  2257. .s = {
  2258. .src_sel_shift = 0,
  2259. .parent_map = gcc_pxo_pll8_map,
  2260. },
  2261. .freq_tbl = clk_tbl_usb,
  2262. .clkr = {
  2263. .enable_reg = 0x2988,
  2264. .enable_mask = BIT(11),
  2265. .hw.init = &(struct clk_init_data){
  2266. .name = "usb_fs2_xcvr_fs_src",
  2267. .parent_names = gcc_pxo_pll8,
  2268. .num_parents = 2,
  2269. .ops = &clk_rcg_ops,
  2270. .flags = CLK_SET_RATE_GATE,
  2271. },
  2272. }
  2273. };
  2274. static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
  2275. static struct clk_branch usb_fs2_xcvr_fs_clk = {
  2276. .halt_reg = 0x2fcc,
  2277. .halt_bit = 12,
  2278. .clkr = {
  2279. .enable_reg = 0x2988,
  2280. .enable_mask = BIT(9),
  2281. .hw.init = &(struct clk_init_data){
  2282. .name = "usb_fs2_xcvr_fs_clk",
  2283. .parent_names = usb_fs2_xcvr_fs_src_p,
  2284. .num_parents = 1,
  2285. .ops = &clk_branch_ops,
  2286. .flags = CLK_SET_RATE_PARENT,
  2287. },
  2288. },
  2289. };
  2290. static struct clk_branch usb_fs2_system_clk = {
  2291. .halt_reg = 0x2fcc,
  2292. .halt_bit = 13,
  2293. .clkr = {
  2294. .enable_reg = 0x298c,
  2295. .enable_mask = BIT(4),
  2296. .hw.init = &(struct clk_init_data){
  2297. .name = "usb_fs2_system_clk",
  2298. .parent_names = usb_fs2_xcvr_fs_src_p,
  2299. .num_parents = 1,
  2300. .ops = &clk_branch_ops,
  2301. .flags = CLK_SET_RATE_PARENT,
  2302. },
  2303. },
  2304. };
  2305. static struct clk_branch ce1_core_clk = {
  2306. .hwcg_reg = 0x2724,
  2307. .hwcg_bit = 6,
  2308. .halt_reg = 0x2fd4,
  2309. .halt_bit = 27,
  2310. .clkr = {
  2311. .enable_reg = 0x2724,
  2312. .enable_mask = BIT(4),
  2313. .hw.init = &(struct clk_init_data){
  2314. .name = "ce1_core_clk",
  2315. .ops = &clk_branch_ops,
  2316. },
  2317. },
  2318. };
  2319. static struct clk_branch ce1_h_clk = {
  2320. .halt_reg = 0x2fd4,
  2321. .halt_bit = 1,
  2322. .clkr = {
  2323. .enable_reg = 0x2720,
  2324. .enable_mask = BIT(4),
  2325. .hw.init = &(struct clk_init_data){
  2326. .name = "ce1_h_clk",
  2327. .ops = &clk_branch_ops,
  2328. },
  2329. },
  2330. };
  2331. static struct clk_branch dma_bam_h_clk = {
  2332. .hwcg_reg = 0x25c0,
  2333. .hwcg_bit = 6,
  2334. .halt_reg = 0x2fc8,
  2335. .halt_bit = 12,
  2336. .clkr = {
  2337. .enable_reg = 0x25c0,
  2338. .enable_mask = BIT(4),
  2339. .hw.init = &(struct clk_init_data){
  2340. .name = "dma_bam_h_clk",
  2341. .ops = &clk_branch_ops,
  2342. },
  2343. },
  2344. };
  2345. static struct clk_branch gsbi1_h_clk = {
  2346. .hwcg_reg = 0x29c0,
  2347. .hwcg_bit = 6,
  2348. .halt_reg = 0x2fcc,
  2349. .halt_bit = 11,
  2350. .clkr = {
  2351. .enable_reg = 0x29c0,
  2352. .enable_mask = BIT(4),
  2353. .hw.init = &(struct clk_init_data){
  2354. .name = "gsbi1_h_clk",
  2355. .ops = &clk_branch_ops,
  2356. },
  2357. },
  2358. };
  2359. static struct clk_branch gsbi2_h_clk = {
  2360. .hwcg_reg = 0x29e0,
  2361. .hwcg_bit = 6,
  2362. .halt_reg = 0x2fcc,
  2363. .halt_bit = 7,
  2364. .clkr = {
  2365. .enable_reg = 0x29e0,
  2366. .enable_mask = BIT(4),
  2367. .hw.init = &(struct clk_init_data){
  2368. .name = "gsbi2_h_clk",
  2369. .ops = &clk_branch_ops,
  2370. },
  2371. },
  2372. };
  2373. static struct clk_branch gsbi3_h_clk = {
  2374. .hwcg_reg = 0x2a00,
  2375. .hwcg_bit = 6,
  2376. .halt_reg = 0x2fcc,
  2377. .halt_bit = 3,
  2378. .clkr = {
  2379. .enable_reg = 0x2a00,
  2380. .enable_mask = BIT(4),
  2381. .hw.init = &(struct clk_init_data){
  2382. .name = "gsbi3_h_clk",
  2383. .ops = &clk_branch_ops,
  2384. },
  2385. },
  2386. };
  2387. static struct clk_branch gsbi4_h_clk = {
  2388. .hwcg_reg = 0x2a20,
  2389. .hwcg_bit = 6,
  2390. .halt_reg = 0x2fd0,
  2391. .halt_bit = 27,
  2392. .clkr = {
  2393. .enable_reg = 0x2a20,
  2394. .enable_mask = BIT(4),
  2395. .hw.init = &(struct clk_init_data){
  2396. .name = "gsbi4_h_clk",
  2397. .ops = &clk_branch_ops,
  2398. },
  2399. },
  2400. };
  2401. static struct clk_branch gsbi5_h_clk = {
  2402. .hwcg_reg = 0x2a40,
  2403. .hwcg_bit = 6,
  2404. .halt_reg = 0x2fd0,
  2405. .halt_bit = 23,
  2406. .clkr = {
  2407. .enable_reg = 0x2a40,
  2408. .enable_mask = BIT(4),
  2409. .hw.init = &(struct clk_init_data){
  2410. .name = "gsbi5_h_clk",
  2411. .ops = &clk_branch_ops,
  2412. },
  2413. },
  2414. };
  2415. static struct clk_branch gsbi6_h_clk = {
  2416. .hwcg_reg = 0x2a60,
  2417. .hwcg_bit = 6,
  2418. .halt_reg = 0x2fd0,
  2419. .halt_bit = 19,
  2420. .clkr = {
  2421. .enable_reg = 0x2a60,
  2422. .enable_mask = BIT(4),
  2423. .hw.init = &(struct clk_init_data){
  2424. .name = "gsbi6_h_clk",
  2425. .ops = &clk_branch_ops,
  2426. },
  2427. },
  2428. };
  2429. static struct clk_branch gsbi7_h_clk = {
  2430. .hwcg_reg = 0x2a80,
  2431. .hwcg_bit = 6,
  2432. .halt_reg = 0x2fd0,
  2433. .halt_bit = 15,
  2434. .clkr = {
  2435. .enable_reg = 0x2a80,
  2436. .enable_mask = BIT(4),
  2437. .hw.init = &(struct clk_init_data){
  2438. .name = "gsbi7_h_clk",
  2439. .ops = &clk_branch_ops,
  2440. },
  2441. },
  2442. };
  2443. static struct clk_branch gsbi8_h_clk = {
  2444. .hwcg_reg = 0x2aa0,
  2445. .hwcg_bit = 6,
  2446. .halt_reg = 0x2fd0,
  2447. .halt_bit = 11,
  2448. .clkr = {
  2449. .enable_reg = 0x2aa0,
  2450. .enable_mask = BIT(4),
  2451. .hw.init = &(struct clk_init_data){
  2452. .name = "gsbi8_h_clk",
  2453. .ops = &clk_branch_ops,
  2454. },
  2455. },
  2456. };
  2457. static struct clk_branch gsbi9_h_clk = {
  2458. .hwcg_reg = 0x2ac0,
  2459. .hwcg_bit = 6,
  2460. .halt_reg = 0x2fd0,
  2461. .halt_bit = 7,
  2462. .clkr = {
  2463. .enable_reg = 0x2ac0,
  2464. .enable_mask = BIT(4),
  2465. .hw.init = &(struct clk_init_data){
  2466. .name = "gsbi9_h_clk",
  2467. .ops = &clk_branch_ops,
  2468. },
  2469. },
  2470. };
  2471. static struct clk_branch gsbi10_h_clk = {
  2472. .hwcg_reg = 0x2ae0,
  2473. .hwcg_bit = 6,
  2474. .halt_reg = 0x2fd0,
  2475. .halt_bit = 3,
  2476. .clkr = {
  2477. .enable_reg = 0x2ae0,
  2478. .enable_mask = BIT(4),
  2479. .hw.init = &(struct clk_init_data){
  2480. .name = "gsbi10_h_clk",
  2481. .ops = &clk_branch_ops,
  2482. },
  2483. },
  2484. };
  2485. static struct clk_branch gsbi11_h_clk = {
  2486. .hwcg_reg = 0x2b00,
  2487. .hwcg_bit = 6,
  2488. .halt_reg = 0x2fd4,
  2489. .halt_bit = 18,
  2490. .clkr = {
  2491. .enable_reg = 0x2b00,
  2492. .enable_mask = BIT(4),
  2493. .hw.init = &(struct clk_init_data){
  2494. .name = "gsbi11_h_clk",
  2495. .ops = &clk_branch_ops,
  2496. },
  2497. },
  2498. };
  2499. static struct clk_branch gsbi12_h_clk = {
  2500. .hwcg_reg = 0x2b20,
  2501. .hwcg_bit = 6,
  2502. .halt_reg = 0x2fd4,
  2503. .halt_bit = 14,
  2504. .clkr = {
  2505. .enable_reg = 0x2b20,
  2506. .enable_mask = BIT(4),
  2507. .hw.init = &(struct clk_init_data){
  2508. .name = "gsbi12_h_clk",
  2509. .ops = &clk_branch_ops,
  2510. },
  2511. },
  2512. };
  2513. static struct clk_branch tsif_h_clk = {
  2514. .hwcg_reg = 0x2700,
  2515. .hwcg_bit = 6,
  2516. .halt_reg = 0x2fd4,
  2517. .halt_bit = 7,
  2518. .clkr = {
  2519. .enable_reg = 0x2700,
  2520. .enable_mask = BIT(4),
  2521. .hw.init = &(struct clk_init_data){
  2522. .name = "tsif_h_clk",
  2523. .ops = &clk_branch_ops,
  2524. },
  2525. },
  2526. };
  2527. static struct clk_branch usb_fs1_h_clk = {
  2528. .halt_reg = 0x2fcc,
  2529. .halt_bit = 17,
  2530. .clkr = {
  2531. .enable_reg = 0x2960,
  2532. .enable_mask = BIT(4),
  2533. .hw.init = &(struct clk_init_data){
  2534. .name = "usb_fs1_h_clk",
  2535. .ops = &clk_branch_ops,
  2536. },
  2537. },
  2538. };
  2539. static struct clk_branch usb_fs2_h_clk = {
  2540. .halt_reg = 0x2fcc,
  2541. .halt_bit = 14,
  2542. .clkr = {
  2543. .enable_reg = 0x2980,
  2544. .enable_mask = BIT(4),
  2545. .hw.init = &(struct clk_init_data){
  2546. .name = "usb_fs2_h_clk",
  2547. .ops = &clk_branch_ops,
  2548. },
  2549. },
  2550. };
  2551. static struct clk_branch usb_hs1_h_clk = {
  2552. .hwcg_reg = 0x2900,
  2553. .hwcg_bit = 6,
  2554. .halt_reg = 0x2fc8,
  2555. .halt_bit = 1,
  2556. .clkr = {
  2557. .enable_reg = 0x2900,
  2558. .enable_mask = BIT(4),
  2559. .hw.init = &(struct clk_init_data){
  2560. .name = "usb_hs1_h_clk",
  2561. .ops = &clk_branch_ops,
  2562. },
  2563. },
  2564. };
  2565. static struct clk_branch usb_hs3_h_clk = {
  2566. .halt_reg = 0x2fc8,
  2567. .halt_bit = 31,
  2568. .clkr = {
  2569. .enable_reg = 0x3700,
  2570. .enable_mask = BIT(4),
  2571. .hw.init = &(struct clk_init_data){
  2572. .name = "usb_hs3_h_clk",
  2573. .ops = &clk_branch_ops,
  2574. },
  2575. },
  2576. };
  2577. static struct clk_branch usb_hs4_h_clk = {
  2578. .halt_reg = 0x2fc8,
  2579. .halt_bit = 7,
  2580. .clkr = {
  2581. .enable_reg = 0x3720,
  2582. .enable_mask = BIT(4),
  2583. .hw.init = &(struct clk_init_data){
  2584. .name = "usb_hs4_h_clk",
  2585. .ops = &clk_branch_ops,
  2586. },
  2587. },
  2588. };
  2589. static struct clk_branch usb_hsic_h_clk = {
  2590. .halt_reg = 0x2fcc,
  2591. .halt_bit = 28,
  2592. .clkr = {
  2593. .enable_reg = 0x2920,
  2594. .enable_mask = BIT(4),
  2595. .hw.init = &(struct clk_init_data){
  2596. .name = "usb_hsic_h_clk",
  2597. .ops = &clk_branch_ops,
  2598. },
  2599. },
  2600. };
  2601. static struct clk_branch sdc1_h_clk = {
  2602. .hwcg_reg = 0x2820,
  2603. .hwcg_bit = 6,
  2604. .halt_reg = 0x2fc8,
  2605. .halt_bit = 11,
  2606. .clkr = {
  2607. .enable_reg = 0x2820,
  2608. .enable_mask = BIT(4),
  2609. .hw.init = &(struct clk_init_data){
  2610. .name = "sdc1_h_clk",
  2611. .ops = &clk_branch_ops,
  2612. },
  2613. },
  2614. };
  2615. static struct clk_branch sdc2_h_clk = {
  2616. .hwcg_reg = 0x2840,
  2617. .hwcg_bit = 6,
  2618. .halt_reg = 0x2fc8,
  2619. .halt_bit = 10,
  2620. .clkr = {
  2621. .enable_reg = 0x2840,
  2622. .enable_mask = BIT(4),
  2623. .hw.init = &(struct clk_init_data){
  2624. .name = "sdc2_h_clk",
  2625. .ops = &clk_branch_ops,
  2626. },
  2627. },
  2628. };
  2629. static struct clk_branch sdc3_h_clk = {
  2630. .hwcg_reg = 0x2860,
  2631. .hwcg_bit = 6,
  2632. .halt_reg = 0x2fc8,
  2633. .halt_bit = 9,
  2634. .clkr = {
  2635. .enable_reg = 0x2860,
  2636. .enable_mask = BIT(4),
  2637. .hw.init = &(struct clk_init_data){
  2638. .name = "sdc3_h_clk",
  2639. .ops = &clk_branch_ops,
  2640. },
  2641. },
  2642. };
  2643. static struct clk_branch sdc4_h_clk = {
  2644. .hwcg_reg = 0x2880,
  2645. .hwcg_bit = 6,
  2646. .halt_reg = 0x2fc8,
  2647. .halt_bit = 8,
  2648. .clkr = {
  2649. .enable_reg = 0x2880,
  2650. .enable_mask = BIT(4),
  2651. .hw.init = &(struct clk_init_data){
  2652. .name = "sdc4_h_clk",
  2653. .ops = &clk_branch_ops,
  2654. },
  2655. },
  2656. };
  2657. static struct clk_branch sdc5_h_clk = {
  2658. .hwcg_reg = 0x28a0,
  2659. .hwcg_bit = 6,
  2660. .halt_reg = 0x2fc8,
  2661. .halt_bit = 7,
  2662. .clkr = {
  2663. .enable_reg = 0x28a0,
  2664. .enable_mask = BIT(4),
  2665. .hw.init = &(struct clk_init_data){
  2666. .name = "sdc5_h_clk",
  2667. .ops = &clk_branch_ops,
  2668. },
  2669. },
  2670. };
  2671. static struct clk_branch adm0_clk = {
  2672. .halt_reg = 0x2fdc,
  2673. .halt_check = BRANCH_HALT_VOTED,
  2674. .halt_bit = 14,
  2675. .clkr = {
  2676. .enable_reg = 0x3080,
  2677. .enable_mask = BIT(2),
  2678. .hw.init = &(struct clk_init_data){
  2679. .name = "adm0_clk",
  2680. .ops = &clk_branch_ops,
  2681. },
  2682. },
  2683. };
  2684. static struct clk_branch adm0_pbus_clk = {
  2685. .hwcg_reg = 0x2208,
  2686. .hwcg_bit = 6,
  2687. .halt_reg = 0x2fdc,
  2688. .halt_check = BRANCH_HALT_VOTED,
  2689. .halt_bit = 13,
  2690. .clkr = {
  2691. .enable_reg = 0x3080,
  2692. .enable_mask = BIT(3),
  2693. .hw.init = &(struct clk_init_data){
  2694. .name = "adm0_pbus_clk",
  2695. .ops = &clk_branch_ops,
  2696. },
  2697. },
  2698. };
  2699. static struct freq_tbl clk_tbl_ce3[] = {
  2700. { 48000000, P_PLL8, 8 },
  2701. { 100000000, P_PLL3, 12 },
  2702. { 120000000, P_PLL3, 10 },
  2703. { }
  2704. };
  2705. static struct clk_rcg ce3_src = {
  2706. .ns_reg = 0x36c0,
  2707. .p = {
  2708. .pre_div_shift = 3,
  2709. .pre_div_width = 4,
  2710. },
  2711. .s = {
  2712. .src_sel_shift = 0,
  2713. .parent_map = gcc_pxo_pll8_pll3_map,
  2714. },
  2715. .freq_tbl = clk_tbl_ce3,
  2716. .clkr = {
  2717. .enable_reg = 0x36c0,
  2718. .enable_mask = BIT(7),
  2719. .hw.init = &(struct clk_init_data){
  2720. .name = "ce3_src",
  2721. .parent_names = gcc_pxo_pll8_pll3,
  2722. .num_parents = 3,
  2723. .ops = &clk_rcg_ops,
  2724. .flags = CLK_SET_RATE_GATE,
  2725. },
  2726. },
  2727. };
  2728. static struct clk_branch ce3_core_clk = {
  2729. .halt_reg = 0x2fdc,
  2730. .halt_bit = 5,
  2731. .clkr = {
  2732. .enable_reg = 0x36cc,
  2733. .enable_mask = BIT(4),
  2734. .hw.init = &(struct clk_init_data){
  2735. .name = "ce3_core_clk",
  2736. .parent_names = (const char *[]){ "ce3_src" },
  2737. .num_parents = 1,
  2738. .ops = &clk_branch_ops,
  2739. .flags = CLK_SET_RATE_PARENT,
  2740. },
  2741. },
  2742. };
  2743. static struct clk_branch ce3_h_clk = {
  2744. .halt_reg = 0x2fc4,
  2745. .halt_bit = 16,
  2746. .clkr = {
  2747. .enable_reg = 0x36c4,
  2748. .enable_mask = BIT(4),
  2749. .hw.init = &(struct clk_init_data){
  2750. .name = "ce3_h_clk",
  2751. .parent_names = (const char *[]){ "ce3_src" },
  2752. .num_parents = 1,
  2753. .ops = &clk_branch_ops,
  2754. .flags = CLK_SET_RATE_PARENT,
  2755. },
  2756. },
  2757. };
  2758. static const struct freq_tbl clk_tbl_sata_ref[] = {
  2759. { 48000000, P_PLL8, 8, 0, 0 },
  2760. { 100000000, P_PLL3, 12, 0, 0 },
  2761. { }
  2762. };
  2763. static struct clk_rcg sata_clk_src = {
  2764. .ns_reg = 0x2c08,
  2765. .p = {
  2766. .pre_div_shift = 3,
  2767. .pre_div_width = 4,
  2768. },
  2769. .s = {
  2770. .src_sel_shift = 0,
  2771. .parent_map = gcc_pxo_pll8_pll3_map,
  2772. },
  2773. .freq_tbl = clk_tbl_sata_ref,
  2774. .clkr = {
  2775. .enable_reg = 0x2c08,
  2776. .enable_mask = BIT(7),
  2777. .hw.init = &(struct clk_init_data){
  2778. .name = "sata_clk_src",
  2779. .parent_names = gcc_pxo_pll8_pll3,
  2780. .num_parents = 3,
  2781. .ops = &clk_rcg_ops,
  2782. .flags = CLK_SET_RATE_GATE,
  2783. },
  2784. },
  2785. };
  2786. static struct clk_branch sata_rxoob_clk = {
  2787. .halt_reg = 0x2fdc,
  2788. .halt_bit = 26,
  2789. .clkr = {
  2790. .enable_reg = 0x2c0c,
  2791. .enable_mask = BIT(4),
  2792. .hw.init = &(struct clk_init_data){
  2793. .name = "sata_rxoob_clk",
  2794. .parent_names = (const char *[]){ "sata_clk_src" },
  2795. .num_parents = 1,
  2796. .ops = &clk_branch_ops,
  2797. .flags = CLK_SET_RATE_PARENT,
  2798. },
  2799. },
  2800. };
  2801. static struct clk_branch sata_pmalive_clk = {
  2802. .halt_reg = 0x2fdc,
  2803. .halt_bit = 25,
  2804. .clkr = {
  2805. .enable_reg = 0x2c10,
  2806. .enable_mask = BIT(4),
  2807. .hw.init = &(struct clk_init_data){
  2808. .name = "sata_pmalive_clk",
  2809. .parent_names = (const char *[]){ "sata_clk_src" },
  2810. .num_parents = 1,
  2811. .ops = &clk_branch_ops,
  2812. .flags = CLK_SET_RATE_PARENT,
  2813. },
  2814. },
  2815. };
  2816. static struct clk_branch sata_phy_ref_clk = {
  2817. .halt_reg = 0x2fdc,
  2818. .halt_bit = 24,
  2819. .clkr = {
  2820. .enable_reg = 0x2c14,
  2821. .enable_mask = BIT(4),
  2822. .hw.init = &(struct clk_init_data){
  2823. .name = "sata_phy_ref_clk",
  2824. .parent_names = (const char *[]){ "pxo" },
  2825. .num_parents = 1,
  2826. .ops = &clk_branch_ops,
  2827. },
  2828. },
  2829. };
  2830. static struct clk_branch sata_a_clk = {
  2831. .halt_reg = 0x2fc0,
  2832. .halt_bit = 12,
  2833. .clkr = {
  2834. .enable_reg = 0x2c20,
  2835. .enable_mask = BIT(4),
  2836. .hw.init = &(struct clk_init_data){
  2837. .name = "sata_a_clk",
  2838. .ops = &clk_branch_ops,
  2839. },
  2840. },
  2841. };
  2842. static struct clk_branch sata_h_clk = {
  2843. .halt_reg = 0x2fdc,
  2844. .halt_bit = 27,
  2845. .clkr = {
  2846. .enable_reg = 0x2c00,
  2847. .enable_mask = BIT(4),
  2848. .hw.init = &(struct clk_init_data){
  2849. .name = "sata_h_clk",
  2850. .ops = &clk_branch_ops,
  2851. },
  2852. },
  2853. };
  2854. static struct clk_branch sfab_sata_s_h_clk = {
  2855. .halt_reg = 0x2fc4,
  2856. .halt_bit = 14,
  2857. .clkr = {
  2858. .enable_reg = 0x2480,
  2859. .enable_mask = BIT(4),
  2860. .hw.init = &(struct clk_init_data){
  2861. .name = "sfab_sata_s_h_clk",
  2862. .ops = &clk_branch_ops,
  2863. },
  2864. },
  2865. };
  2866. static struct clk_branch sata_phy_cfg_clk = {
  2867. .halt_reg = 0x2fcc,
  2868. .halt_bit = 12,
  2869. .clkr = {
  2870. .enable_reg = 0x2c40,
  2871. .enable_mask = BIT(4),
  2872. .hw.init = &(struct clk_init_data){
  2873. .name = "sata_phy_cfg_clk",
  2874. .ops = &clk_branch_ops,
  2875. },
  2876. },
  2877. };
  2878. static struct clk_branch pcie_phy_ref_clk = {
  2879. .halt_reg = 0x2fdc,
  2880. .halt_bit = 29,
  2881. .clkr = {
  2882. .enable_reg = 0x22d0,
  2883. .enable_mask = BIT(4),
  2884. .hw.init = &(struct clk_init_data){
  2885. .name = "pcie_phy_ref_clk",
  2886. .ops = &clk_branch_ops,
  2887. },
  2888. },
  2889. };
  2890. static struct clk_branch pcie_h_clk = {
  2891. .halt_reg = 0x2fd4,
  2892. .halt_bit = 8,
  2893. .clkr = {
  2894. .enable_reg = 0x22cc,
  2895. .enable_mask = BIT(4),
  2896. .hw.init = &(struct clk_init_data){
  2897. .name = "pcie_h_clk",
  2898. .ops = &clk_branch_ops,
  2899. },
  2900. },
  2901. };
  2902. static struct clk_branch pcie_a_clk = {
  2903. .halt_reg = 0x2fc0,
  2904. .halt_bit = 13,
  2905. .clkr = {
  2906. .enable_reg = 0x22c0,
  2907. .enable_mask = BIT(4),
  2908. .hw.init = &(struct clk_init_data){
  2909. .name = "pcie_a_clk",
  2910. .ops = &clk_branch_ops,
  2911. },
  2912. },
  2913. };
  2914. static struct clk_branch pmic_arb0_h_clk = {
  2915. .halt_reg = 0x2fd8,
  2916. .halt_check = BRANCH_HALT_VOTED,
  2917. .halt_bit = 22,
  2918. .clkr = {
  2919. .enable_reg = 0x3080,
  2920. .enable_mask = BIT(8),
  2921. .hw.init = &(struct clk_init_data){
  2922. .name = "pmic_arb0_h_clk",
  2923. .ops = &clk_branch_ops,
  2924. },
  2925. },
  2926. };
  2927. static struct clk_branch pmic_arb1_h_clk = {
  2928. .halt_reg = 0x2fd8,
  2929. .halt_check = BRANCH_HALT_VOTED,
  2930. .halt_bit = 21,
  2931. .clkr = {
  2932. .enable_reg = 0x3080,
  2933. .enable_mask = BIT(9),
  2934. .hw.init = &(struct clk_init_data){
  2935. .name = "pmic_arb1_h_clk",
  2936. .ops = &clk_branch_ops,
  2937. },
  2938. },
  2939. };
  2940. static struct clk_branch pmic_ssbi2_clk = {
  2941. .halt_reg = 0x2fd8,
  2942. .halt_check = BRANCH_HALT_VOTED,
  2943. .halt_bit = 23,
  2944. .clkr = {
  2945. .enable_reg = 0x3080,
  2946. .enable_mask = BIT(7),
  2947. .hw.init = &(struct clk_init_data){
  2948. .name = "pmic_ssbi2_clk",
  2949. .ops = &clk_branch_ops,
  2950. },
  2951. },
  2952. };
  2953. static struct clk_branch rpm_msg_ram_h_clk = {
  2954. .hwcg_reg = 0x27e0,
  2955. .hwcg_bit = 6,
  2956. .halt_reg = 0x2fd8,
  2957. .halt_check = BRANCH_HALT_VOTED,
  2958. .halt_bit = 12,
  2959. .clkr = {
  2960. .enable_reg = 0x3080,
  2961. .enable_mask = BIT(6),
  2962. .hw.init = &(struct clk_init_data){
  2963. .name = "rpm_msg_ram_h_clk",
  2964. .ops = &clk_branch_ops,
  2965. },
  2966. },
  2967. };
  2968. static struct clk_regmap *gcc_msm8960_clks[] = {
  2969. [PLL3] = &pll3.clkr,
  2970. [PLL4_VOTE] = &pll4_vote,
  2971. [PLL8] = &pll8.clkr,
  2972. [PLL8_VOTE] = &pll8_vote,
  2973. [PLL14] = &pll14.clkr,
  2974. [PLL14_VOTE] = &pll14_vote,
  2975. [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
  2976. [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
  2977. [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
  2978. [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
  2979. [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
  2980. [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
  2981. [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
  2982. [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
  2983. [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
  2984. [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
  2985. [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
  2986. [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
  2987. [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
  2988. [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
  2989. [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
  2990. [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
  2991. [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
  2992. [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
  2993. [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
  2994. [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
  2995. [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
  2996. [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
  2997. [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
  2998. [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
  2999. [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
  3000. [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
  3001. [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
  3002. [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
  3003. [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
  3004. [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
  3005. [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
  3006. [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
  3007. [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
  3008. [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
  3009. [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
  3010. [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
  3011. [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
  3012. [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
  3013. [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
  3014. [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
  3015. [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
  3016. [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
  3017. [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
  3018. [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
  3019. [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
  3020. [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
  3021. [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
  3022. [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
  3023. [GP0_SRC] = &gp0_src.clkr,
  3024. [GP0_CLK] = &gp0_clk.clkr,
  3025. [GP1_SRC] = &gp1_src.clkr,
  3026. [GP1_CLK] = &gp1_clk.clkr,
  3027. [GP2_SRC] = &gp2_src.clkr,
  3028. [GP2_CLK] = &gp2_clk.clkr,
  3029. [PMEM_A_CLK] = &pmem_clk.clkr,
  3030. [PRNG_SRC] = &prng_src.clkr,
  3031. [PRNG_CLK] = &prng_clk.clkr,
  3032. [SDC1_SRC] = &sdc1_src.clkr,
  3033. [SDC1_CLK] = &sdc1_clk.clkr,
  3034. [SDC2_SRC] = &sdc2_src.clkr,
  3035. [SDC2_CLK] = &sdc2_clk.clkr,
  3036. [SDC3_SRC] = &sdc3_src.clkr,
  3037. [SDC3_CLK] = &sdc3_clk.clkr,
  3038. [SDC4_SRC] = &sdc4_src.clkr,
  3039. [SDC4_CLK] = &sdc4_clk.clkr,
  3040. [SDC5_SRC] = &sdc5_src.clkr,
  3041. [SDC5_CLK] = &sdc5_clk.clkr,
  3042. [TSIF_REF_SRC] = &tsif_ref_src.clkr,
  3043. [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
  3044. [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
  3045. [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
  3046. [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
  3047. [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
  3048. [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
  3049. [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
  3050. [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
  3051. [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
  3052. [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
  3053. [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
  3054. [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
  3055. [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
  3056. [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
  3057. [CE1_CORE_CLK] = &ce1_core_clk.clkr,
  3058. [CE1_H_CLK] = &ce1_h_clk.clkr,
  3059. [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
  3060. [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
  3061. [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
  3062. [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
  3063. [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
  3064. [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
  3065. [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
  3066. [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
  3067. [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
  3068. [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
  3069. [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
  3070. [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
  3071. [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
  3072. [TSIF_H_CLK] = &tsif_h_clk.clkr,
  3073. [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
  3074. [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
  3075. [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
  3076. [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
  3077. [SDC1_H_CLK] = &sdc1_h_clk.clkr,
  3078. [SDC2_H_CLK] = &sdc2_h_clk.clkr,
  3079. [SDC3_H_CLK] = &sdc3_h_clk.clkr,
  3080. [SDC4_H_CLK] = &sdc4_h_clk.clkr,
  3081. [SDC5_H_CLK] = &sdc5_h_clk.clkr,
  3082. [ADM0_CLK] = &adm0_clk.clkr,
  3083. [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
  3084. [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
  3085. [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
  3086. [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
  3087. [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
  3088. [PLL9] = &hfpll0.clkr,
  3089. [PLL10] = &hfpll1.clkr,
  3090. [PLL12] = &hfpll_l2.clkr,
  3091. };
  3092. static const struct qcom_reset_map gcc_msm8960_resets[] = {
  3093. [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
  3094. [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
  3095. [QDSS_STM_RESET] = { 0x2060, 6 },
  3096. [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
  3097. [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
  3098. [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
  3099. [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
  3100. [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
  3101. [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
  3102. [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
  3103. [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
  3104. [ADM0_C2_RESET] = { 0x220c, 4},
  3105. [ADM0_C1_RESET] = { 0x220c, 3},
  3106. [ADM0_C0_RESET] = { 0x220c, 2},
  3107. [ADM0_PBUS_RESET] = { 0x220c, 1 },
  3108. [ADM0_RESET] = { 0x220c },
  3109. [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
  3110. [QDSS_POR_RESET] = { 0x2260, 4 },
  3111. [QDSS_TSCTR_RESET] = { 0x2260, 3 },
  3112. [QDSS_HRESET_RESET] = { 0x2260, 2 },
  3113. [QDSS_AXI_RESET] = { 0x2260, 1 },
  3114. [QDSS_DBG_RESET] = { 0x2260 },
  3115. [PCIE_A_RESET] = { 0x22c0, 7 },
  3116. [PCIE_AUX_RESET] = { 0x22c8, 7 },
  3117. [PCIE_H_RESET] = { 0x22d0, 7 },
  3118. [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
  3119. [SFAB_PCIE_S_RESET] = { 0x22d4 },
  3120. [SFAB_MSS_M_RESET] = { 0x2340, 7 },
  3121. [SFAB_USB3_M_RESET] = { 0x2360, 7 },
  3122. [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
  3123. [SFAB_LPASS_RESET] = { 0x23a0, 7 },
  3124. [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
  3125. [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
  3126. [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
  3127. [SFAB_SATA_S_RESET] = { 0x2480, 7 },
  3128. [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
  3129. [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
  3130. [DFAB_SWAY0_RESET] = { 0x2540, 7 },
  3131. [DFAB_SWAY1_RESET] = { 0x2544, 7 },
  3132. [DFAB_ARB0_RESET] = { 0x2560, 7 },
  3133. [DFAB_ARB1_RESET] = { 0x2564, 7 },
  3134. [PPSS_PROC_RESET] = { 0x2594, 1 },
  3135. [PPSS_RESET] = { 0x2594},
  3136. [DMA_BAM_RESET] = { 0x25c0, 7 },
  3137. [SPS_TIC_H_RESET] = { 0x2600, 7 },
  3138. [SLIMBUS_H_RESET] = { 0x2620, 7 },
  3139. [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
  3140. [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
  3141. [TSIF_H_RESET] = { 0x2700, 7 },
  3142. [CE1_H_RESET] = { 0x2720, 7 },
  3143. [CE1_CORE_RESET] = { 0x2724, 7 },
  3144. [CE1_SLEEP_RESET] = { 0x2728, 7 },
  3145. [CE2_H_RESET] = { 0x2740, 7 },
  3146. [CE2_CORE_RESET] = { 0x2744, 7 },
  3147. [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
  3148. [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
  3149. [RPM_PROC_RESET] = { 0x27c0, 7 },
  3150. [PMIC_SSBI2_RESET] = { 0x280c, 12 },
  3151. [SDC1_RESET] = { 0x2830 },
  3152. [SDC2_RESET] = { 0x2850 },
  3153. [SDC3_RESET] = { 0x2870 },
  3154. [SDC4_RESET] = { 0x2890 },
  3155. [SDC5_RESET] = { 0x28b0 },
  3156. [DFAB_A2_RESET] = { 0x28c0, 7 },
  3157. [USB_HS1_RESET] = { 0x2910 },
  3158. [USB_HSIC_RESET] = { 0x2934 },
  3159. [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
  3160. [USB_FS1_RESET] = { 0x2974 },
  3161. [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
  3162. [USB_FS2_RESET] = { 0x2994 },
  3163. [GSBI1_RESET] = { 0x29dc },
  3164. [GSBI2_RESET] = { 0x29fc },
  3165. [GSBI3_RESET] = { 0x2a1c },
  3166. [GSBI4_RESET] = { 0x2a3c },
  3167. [GSBI5_RESET] = { 0x2a5c },
  3168. [GSBI6_RESET] = { 0x2a7c },
  3169. [GSBI7_RESET] = { 0x2a9c },
  3170. [GSBI8_RESET] = { 0x2abc },
  3171. [GSBI9_RESET] = { 0x2adc },
  3172. [GSBI10_RESET] = { 0x2afc },
  3173. [GSBI11_RESET] = { 0x2b1c },
  3174. [GSBI12_RESET] = { 0x2b3c },
  3175. [SPDM_RESET] = { 0x2b6c },
  3176. [TLMM_H_RESET] = { 0x2ba0, 7 },
  3177. [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
  3178. [MSS_SLP_RESET] = { 0x2c60, 7 },
  3179. [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
  3180. [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
  3181. [MSS_RESET] = { 0x2c64 },
  3182. [SATA_H_RESET] = { 0x2c80, 7 },
  3183. [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
  3184. [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
  3185. [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
  3186. [TSSC_RESET] = { 0x2ca0, 7 },
  3187. [PDM_RESET] = { 0x2cc0, 12 },
  3188. [MPM_H_RESET] = { 0x2da0, 7 },
  3189. [MPM_RESET] = { 0x2da4 },
  3190. [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
  3191. [PRNG_RESET] = { 0x2e80, 12 },
  3192. [RIVA_RESET] = { 0x35e0 },
  3193. };
  3194. static struct clk_regmap *gcc_apq8064_clks[] = {
  3195. [PLL3] = &pll3.clkr,
  3196. [PLL4_VOTE] = &pll4_vote,
  3197. [PLL8] = &pll8.clkr,
  3198. [PLL8_VOTE] = &pll8_vote,
  3199. [PLL14] = &pll14.clkr,
  3200. [PLL14_VOTE] = &pll14_vote,
  3201. [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
  3202. [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
  3203. [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
  3204. [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
  3205. [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
  3206. [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
  3207. [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
  3208. [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
  3209. [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
  3210. [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
  3211. [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
  3212. [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
  3213. [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
  3214. [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
  3215. [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
  3216. [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
  3217. [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
  3218. [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
  3219. [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
  3220. [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
  3221. [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
  3222. [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
  3223. [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
  3224. [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
  3225. [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
  3226. [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
  3227. [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
  3228. [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
  3229. [GP0_SRC] = &gp0_src.clkr,
  3230. [GP0_CLK] = &gp0_clk.clkr,
  3231. [GP1_SRC] = &gp1_src.clkr,
  3232. [GP1_CLK] = &gp1_clk.clkr,
  3233. [GP2_SRC] = &gp2_src.clkr,
  3234. [GP2_CLK] = &gp2_clk.clkr,
  3235. [PMEM_A_CLK] = &pmem_clk.clkr,
  3236. [PRNG_SRC] = &prng_src.clkr,
  3237. [PRNG_CLK] = &prng_clk.clkr,
  3238. [SDC1_SRC] = &sdc1_src.clkr,
  3239. [SDC1_CLK] = &sdc1_clk.clkr,
  3240. [SDC2_SRC] = &sdc2_src.clkr,
  3241. [SDC2_CLK] = &sdc2_clk.clkr,
  3242. [SDC3_SRC] = &sdc3_src.clkr,
  3243. [SDC3_CLK] = &sdc3_clk.clkr,
  3244. [SDC4_SRC] = &sdc4_src.clkr,
  3245. [SDC4_CLK] = &sdc4_clk.clkr,
  3246. [TSIF_REF_SRC] = &tsif_ref_src.clkr,
  3247. [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
  3248. [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
  3249. [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
  3250. [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
  3251. [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
  3252. [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
  3253. [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
  3254. [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
  3255. [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
  3256. [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
  3257. [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
  3258. [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
  3259. [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
  3260. [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
  3261. [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
  3262. [SATA_H_CLK] = &sata_h_clk.clkr,
  3263. [SATA_CLK_SRC] = &sata_clk_src.clkr,
  3264. [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
  3265. [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
  3266. [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
  3267. [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
  3268. [SATA_A_CLK] = &sata_a_clk.clkr,
  3269. [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
  3270. [CE3_SRC] = &ce3_src.clkr,
  3271. [CE3_CORE_CLK] = &ce3_core_clk.clkr,
  3272. [CE3_H_CLK] = &ce3_h_clk.clkr,
  3273. [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
  3274. [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
  3275. [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
  3276. [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
  3277. [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
  3278. [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
  3279. [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
  3280. [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
  3281. [TSIF_H_CLK] = &tsif_h_clk.clkr,
  3282. [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
  3283. [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
  3284. [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
  3285. [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
  3286. [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
  3287. [SDC1_H_CLK] = &sdc1_h_clk.clkr,
  3288. [SDC2_H_CLK] = &sdc2_h_clk.clkr,
  3289. [SDC3_H_CLK] = &sdc3_h_clk.clkr,
  3290. [SDC4_H_CLK] = &sdc4_h_clk.clkr,
  3291. [ADM0_CLK] = &adm0_clk.clkr,
  3292. [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
  3293. [PCIE_A_CLK] = &pcie_a_clk.clkr,
  3294. [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
  3295. [PCIE_H_CLK] = &pcie_h_clk.clkr,
  3296. [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
  3297. [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
  3298. [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
  3299. [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
  3300. [PLL9] = &hfpll0.clkr,
  3301. [PLL10] = &hfpll1.clkr,
  3302. [PLL12] = &hfpll_l2.clkr,
  3303. [PLL16] = &hfpll2.clkr,
  3304. [PLL17] = &hfpll3.clkr,
  3305. };
  3306. static const struct qcom_reset_map gcc_apq8064_resets[] = {
  3307. [QDSS_STM_RESET] = { 0x2060, 6 },
  3308. [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
  3309. [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
  3310. [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
  3311. [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
  3312. [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
  3313. [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
  3314. [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
  3315. [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
  3316. [ADM0_C2_RESET] = { 0x220c, 4},
  3317. [ADM0_C1_RESET] = { 0x220c, 3},
  3318. [ADM0_C0_RESET] = { 0x220c, 2},
  3319. [ADM0_PBUS_RESET] = { 0x220c, 1 },
  3320. [ADM0_RESET] = { 0x220c },
  3321. [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
  3322. [QDSS_POR_RESET] = { 0x2260, 4 },
  3323. [QDSS_TSCTR_RESET] = { 0x2260, 3 },
  3324. [QDSS_HRESET_RESET] = { 0x2260, 2 },
  3325. [QDSS_AXI_RESET] = { 0x2260, 1 },
  3326. [QDSS_DBG_RESET] = { 0x2260 },
  3327. [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
  3328. [SFAB_PCIE_S_RESET] = { 0x22d8 },
  3329. [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
  3330. [PCIE_PHY_RESET] = { 0x22dc, 5 },
  3331. [PCIE_PCI_RESET] = { 0x22dc, 4 },
  3332. [PCIE_POR_RESET] = { 0x22dc, 3 },
  3333. [PCIE_HCLK_RESET] = { 0x22dc, 2 },
  3334. [PCIE_ACLK_RESET] = { 0x22dc },
  3335. [SFAB_USB3_M_RESET] = { 0x2360, 7 },
  3336. [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
  3337. [SFAB_LPASS_RESET] = { 0x23a0, 7 },
  3338. [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
  3339. [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
  3340. [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
  3341. [SFAB_SATA_S_RESET] = { 0x2480, 7 },
  3342. [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
  3343. [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
  3344. [DFAB_SWAY0_RESET] = { 0x2540, 7 },
  3345. [DFAB_SWAY1_RESET] = { 0x2544, 7 },
  3346. [DFAB_ARB0_RESET] = { 0x2560, 7 },
  3347. [DFAB_ARB1_RESET] = { 0x2564, 7 },
  3348. [PPSS_PROC_RESET] = { 0x2594, 1 },
  3349. [PPSS_RESET] = { 0x2594},
  3350. [DMA_BAM_RESET] = { 0x25c0, 7 },
  3351. [SPS_TIC_H_RESET] = { 0x2600, 7 },
  3352. [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
  3353. [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
  3354. [TSIF_H_RESET] = { 0x2700, 7 },
  3355. [CE1_H_RESET] = { 0x2720, 7 },
  3356. [CE1_CORE_RESET] = { 0x2724, 7 },
  3357. [CE1_SLEEP_RESET] = { 0x2728, 7 },
  3358. [CE2_H_RESET] = { 0x2740, 7 },
  3359. [CE2_CORE_RESET] = { 0x2744, 7 },
  3360. [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
  3361. [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
  3362. [RPM_PROC_RESET] = { 0x27c0, 7 },
  3363. [PMIC_SSBI2_RESET] = { 0x280c, 12 },
  3364. [SDC1_RESET] = { 0x2830 },
  3365. [SDC2_RESET] = { 0x2850 },
  3366. [SDC3_RESET] = { 0x2870 },
  3367. [SDC4_RESET] = { 0x2890 },
  3368. [USB_HS1_RESET] = { 0x2910 },
  3369. [USB_HSIC_RESET] = { 0x2934 },
  3370. [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
  3371. [USB_FS1_RESET] = { 0x2974 },
  3372. [GSBI1_RESET] = { 0x29dc },
  3373. [GSBI2_RESET] = { 0x29fc },
  3374. [GSBI3_RESET] = { 0x2a1c },
  3375. [GSBI4_RESET] = { 0x2a3c },
  3376. [GSBI5_RESET] = { 0x2a5c },
  3377. [GSBI6_RESET] = { 0x2a7c },
  3378. [GSBI7_RESET] = { 0x2a9c },
  3379. [SPDM_RESET] = { 0x2b6c },
  3380. [TLMM_H_RESET] = { 0x2ba0, 7 },
  3381. [SATA_SFAB_M_RESET] = { 0x2c18 },
  3382. [SATA_RESET] = { 0x2c1c },
  3383. [GSS_SLP_RESET] = { 0x2c60, 7 },
  3384. [GSS_RESET] = { 0x2c64 },
  3385. [TSSC_RESET] = { 0x2ca0, 7 },
  3386. [PDM_RESET] = { 0x2cc0, 12 },
  3387. [MPM_H_RESET] = { 0x2da0, 7 },
  3388. [MPM_RESET] = { 0x2da4 },
  3389. [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
  3390. [PRNG_RESET] = { 0x2e80, 12 },
  3391. [RIVA_RESET] = { 0x35e0 },
  3392. [CE3_H_RESET] = { 0x36c4, 7 },
  3393. [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
  3394. [SFAB_CE3_S_RESET] = { 0x36c8 },
  3395. [CE3_RESET] = { 0x36cc, 7 },
  3396. [CE3_SLEEP_RESET] = { 0x36d0, 7 },
  3397. [USB_HS3_RESET] = { 0x3710 },
  3398. [USB_HS4_RESET] = { 0x3730 },
  3399. };
  3400. static const struct regmap_config gcc_msm8960_regmap_config = {
  3401. .reg_bits = 32,
  3402. .reg_stride = 4,
  3403. .val_bits = 32,
  3404. .max_register = 0x3660,
  3405. .fast_io = true,
  3406. };
  3407. static const struct regmap_config gcc_apq8064_regmap_config = {
  3408. .reg_bits = 32,
  3409. .reg_stride = 4,
  3410. .val_bits = 32,
  3411. .max_register = 0x3880,
  3412. .fast_io = true,
  3413. };
  3414. static const struct qcom_cc_desc gcc_msm8960_desc = {
  3415. .config = &gcc_msm8960_regmap_config,
  3416. .clks = gcc_msm8960_clks,
  3417. .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
  3418. .resets = gcc_msm8960_resets,
  3419. .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
  3420. };
  3421. static const struct qcom_cc_desc gcc_apq8064_desc = {
  3422. .config = &gcc_apq8064_regmap_config,
  3423. .clks = gcc_apq8064_clks,
  3424. .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
  3425. .resets = gcc_apq8064_resets,
  3426. .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
  3427. };
  3428. static const struct of_device_id gcc_msm8960_match_table[] = {
  3429. { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
  3430. { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
  3431. { }
  3432. };
  3433. MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
  3434. static int gcc_msm8960_probe(struct platform_device *pdev)
  3435. {
  3436. struct device *dev = &pdev->dev;
  3437. const struct of_device_id *match;
  3438. struct platform_device *tsens;
  3439. int ret;
  3440. match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
  3441. if (!match)
  3442. return -EINVAL;
  3443. ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
  3444. if (ret)
  3445. return ret;
  3446. ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
  3447. if (ret)
  3448. return ret;
  3449. ret = qcom_cc_probe(pdev, match->data);
  3450. if (ret)
  3451. return ret;
  3452. if (match->data == &gcc_apq8064_desc) {
  3453. hfpll1.d = &hfpll1_8064_data;
  3454. hfpll_l2.d = &hfpll_l2_8064_data;
  3455. }
  3456. tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
  3457. NULL, 0);
  3458. if (IS_ERR(tsens))
  3459. return PTR_ERR(tsens);
  3460. platform_set_drvdata(pdev, tsens);
  3461. return 0;
  3462. }
  3463. static int gcc_msm8960_remove(struct platform_device *pdev)
  3464. {
  3465. struct platform_device *tsens = platform_get_drvdata(pdev);
  3466. platform_device_unregister(tsens);
  3467. return 0;
  3468. }
  3469. static struct platform_driver gcc_msm8960_driver = {
  3470. .probe = gcc_msm8960_probe,
  3471. .remove = gcc_msm8960_remove,
  3472. .driver = {
  3473. .name = "gcc-msm8960",
  3474. .of_match_table = gcc_msm8960_match_table,
  3475. },
  3476. };
  3477. static int __init gcc_msm8960_init(void)
  3478. {
  3479. return platform_driver_register(&gcc_msm8960_driver);
  3480. }
  3481. core_initcall(gcc_msm8960_init);
  3482. static void __exit gcc_msm8960_exit(void)
  3483. {
  3484. platform_driver_unregister(&gcc_msm8960_driver);
  3485. }
  3486. module_exit(gcc_msm8960_exit);
  3487. MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
  3488. MODULE_LICENSE("GPL v2");
  3489. MODULE_ALIAS("platform:gcc-msm8960");