clk.h 6.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __MACH_MMP_CLK_H
  3. #define __MACH_MMP_CLK_H
  4. #include <linux/clk-provider.h>
  5. #include <linux/pm_domain.h>
  6. #include <linux/clkdev.h>
  7. #define APBC_NO_BUS_CTRL BIT(0)
  8. #define APBC_POWER_CTRL BIT(1)
  9. /* Clock type "factor" */
  10. struct mmp_clk_factor_masks {
  11. unsigned int factor;
  12. unsigned int num_mask;
  13. unsigned int den_mask;
  14. unsigned int num_shift;
  15. unsigned int den_shift;
  16. unsigned int enable_mask;
  17. };
  18. struct mmp_clk_factor_tbl {
  19. unsigned int num;
  20. unsigned int den;
  21. };
  22. struct mmp_clk_factor {
  23. struct clk_hw hw;
  24. void __iomem *base;
  25. struct mmp_clk_factor_masks *masks;
  26. struct mmp_clk_factor_tbl *ftbl;
  27. unsigned int ftbl_cnt;
  28. spinlock_t *lock;
  29. };
  30. extern struct clk *mmp_clk_register_factor(const char *name,
  31. const char *parent_name, unsigned long flags,
  32. void __iomem *base, struct mmp_clk_factor_masks *masks,
  33. struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
  34. spinlock_t *lock);
  35. /* Clock type "mix" */
  36. #define MMP_CLK_BITS_MASK(width, shift) \
  37. (((1 << (width)) - 1) << (shift))
  38. #define MMP_CLK_BITS_GET_VAL(data, width, shift) \
  39. ((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
  40. #define MMP_CLK_BITS_SET_VAL(val, width, shift) \
  41. (((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift))
  42. enum {
  43. MMP_CLK_MIX_TYPE_V1,
  44. MMP_CLK_MIX_TYPE_V2,
  45. MMP_CLK_MIX_TYPE_V3,
  46. };
  47. /* The register layout */
  48. struct mmp_clk_mix_reg_info {
  49. void __iomem *reg_clk_ctrl;
  50. void __iomem *reg_clk_sel;
  51. u8 width_div;
  52. u8 shift_div;
  53. u8 width_mux;
  54. u8 shift_mux;
  55. u8 bit_fc;
  56. };
  57. /* The suggested clock table from user. */
  58. struct mmp_clk_mix_clk_table {
  59. unsigned long rate;
  60. u8 parent_index;
  61. unsigned int divisor;
  62. unsigned int valid;
  63. };
  64. struct mmp_clk_mix_config {
  65. struct mmp_clk_mix_reg_info reg_info;
  66. struct mmp_clk_mix_clk_table *table;
  67. unsigned int table_size;
  68. u32 *mux_table;
  69. struct clk_div_table *div_table;
  70. u8 div_flags;
  71. u8 mux_flags;
  72. };
  73. struct mmp_clk_mix {
  74. struct clk_hw hw;
  75. struct mmp_clk_mix_reg_info reg_info;
  76. struct mmp_clk_mix_clk_table *table;
  77. u32 *mux_table;
  78. struct clk_div_table *div_table;
  79. unsigned int table_size;
  80. u8 div_flags;
  81. u8 mux_flags;
  82. unsigned int type;
  83. spinlock_t *lock;
  84. };
  85. extern const struct clk_ops mmp_clk_mix_ops;
  86. extern struct clk *mmp_clk_register_mix(struct device *dev,
  87. const char *name,
  88. const char * const *parent_names,
  89. u8 num_parents,
  90. unsigned long flags,
  91. struct mmp_clk_mix_config *config,
  92. spinlock_t *lock);
  93. /* Clock type "gate". MMP private gate */
  94. #define MMP_CLK_GATE_NEED_DELAY BIT(0)
  95. struct mmp_clk_gate {
  96. struct clk_hw hw;
  97. void __iomem *reg;
  98. u32 mask;
  99. u32 val_enable;
  100. u32 val_disable;
  101. unsigned int flags;
  102. spinlock_t *lock;
  103. };
  104. extern const struct clk_ops mmp_clk_gate_ops;
  105. extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
  106. const char *parent_name, unsigned long flags,
  107. void __iomem *reg, u32 mask, u32 val_enable,
  108. u32 val_disable, unsigned int gate_flags,
  109. spinlock_t *lock);
  110. extern struct clk *mmp_clk_register_apbc(const char *name,
  111. const char *parent_name, void __iomem *base,
  112. unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
  113. extern struct clk *mmp_clk_register_apmu(const char *name,
  114. const char *parent_name, void __iomem *base, u32 enable_mask,
  115. spinlock_t *lock);
  116. struct mmp_clk_unit {
  117. unsigned int nr_clks;
  118. struct clk **clk_table;
  119. struct clk_onecell_data clk_data;
  120. };
  121. struct mmp_param_fixed_rate_clk {
  122. unsigned int id;
  123. char *name;
  124. const char *parent_name;
  125. unsigned long flags;
  126. unsigned long fixed_rate;
  127. };
  128. void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
  129. struct mmp_param_fixed_rate_clk *clks,
  130. int size);
  131. struct mmp_param_fixed_factor_clk {
  132. unsigned int id;
  133. char *name;
  134. const char *parent_name;
  135. unsigned long mult;
  136. unsigned long div;
  137. unsigned long flags;
  138. };
  139. void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
  140. struct mmp_param_fixed_factor_clk *clks,
  141. int size);
  142. struct mmp_param_general_gate_clk {
  143. unsigned int id;
  144. const char *name;
  145. const char *parent_name;
  146. unsigned long flags;
  147. unsigned long offset;
  148. u8 bit_idx;
  149. u8 gate_flags;
  150. spinlock_t *lock;
  151. };
  152. void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
  153. struct mmp_param_general_gate_clk *clks,
  154. void __iomem *base, int size);
  155. struct mmp_param_gate_clk {
  156. unsigned int id;
  157. char *name;
  158. const char *parent_name;
  159. unsigned long flags;
  160. unsigned long offset;
  161. u32 mask;
  162. u32 val_enable;
  163. u32 val_disable;
  164. unsigned int gate_flags;
  165. spinlock_t *lock;
  166. };
  167. void mmp_register_gate_clks(struct mmp_clk_unit *unit,
  168. struct mmp_param_gate_clk *clks,
  169. void __iomem *base, int size);
  170. struct mmp_param_mux_clk {
  171. unsigned int id;
  172. char *name;
  173. const char * const *parent_name;
  174. u8 num_parents;
  175. unsigned long flags;
  176. unsigned long offset;
  177. u8 shift;
  178. u8 width;
  179. u8 mux_flags;
  180. spinlock_t *lock;
  181. };
  182. void mmp_register_mux_clks(struct mmp_clk_unit *unit,
  183. struct mmp_param_mux_clk *clks,
  184. void __iomem *base, int size);
  185. struct mmp_param_div_clk {
  186. unsigned int id;
  187. char *name;
  188. const char *parent_name;
  189. unsigned long flags;
  190. unsigned long offset;
  191. u8 shift;
  192. u8 width;
  193. u8 div_flags;
  194. spinlock_t *lock;
  195. };
  196. void mmp_register_div_clks(struct mmp_clk_unit *unit,
  197. struct mmp_param_div_clk *clks,
  198. void __iomem *base, int size);
  199. struct mmp_param_pll_clk {
  200. unsigned int id;
  201. char *name;
  202. unsigned long default_rate;
  203. unsigned long enable_offset;
  204. u32 enable;
  205. unsigned long offset;
  206. u8 shift;
  207. /* MMP3 specific: */
  208. unsigned long input_rate;
  209. unsigned long postdiv_offset;
  210. unsigned long postdiv_shift;
  211. };
  212. void mmp_register_pll_clks(struct mmp_clk_unit *unit,
  213. struct mmp_param_pll_clk *clks,
  214. void __iomem *base, int size);
  215. #define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \
  216. { \
  217. .width_div = (w_d), \
  218. .shift_div = (s_d), \
  219. .width_mux = (w_m), \
  220. .shift_mux = (s_m), \
  221. .bit_fc = (fc), \
  222. }
  223. void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
  224. int nr_clks);
  225. void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
  226. struct clk *clk);
  227. /* Power islands */
  228. #define MMP_PM_DOMAIN_NO_DISABLE BIT(0)
  229. struct generic_pm_domain *mmp_pm_domain_register(const char *name,
  230. void __iomem *reg,
  231. u32 power_on, u32 reset, u32 clock_enable,
  232. unsigned int flags, spinlock_t *lock);
  233. #endif