clk-pxa910.c 11 KB

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  1. /*
  2. * pxa910 clock framework source file
  3. *
  4. * Copyright (C) 2012 Marvell
  5. * Chao Xie <xiechao.mail@gmail.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clk/mmp.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/io.h>
  17. #include <linux/delay.h>
  18. #include <linux/err.h>
  19. #include "clk.h"
  20. #define APBC_RTC 0x28
  21. #define APBC_TWSI0 0x2c
  22. #define APBC_KPC 0x18
  23. #define APBC_UART0 0x0
  24. #define APBC_UART1 0x4
  25. #define APBC_GPIO 0x8
  26. #define APBC_PWM0 0xc
  27. #define APBC_PWM1 0x10
  28. #define APBC_PWM2 0x14
  29. #define APBC_PWM3 0x18
  30. #define APBC_SSP0 0x1c
  31. #define APBC_SSP1 0x20
  32. #define APBC_SSP2 0x4c
  33. #define APBCP_TWSI1 0x28
  34. #define APBCP_UART2 0x1c
  35. #define APMU_SDH0 0x54
  36. #define APMU_SDH1 0x58
  37. #define APMU_USB 0x5c
  38. #define APMU_DISP0 0x4c
  39. #define APMU_CCIC0 0x50
  40. #define APMU_DFC 0x60
  41. #define MPMU_UART_PLL 0x14
  42. static DEFINE_SPINLOCK(clk_lock);
  43. static struct mmp_clk_factor_masks uart_factor_masks = {
  44. .factor = 2,
  45. .num_mask = 0x1fff,
  46. .den_mask = 0x1fff,
  47. .num_shift = 16,
  48. .den_shift = 0,
  49. };
  50. static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
  51. {.num = 8125, .den = 1536}, /*14.745MHZ */
  52. };
  53. static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
  54. static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
  55. static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
  56. static const char *disp_parent[] = {"pll1_2", "pll1_12"};
  57. static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
  58. static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
  59. void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
  60. phys_addr_t apbc_phys, phys_addr_t apbcp_phys)
  61. {
  62. struct clk *clk;
  63. struct clk *uart_pll;
  64. void __iomem *mpmu_base;
  65. void __iomem *apmu_base;
  66. void __iomem *apbcp_base;
  67. void __iomem *apbc_base;
  68. mpmu_base = ioremap(mpmu_phys, SZ_4K);
  69. if (!mpmu_base) {
  70. pr_err("error to ioremap MPMU base\n");
  71. return;
  72. }
  73. apmu_base = ioremap(apmu_phys, SZ_4K);
  74. if (!apmu_base) {
  75. pr_err("error to ioremap APMU base\n");
  76. return;
  77. }
  78. apbcp_base = ioremap(apbcp_phys, SZ_4K);
  79. if (!apbcp_base) {
  80. pr_err("error to ioremap APBC extension base\n");
  81. return;
  82. }
  83. apbc_base = ioremap(apbc_phys, SZ_4K);
  84. if (!apbc_base) {
  85. pr_err("error to ioremap APBC base\n");
  86. return;
  87. }
  88. clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
  89. clk_register_clkdev(clk, "clk32", NULL);
  90. clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
  91. clk_register_clkdev(clk, "vctcxo", NULL);
  92. clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
  93. clk_register_clkdev(clk, "pll1", NULL);
  94. clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
  95. CLK_SET_RATE_PARENT, 1, 2);
  96. clk_register_clkdev(clk, "pll1_2", NULL);
  97. clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
  98. CLK_SET_RATE_PARENT, 1, 2);
  99. clk_register_clkdev(clk, "pll1_4", NULL);
  100. clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
  101. CLK_SET_RATE_PARENT, 1, 2);
  102. clk_register_clkdev(clk, "pll1_8", NULL);
  103. clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
  104. CLK_SET_RATE_PARENT, 1, 2);
  105. clk_register_clkdev(clk, "pll1_16", NULL);
  106. clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
  107. CLK_SET_RATE_PARENT, 1, 3);
  108. clk_register_clkdev(clk, "pll1_6", NULL);
  109. clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
  110. CLK_SET_RATE_PARENT, 1, 2);
  111. clk_register_clkdev(clk, "pll1_12", NULL);
  112. clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
  113. CLK_SET_RATE_PARENT, 1, 2);
  114. clk_register_clkdev(clk, "pll1_24", NULL);
  115. clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
  116. CLK_SET_RATE_PARENT, 1, 2);
  117. clk_register_clkdev(clk, "pll1_48", NULL);
  118. clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
  119. CLK_SET_RATE_PARENT, 1, 2);
  120. clk_register_clkdev(clk, "pll1_96", NULL);
  121. clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
  122. CLK_SET_RATE_PARENT, 1, 13);
  123. clk_register_clkdev(clk, "pll1_13", NULL);
  124. clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
  125. CLK_SET_RATE_PARENT, 2, 3);
  126. clk_register_clkdev(clk, "pll1_13_1_5", NULL);
  127. clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
  128. CLK_SET_RATE_PARENT, 2, 3);
  129. clk_register_clkdev(clk, "pll1_2_1_5", NULL);
  130. clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
  131. CLK_SET_RATE_PARENT, 3, 16);
  132. clk_register_clkdev(clk, "pll1_3_16", NULL);
  133. uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
  134. mpmu_base + MPMU_UART_PLL,
  135. &uart_factor_masks, uart_factor_tbl,
  136. ARRAY_SIZE(uart_factor_tbl), &clk_lock);
  137. clk_set_rate(uart_pll, 14745600);
  138. clk_register_clkdev(uart_pll, "uart_pll", NULL);
  139. clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
  140. apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
  141. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
  142. clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
  143. apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
  144. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
  145. clk = mmp_clk_register_apbc("gpio", "vctcxo",
  146. apbc_base + APBC_GPIO, 10, 0, &clk_lock);
  147. clk_register_clkdev(clk, NULL, "mmp-gpio");
  148. clk = mmp_clk_register_apbc("kpc", "clk32",
  149. apbc_base + APBC_KPC, 10, 0, &clk_lock);
  150. clk_register_clkdev(clk, NULL, "pxa27x-keypad");
  151. clk = mmp_clk_register_apbc("rtc", "clk32",
  152. apbc_base + APBC_RTC, 10, 0, &clk_lock);
  153. clk_register_clkdev(clk, NULL, "sa1100-rtc");
  154. clk = mmp_clk_register_apbc("pwm0", "pll1_48",
  155. apbc_base + APBC_PWM0, 10, 0, &clk_lock);
  156. clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
  157. clk = mmp_clk_register_apbc("pwm1", "pll1_48",
  158. apbc_base + APBC_PWM1, 10, 0, &clk_lock);
  159. clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
  160. clk = mmp_clk_register_apbc("pwm2", "pll1_48",
  161. apbc_base + APBC_PWM2, 10, 0, &clk_lock);
  162. clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
  163. clk = mmp_clk_register_apbc("pwm3", "pll1_48",
  164. apbc_base + APBC_PWM3, 10, 0, &clk_lock);
  165. clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
  166. clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
  167. ARRAY_SIZE(uart_parent),
  168. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  169. apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
  170. clk_set_parent(clk, uart_pll);
  171. clk_register_clkdev(clk, "uart_mux.0", NULL);
  172. clk = mmp_clk_register_apbc("uart0", "uart0_mux",
  173. apbc_base + APBC_UART0, 10, 0, &clk_lock);
  174. clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
  175. clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
  176. ARRAY_SIZE(uart_parent),
  177. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  178. apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
  179. clk_set_parent(clk, uart_pll);
  180. clk_register_clkdev(clk, "uart_mux.1", NULL);
  181. clk = mmp_clk_register_apbc("uart1", "uart1_mux",
  182. apbc_base + APBC_UART1, 10, 0, &clk_lock);
  183. clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
  184. clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
  185. ARRAY_SIZE(uart_parent),
  186. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  187. apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
  188. clk_set_parent(clk, uart_pll);
  189. clk_register_clkdev(clk, "uart_mux.2", NULL);
  190. clk = mmp_clk_register_apbc("uart2", "uart2_mux",
  191. apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
  192. clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
  193. clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
  194. ARRAY_SIZE(ssp_parent),
  195. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  196. apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
  197. clk_register_clkdev(clk, "uart_mux.0", NULL);
  198. clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
  199. apbc_base + APBC_SSP0, 10, 0, &clk_lock);
  200. clk_register_clkdev(clk, NULL, "mmp-ssp.0");
  201. clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
  202. ARRAY_SIZE(ssp_parent),
  203. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  204. apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
  205. clk_register_clkdev(clk, "ssp_mux.1", NULL);
  206. clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
  207. apbc_base + APBC_SSP1, 10, 0, &clk_lock);
  208. clk_register_clkdev(clk, NULL, "mmp-ssp.1");
  209. clk = mmp_clk_register_apmu("dfc", "pll1_4",
  210. apmu_base + APMU_DFC, 0x19b, &clk_lock);
  211. clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
  212. clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
  213. ARRAY_SIZE(sdh_parent),
  214. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  215. apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
  216. clk_register_clkdev(clk, "sdh0_mux", NULL);
  217. clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
  218. apmu_base + APMU_SDH0, 0x1b, &clk_lock);
  219. clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
  220. clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
  221. ARRAY_SIZE(sdh_parent),
  222. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  223. apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
  224. clk_register_clkdev(clk, "sdh1_mux", NULL);
  225. clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
  226. apmu_base + APMU_SDH1, 0x1b, &clk_lock);
  227. clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
  228. clk = mmp_clk_register_apmu("usb", "usb_pll",
  229. apmu_base + APMU_USB, 0x9, &clk_lock);
  230. clk_register_clkdev(clk, "usb_clk", NULL);
  231. clk = mmp_clk_register_apmu("sph", "usb_pll",
  232. apmu_base + APMU_USB, 0x12, &clk_lock);
  233. clk_register_clkdev(clk, "sph_clk", NULL);
  234. clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
  235. ARRAY_SIZE(disp_parent),
  236. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  237. apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
  238. clk_register_clkdev(clk, "disp_mux.0", NULL);
  239. clk = mmp_clk_register_apmu("disp0", "disp0_mux",
  240. apmu_base + APMU_DISP0, 0x1b, &clk_lock);
  241. clk_register_clkdev(clk, NULL, "mmp-disp.0");
  242. clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
  243. ARRAY_SIZE(ccic_parent),
  244. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  245. apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
  246. clk_register_clkdev(clk, "ccic_mux.0", NULL);
  247. clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
  248. apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
  249. clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
  250. clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
  251. ARRAY_SIZE(ccic_phy_parent),
  252. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  253. apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
  254. clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
  255. clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
  256. apmu_base + APMU_CCIC0, 0x24, &clk_lock);
  257. clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
  258. clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
  259. CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
  260. 10, 5, 0, &clk_lock);
  261. clk_register_clkdev(clk, "sphyclk_div", NULL);
  262. clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
  263. apmu_base + APMU_CCIC0, 0x300, &clk_lock);
  264. clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
  265. }