clk-of-pxa910.c 12 KB

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  1. /*
  2. * pxa910 clock framework source file
  3. *
  4. * Copyright (C) 2012 Marvell
  5. * Chao Xie <xiechao.mail@gmail.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/io.h>
  15. #include <linux/delay.h>
  16. #include <linux/err.h>
  17. #include <linux/of_address.h>
  18. #include <dt-bindings/clock/marvell,pxa910.h>
  19. #include "clk.h"
  20. #include "reset.h"
  21. #define APBC_RTC 0x28
  22. #define APBC_TWSI0 0x2c
  23. #define APBC_KPC 0x18
  24. #define APBC_UART0 0x0
  25. #define APBC_UART1 0x4
  26. #define APBC_GPIO 0x8
  27. #define APBC_PWM0 0xc
  28. #define APBC_PWM1 0x10
  29. #define APBC_PWM2 0x14
  30. #define APBC_PWM3 0x18
  31. #define APBC_SSP0 0x1c
  32. #define APBC_SSP1 0x20
  33. #define APBC_SSP2 0x4c
  34. #define APBC_TIMER0 0x30
  35. #define APBC_TIMER1 0x44
  36. #define APBCP_TWSI1 0x28
  37. #define APBCP_UART2 0x1c
  38. #define APMU_SDH0 0x54
  39. #define APMU_SDH1 0x58
  40. #define APMU_USB 0x5c
  41. #define APMU_DISP0 0x4c
  42. #define APMU_CCIC0 0x50
  43. #define APMU_DFC 0x60
  44. #define MPMU_UART_PLL 0x14
  45. struct pxa910_clk_unit {
  46. struct mmp_clk_unit unit;
  47. void __iomem *mpmu_base;
  48. void __iomem *apmu_base;
  49. void __iomem *apbc_base;
  50. void __iomem *apbcp_base;
  51. };
  52. static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
  53. {PXA910_CLK_CLK32, "clk32", NULL, 0, 32768},
  54. {PXA910_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
  55. {PXA910_CLK_PLL1, "pll1", NULL, 0, 624000000},
  56. {PXA910_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
  57. };
  58. static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
  59. {PXA910_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
  60. {PXA910_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
  61. {PXA910_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
  62. {PXA910_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
  63. {PXA910_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
  64. {PXA910_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
  65. {PXA910_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
  66. {PXA910_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
  67. {PXA910_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
  68. {PXA910_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0},
  69. {PXA910_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
  70. {PXA910_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
  71. {PXA910_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
  72. {PXA910_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
  73. };
  74. static struct mmp_clk_factor_masks uart_factor_masks = {
  75. .factor = 2,
  76. .num_mask = 0x1fff,
  77. .den_mask = 0x1fff,
  78. .num_shift = 16,
  79. .den_shift = 0,
  80. };
  81. static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
  82. {.num = 8125, .den = 1536}, /*14.745MHZ */
  83. };
  84. static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit)
  85. {
  86. struct clk *clk;
  87. struct mmp_clk_unit *unit = &pxa_unit->unit;
  88. mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
  89. ARRAY_SIZE(fixed_rate_clks));
  90. mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
  91. ARRAY_SIZE(fixed_factor_clks));
  92. clk = mmp_clk_register_factor("uart_pll", "pll1_4",
  93. CLK_SET_RATE_PARENT,
  94. pxa_unit->mpmu_base + MPMU_UART_PLL,
  95. &uart_factor_masks, uart_factor_tbl,
  96. ARRAY_SIZE(uart_factor_tbl), NULL);
  97. mmp_clk_add(unit, PXA910_CLK_UART_PLL, clk);
  98. }
  99. static DEFINE_SPINLOCK(uart0_lock);
  100. static DEFINE_SPINLOCK(uart1_lock);
  101. static DEFINE_SPINLOCK(uart2_lock);
  102. static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
  103. static DEFINE_SPINLOCK(ssp0_lock);
  104. static DEFINE_SPINLOCK(ssp1_lock);
  105. static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
  106. static DEFINE_SPINLOCK(timer0_lock);
  107. static DEFINE_SPINLOCK(timer1_lock);
  108. static const char *timer_parent_names[] = {"pll1_48", "clk32", "pll1_96"};
  109. static DEFINE_SPINLOCK(reset_lock);
  110. static struct mmp_param_mux_clk apbc_mux_clks[] = {
  111. {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
  112. {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
  113. {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
  114. {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
  115. {0, "timer0_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER0, 4, 3, 0, &timer0_lock},
  116. {0, "timer1_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER1, 4, 3, 0, &timer1_lock},
  117. };
  118. static struct mmp_param_mux_clk apbcp_mux_clks[] = {
  119. {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
  120. };
  121. static struct mmp_param_gate_clk apbc_gate_clks[] = {
  122. {PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
  123. {PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
  124. {PXA910_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
  125. {PXA910_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
  126. {PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
  127. {PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
  128. {PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
  129. {PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
  130. /* The gate clocks has mux parent. */
  131. {PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
  132. {PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
  133. {PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
  134. {PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
  135. {PXA910_CLK_TIMER0, "timer0_clk", "timer0_mux", CLK_SET_RATE_PARENT, APBC_TIMER0, 0x3, 0x3, 0x0, 0, &timer0_lock},
  136. {PXA910_CLK_TIMER1, "timer1_clk", "timer1_mux", CLK_SET_RATE_PARENT, APBC_TIMER1, 0x3, 0x3, 0x0, 0, &timer1_lock},
  137. };
  138. static struct mmp_param_gate_clk apbcp_gate_clks[] = {
  139. {PXA910_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
  140. /* The gate clocks has mux parent. */
  141. {PXA910_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
  142. };
  143. static void pxa910_apb_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
  144. {
  145. struct mmp_clk_unit *unit = &pxa_unit->unit;
  146. mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
  147. ARRAY_SIZE(apbc_mux_clks));
  148. mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base,
  149. ARRAY_SIZE(apbcp_mux_clks));
  150. mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
  151. ARRAY_SIZE(apbc_gate_clks));
  152. mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base,
  153. ARRAY_SIZE(apbcp_gate_clks));
  154. }
  155. static DEFINE_SPINLOCK(sdh0_lock);
  156. static DEFINE_SPINLOCK(sdh1_lock);
  157. static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
  158. static DEFINE_SPINLOCK(usb_lock);
  159. static DEFINE_SPINLOCK(disp0_lock);
  160. static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
  161. static DEFINE_SPINLOCK(ccic0_lock);
  162. static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
  163. static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
  164. static struct mmp_param_mux_clk apmu_mux_clks[] = {
  165. {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
  166. {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
  167. {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
  168. {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
  169. {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
  170. };
  171. static struct mmp_param_div_clk apmu_div_clks[] = {
  172. {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
  173. };
  174. static struct mmp_param_gate_clk apmu_gate_clks[] = {
  175. {PXA910_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
  176. {PXA910_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
  177. {PXA910_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
  178. /* The gate clocks has mux parent. */
  179. {PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
  180. {PXA910_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
  181. {PXA910_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
  182. {PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
  183. {PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
  184. {PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
  185. };
  186. static void pxa910_axi_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
  187. {
  188. struct mmp_clk_unit *unit = &pxa_unit->unit;
  189. mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
  190. ARRAY_SIZE(apmu_mux_clks));
  191. mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
  192. ARRAY_SIZE(apmu_div_clks));
  193. mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
  194. ARRAY_SIZE(apmu_gate_clks));
  195. }
  196. static void pxa910_clk_reset_init(struct device_node *np,
  197. struct pxa910_clk_unit *pxa_unit)
  198. {
  199. struct mmp_clk_reset_cell *cells;
  200. int i, base, nr_resets_apbc, nr_resets_apbcp, nr_resets;
  201. nr_resets_apbc = ARRAY_SIZE(apbc_gate_clks);
  202. nr_resets_apbcp = ARRAY_SIZE(apbcp_gate_clks);
  203. nr_resets = nr_resets_apbc + nr_resets_apbcp;
  204. cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
  205. if (!cells)
  206. return;
  207. base = 0;
  208. for (i = 0; i < nr_resets_apbc; i++) {
  209. cells[base + i].clk_id = apbc_gate_clks[i].id;
  210. cells[base + i].reg =
  211. pxa_unit->apbc_base + apbc_gate_clks[i].offset;
  212. cells[base + i].flags = 0;
  213. cells[base + i].lock = apbc_gate_clks[i].lock;
  214. cells[base + i].bits = 0x4;
  215. }
  216. base = nr_resets_apbc;
  217. for (i = 0; i < nr_resets_apbcp; i++) {
  218. cells[base + i].clk_id = apbcp_gate_clks[i].id;
  219. cells[base + i].reg =
  220. pxa_unit->apbc_base + apbc_gate_clks[i].offset;
  221. cells[base + i].flags = 0;
  222. cells[base + i].lock = apbc_gate_clks[i].lock;
  223. cells[base + i].bits = 0x4;
  224. }
  225. mmp_clk_reset_register(np, cells, nr_resets);
  226. }
  227. static void __init pxa910_clk_init(struct device_node *np)
  228. {
  229. struct pxa910_clk_unit *pxa_unit;
  230. pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
  231. if (!pxa_unit)
  232. return;
  233. pxa_unit->mpmu_base = of_iomap(np, 0);
  234. if (!pxa_unit->mpmu_base) {
  235. pr_err("failed to map mpmu registers\n");
  236. goto free_memory;
  237. }
  238. pxa_unit->apmu_base = of_iomap(np, 1);
  239. if (!pxa_unit->apmu_base) {
  240. pr_err("failed to map apmu registers\n");
  241. goto unmap_mpmu_region;
  242. }
  243. pxa_unit->apbc_base = of_iomap(np, 2);
  244. if (!pxa_unit->apbc_base) {
  245. pr_err("failed to map apbc registers\n");
  246. goto unmap_apmu_region;
  247. }
  248. pxa_unit->apbcp_base = of_iomap(np, 3);
  249. if (!pxa_unit->apbcp_base) {
  250. pr_err("failed to map apbcp registers\n");
  251. goto unmap_apbc_region;
  252. }
  253. mmp_clk_init(np, &pxa_unit->unit, PXA910_NR_CLKS);
  254. pxa910_pll_init(pxa_unit);
  255. pxa910_apb_periph_clk_init(pxa_unit);
  256. pxa910_axi_periph_clk_init(pxa_unit);
  257. pxa910_clk_reset_init(np, pxa_unit);
  258. return;
  259. unmap_apbc_region:
  260. iounmap(pxa_unit->apbc_base);
  261. unmap_apmu_region:
  262. iounmap(pxa_unit->apmu_base);
  263. unmap_mpmu_region:
  264. iounmap(pxa_unit->mpmu_base);
  265. free_memory:
  266. kfree(pxa_unit);
  267. }
  268. CLK_OF_DECLARE(pxa910_clk, "marvell,pxa910-clock", pxa910_clk_init);