clk-of-pxa1928.c 10 KB

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  1. /*
  2. * pxa1928 clock framework source file
  3. *
  4. * Copyright (C) 2015 Linaro, Ltd.
  5. * Rob Herring <robh@kernel.org>
  6. *
  7. * Based on drivers/clk/mmp/clk-of-mmp2.c:
  8. * Copyright (C) 2012 Marvell
  9. * Chao Xie <xiechao.mail@gmail.com>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/io.h>
  17. #include <linux/of_address.h>
  18. #include <linux/slab.h>
  19. #include <linux/spinlock.h>
  20. #include <dt-bindings/clock/marvell,pxa1928.h>
  21. #include "clk.h"
  22. #include "reset.h"
  23. #define MPMU_UART_PLL 0x14
  24. struct pxa1928_clk_unit {
  25. struct mmp_clk_unit unit;
  26. void __iomem *mpmu_base;
  27. void __iomem *apmu_base;
  28. void __iomem *apbc_base;
  29. void __iomem *apbcp_base;
  30. };
  31. static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
  32. {0, "clk32", NULL, 0, 32768},
  33. {0, "vctcxo", NULL, 0, 26000000},
  34. {0, "pll1_624", NULL, 0, 624000000},
  35. {0, "pll5p", NULL, 0, 832000000},
  36. {0, "pll5", NULL, 0, 1248000000},
  37. {0, "usb_pll", NULL, 0, 480000000},
  38. };
  39. static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
  40. {0, "pll1_d2", "pll1_624", 1, 2, 0},
  41. {0, "pll1_d9", "pll1_624", 1, 9, 0},
  42. {0, "pll1_d12", "pll1_624", 1, 12, 0},
  43. {0, "pll1_d16", "pll1_624", 1, 16, 0},
  44. {0, "pll1_d20", "pll1_624", 1, 20, 0},
  45. {0, "pll1_416", "pll1_624", 2, 3, 0},
  46. {0, "vctcxo_d2", "vctcxo", 1, 2, 0},
  47. {0, "vctcxo_d4", "vctcxo", 1, 4, 0},
  48. };
  49. static struct mmp_clk_factor_masks uart_factor_masks = {
  50. .factor = 2,
  51. .num_mask = 0x1fff,
  52. .den_mask = 0x1fff,
  53. .num_shift = 16,
  54. .den_shift = 0,
  55. };
  56. static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
  57. {.num = 832, .den = 234}, /*58.5MHZ */
  58. {.num = 1, .den = 1}, /*26MHZ */
  59. };
  60. static void pxa1928_pll_init(struct pxa1928_clk_unit *pxa_unit)
  61. {
  62. struct mmp_clk_unit *unit = &pxa_unit->unit;
  63. mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
  64. ARRAY_SIZE(fixed_rate_clks));
  65. mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
  66. ARRAY_SIZE(fixed_factor_clks));
  67. mmp_clk_register_factor("uart_pll", "pll1_416",
  68. CLK_SET_RATE_PARENT,
  69. pxa_unit->mpmu_base + MPMU_UART_PLL,
  70. &uart_factor_masks, uart_factor_tbl,
  71. ARRAY_SIZE(uart_factor_tbl), NULL);
  72. }
  73. static DEFINE_SPINLOCK(uart0_lock);
  74. static DEFINE_SPINLOCK(uart1_lock);
  75. static DEFINE_SPINLOCK(uart2_lock);
  76. static DEFINE_SPINLOCK(uart3_lock);
  77. static const char *uart_parent_names[] = {"uart_pll", "vctcxo"};
  78. static DEFINE_SPINLOCK(ssp0_lock);
  79. static DEFINE_SPINLOCK(ssp1_lock);
  80. static const char *ssp_parent_names[] = {"vctcxo_d4", "vctcxo_d2", "vctcxo", "pll1_d12"};
  81. static DEFINE_SPINLOCK(reset_lock);
  82. static struct mmp_param_mux_clk apbc_mux_clks[] = {
  83. {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 4, 3, 0, &uart0_lock},
  84. {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 4, 3, 0, &uart1_lock},
  85. {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 4, 3, 0, &uart2_lock},
  86. {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART3 * 4, 4, 3, 0, &uart3_lock},
  87. {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 4, 3, 0, &ssp0_lock},
  88. {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP1 * 4, 4, 3, 0, &ssp1_lock},
  89. };
  90. static struct mmp_param_gate_clk apbc_gate_clks[] = {
  91. {PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
  92. {PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
  93. {PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
  94. {PXA1928_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI3 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
  95. {PXA1928_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI4 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
  96. {PXA1928_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI5 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
  97. {PXA1928_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_GPIO * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
  98. {PXA1928_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, PXA1928_CLK_KPC * 4, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
  99. {PXA1928_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, PXA1928_CLK_RTC * 4, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
  100. {PXA1928_CLK_PWM0, "pwm0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
  101. {PXA1928_CLK_PWM1, "pwm1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
  102. {PXA1928_CLK_PWM2, "pwm2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM2 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
  103. {PXA1928_CLK_PWM3, "pwm3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM3 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
  104. /* The gate clocks has mux parent. */
  105. {PXA1928_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 0x3, 0x3, 0x0, 0, &uart0_lock},
  106. {PXA1928_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 0x3, 0x3, 0x0, 0, &uart1_lock},
  107. {PXA1928_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 0x3, 0x3, 0x0, 0, &uart2_lock},
  108. {PXA1928_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART3 * 4, 0x3, 0x3, 0x0, 0, &uart3_lock},
  109. {PXA1928_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 0x3, 0x3, 0x0, 0, &ssp0_lock},
  110. {PXA1928_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_SSP1 * 4, 0x3, 0x3, 0x0, 0, &ssp1_lock},
  111. };
  112. static void pxa1928_apb_periph_clk_init(struct pxa1928_clk_unit *pxa_unit)
  113. {
  114. struct mmp_clk_unit *unit = &pxa_unit->unit;
  115. mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
  116. ARRAY_SIZE(apbc_mux_clks));
  117. mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
  118. ARRAY_SIZE(apbc_gate_clks));
  119. }
  120. static DEFINE_SPINLOCK(sdh0_lock);
  121. static DEFINE_SPINLOCK(sdh1_lock);
  122. static DEFINE_SPINLOCK(sdh2_lock);
  123. static DEFINE_SPINLOCK(sdh3_lock);
  124. static DEFINE_SPINLOCK(sdh4_lock);
  125. static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"};
  126. static DEFINE_SPINLOCK(usb_lock);
  127. static struct mmp_param_mux_clk apmu_mux_clks[] = {
  128. {0, "sdh_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SDH0 * 4, 8, 2, 0, &sdh0_lock},
  129. };
  130. static struct mmp_param_div_clk apmu_div_clks[] = {
  131. {0, "sdh_div", "sdh_mux", 0, PXA1928_CLK_SDH0 * 4, 10, 4, CLK_DIVIDER_ONE_BASED, &sdh0_lock},
  132. };
  133. static struct mmp_param_gate_clk apmu_gate_clks[] = {
  134. {PXA1928_CLK_USB, "usb_clk", "usb_pll", 0, PXA1928_CLK_USB * 4, 0x9, 0x9, 0x0, 0, &usb_lock},
  135. {PXA1928_CLK_HSIC, "hsic_clk", "usb_pll", 0, PXA1928_CLK_HSIC * 4, 0x9, 0x9, 0x0, 0, &usb_lock},
  136. /* The gate clocks has mux parent. */
  137. {PXA1928_CLK_SDH0, "sdh0_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH0 * 4, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
  138. {PXA1928_CLK_SDH1, "sdh1_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH1 * 4, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
  139. {PXA1928_CLK_SDH2, "sdh2_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH2 * 4, 0x1b, 0x1b, 0x0, 0, &sdh2_lock},
  140. {PXA1928_CLK_SDH3, "sdh3_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH3 * 4, 0x1b, 0x1b, 0x0, 0, &sdh3_lock},
  141. {PXA1928_CLK_SDH4, "sdh4_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH4 * 4, 0x1b, 0x1b, 0x0, 0, &sdh4_lock},
  142. };
  143. static void pxa1928_axi_periph_clk_init(struct pxa1928_clk_unit *pxa_unit)
  144. {
  145. struct mmp_clk_unit *unit = &pxa_unit->unit;
  146. mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
  147. ARRAY_SIZE(apmu_mux_clks));
  148. mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
  149. ARRAY_SIZE(apmu_div_clks));
  150. mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
  151. ARRAY_SIZE(apmu_gate_clks));
  152. }
  153. static void pxa1928_clk_reset_init(struct device_node *np,
  154. struct pxa1928_clk_unit *pxa_unit)
  155. {
  156. struct mmp_clk_reset_cell *cells;
  157. int i, base, nr_resets;
  158. nr_resets = ARRAY_SIZE(apbc_gate_clks);
  159. cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
  160. if (!cells)
  161. return;
  162. base = 0;
  163. for (i = 0; i < nr_resets; i++) {
  164. cells[base + i].clk_id = apbc_gate_clks[i].id;
  165. cells[base + i].reg =
  166. pxa_unit->apbc_base + apbc_gate_clks[i].offset;
  167. cells[base + i].flags = 0;
  168. cells[base + i].lock = apbc_gate_clks[i].lock;
  169. cells[base + i].bits = 0x4;
  170. }
  171. mmp_clk_reset_register(np, cells, nr_resets);
  172. }
  173. static void __init pxa1928_mpmu_clk_init(struct device_node *np)
  174. {
  175. struct pxa1928_clk_unit *pxa_unit;
  176. pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
  177. if (!pxa_unit)
  178. return;
  179. pxa_unit->mpmu_base = of_iomap(np, 0);
  180. if (!pxa_unit->mpmu_base) {
  181. pr_err("failed to map mpmu registers\n");
  182. kfree(pxa_unit);
  183. return;
  184. }
  185. pxa1928_pll_init(pxa_unit);
  186. }
  187. CLK_OF_DECLARE(pxa1928_mpmu_clk, "marvell,pxa1928-mpmu", pxa1928_mpmu_clk_init);
  188. static void __init pxa1928_apmu_clk_init(struct device_node *np)
  189. {
  190. struct pxa1928_clk_unit *pxa_unit;
  191. pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
  192. if (!pxa_unit)
  193. return;
  194. pxa_unit->apmu_base = of_iomap(np, 0);
  195. if (!pxa_unit->apmu_base) {
  196. pr_err("failed to map apmu registers\n");
  197. kfree(pxa_unit);
  198. return;
  199. }
  200. mmp_clk_init(np, &pxa_unit->unit, PXA1928_APMU_NR_CLKS);
  201. pxa1928_axi_periph_clk_init(pxa_unit);
  202. }
  203. CLK_OF_DECLARE(pxa1928_apmu_clk, "marvell,pxa1928-apmu", pxa1928_apmu_clk_init);
  204. static void __init pxa1928_apbc_clk_init(struct device_node *np)
  205. {
  206. struct pxa1928_clk_unit *pxa_unit;
  207. pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
  208. if (!pxa_unit)
  209. return;
  210. pxa_unit->apbc_base = of_iomap(np, 0);
  211. if (!pxa_unit->apbc_base) {
  212. pr_err("failed to map apbc registers\n");
  213. kfree(pxa_unit);
  214. return;
  215. }
  216. mmp_clk_init(np, &pxa_unit->unit, PXA1928_APBC_NR_CLKS);
  217. pxa1928_apb_periph_clk_init(pxa_unit);
  218. pxa1928_clk_reset_init(np, pxa_unit);
  219. }
  220. CLK_OF_DECLARE(pxa1928_apbc_clk, "marvell,pxa1928-apbc", pxa1928_apbc_clk_init);