clk-of-mmp2.c 23 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570
  1. /*
  2. * mmp2 clock framework source file
  3. *
  4. * Copyright (C) 2012 Marvell
  5. * Chao Xie <xiechao.mail@gmail.com>
  6. * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/io.h>
  16. #include <linux/delay.h>
  17. #include <linux/err.h>
  18. #include <linux/of_address.h>
  19. #include <linux/clk.h>
  20. #include <dt-bindings/clock/marvell,mmp2.h>
  21. #include <dt-bindings/power/marvell,mmp2.h>
  22. #include "clk.h"
  23. #include "reset.h"
  24. #define APBC_RTC 0x0
  25. #define APBC_TWSI0 0x4
  26. #define APBC_TWSI1 0x8
  27. #define APBC_TWSI2 0xc
  28. #define APBC_TWSI3 0x10
  29. #define APBC_TWSI4 0x7c
  30. #define APBC_TWSI5 0x80
  31. #define APBC_KPC 0x18
  32. #define APBC_TIMER 0x24
  33. #define APBC_UART0 0x2c
  34. #define APBC_UART1 0x30
  35. #define APBC_UART2 0x34
  36. #define APBC_UART3 0x88
  37. #define APBC_GPIO 0x38
  38. #define APBC_PWM0 0x3c
  39. #define APBC_PWM1 0x40
  40. #define APBC_PWM2 0x44
  41. #define APBC_PWM3 0x48
  42. #define APBC_SSP0 0x50
  43. #define APBC_SSP1 0x54
  44. #define APBC_SSP2 0x58
  45. #define APBC_SSP3 0x5c
  46. #define APBC_THERMAL0 0x90
  47. #define APBC_THERMAL1 0x98
  48. #define APBC_THERMAL2 0x9c
  49. #define APBC_THERMAL3 0xa0
  50. #define APMU_SDH0 0x54
  51. #define APMU_SDH1 0x58
  52. #define APMU_SDH2 0xe8
  53. #define APMU_SDH3 0xec
  54. #define APMU_SDH4 0x15c
  55. #define APMU_USB 0x5c
  56. #define APMU_DISP0 0x4c
  57. #define APMU_DISP1 0x110
  58. #define APMU_CCIC0 0x50
  59. #define APMU_CCIC1 0xf4
  60. #define APMU_USBHSIC0 0xf8
  61. #define APMU_USBHSIC1 0xfc
  62. #define APMU_GPU 0xcc
  63. #define APMU_AUDIO 0x10c
  64. #define APMU_CAMERA 0x1fc
  65. #define MPMU_FCCR 0x8
  66. #define MPMU_POSR 0x10
  67. #define MPMU_UART_PLL 0x14
  68. #define MPMU_PLL2_CR 0x34
  69. #define MPMU_I2S0_PLL 0x40
  70. #define MPMU_I2S1_PLL 0x44
  71. #define MPMU_ACGR 0x1024
  72. /* MMP3 specific below */
  73. #define MPMU_PLL3_CR 0x50
  74. #define MPMU_PLL3_CTRL1 0x58
  75. #define MPMU_PLL1_CTRL 0x5c
  76. #define MPMU_PLL_DIFF_CTRL 0x68
  77. #define MPMU_PLL2_CTRL1 0x414
  78. enum mmp2_clk_model {
  79. CLK_MODEL_MMP2,
  80. CLK_MODEL_MMP3,
  81. };
  82. struct mmp2_clk_unit {
  83. struct mmp_clk_unit unit;
  84. enum mmp2_clk_model model;
  85. struct genpd_onecell_data pd_data;
  86. struct generic_pm_domain *pm_domains[MMP2_NR_POWER_DOMAINS];
  87. void __iomem *mpmu_base;
  88. void __iomem *apmu_base;
  89. void __iomem *apbc_base;
  90. };
  91. static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
  92. {MMP2_CLK_CLK32, "clk32", NULL, 0, 32768},
  93. {MMP2_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
  94. {MMP2_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
  95. {0, "i2s_pll", NULL, 0, 99666667},
  96. };
  97. static struct mmp_param_pll_clk pll_clks[] = {
  98. {MMP2_CLK_PLL1, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0},
  99. {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10},
  100. };
  101. static struct mmp_param_pll_clk mmp3_pll_clks[] = {
  102. {MMP2_CLK_PLL2, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0, 26000000, MPMU_PLL1_CTRL, 25},
  103. {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10, 26000000, MPMU_PLL2_CTRL1, 25},
  104. {MMP3_CLK_PLL1_P, "pll1_p", 0, MPMU_PLL_DIFF_CTRL, 0x0010, 0, 0, 797330000, MPMU_PLL_DIFF_CTRL, 0},
  105. {MMP3_CLK_PLL2_P, "pll2_p", 0, MPMU_PLL_DIFF_CTRL, 0x0100, MPMU_PLL2_CR, 10, 26000000, MPMU_PLL_DIFF_CTRL, 5},
  106. {MMP3_CLK_PLL3, "pll3", 0, MPMU_PLL3_CR, 0x0300, MPMU_PLL3_CR, 10, 26000000, MPMU_PLL3_CTRL1, 25},
  107. };
  108. static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
  109. {MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
  110. {MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
  111. {MMP2_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
  112. {MMP2_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
  113. {MMP2_CLK_PLL1_20, "pll1_20", "pll1_4", 1, 5, 0},
  114. {MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0},
  115. {MMP2_CLK_PLL1_6, "pll1_6", "pll1_3", 1, 2, 0},
  116. {MMP2_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
  117. {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
  118. {MMP2_CLK_PLL2_4, "pll2_4", "pll2_2", 1, 2, 0},
  119. {MMP2_CLK_PLL2_8, "pll2_8", "pll2_4", 1, 2, 0},
  120. {MMP2_CLK_PLL2_16, "pll2_16", "pll2_8", 1, 2, 0},
  121. {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
  122. {MMP2_CLK_PLL2_6, "pll2_6", "pll2_3", 1, 2, 0},
  123. {MMP2_CLK_PLL2_12, "pll2_12", "pll2_6", 1, 2, 0},
  124. {MMP2_CLK_VCTCXO_2, "vctcxo_2", "vctcxo", 1, 2, 0},
  125. {MMP2_CLK_VCTCXO_4, "vctcxo_4", "vctcxo_2", 1, 2, 0},
  126. };
  127. static struct mmp_clk_factor_masks uart_factor_masks = {
  128. .factor = 2,
  129. .num_mask = 0x1fff,
  130. .den_mask = 0x1fff,
  131. .num_shift = 16,
  132. .den_shift = 0,
  133. };
  134. static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
  135. {.num = 8125, .den = 1536}, /*14.745MHZ */
  136. {.num = 3521, .den = 689}, /*19.23MHZ */
  137. };
  138. static struct mmp_clk_factor_masks i2s_factor_masks = {
  139. .factor = 2,
  140. .num_mask = 0x7fff,
  141. .den_mask = 0x1fff,
  142. .num_shift = 0,
  143. .den_shift = 15,
  144. .enable_mask = 0xd0000000,
  145. };
  146. static struct mmp_clk_factor_tbl i2s_factor_tbl[] = {
  147. {.num = 24868, .den = 511}, /* 2.0480 MHz */
  148. {.num = 28003, .den = 793}, /* 2.8224 MHz */
  149. {.num = 24941, .den = 1025}, /* 4.0960 MHz */
  150. {.num = 28003, .den = 1586}, /* 5.6448 MHz */
  151. {.num = 31158, .den = 2561}, /* 8.1920 MHz */
  152. {.num = 16288, .den = 1845}, /* 11.2896 MHz */
  153. {.num = 20772, .den = 2561}, /* 12.2880 MHz */
  154. {.num = 8144, .den = 1845}, /* 22.5792 MHz */
  155. {.num = 10386, .den = 2561}, /* 24.5760 MHz */
  156. };
  157. static DEFINE_SPINLOCK(acgr_lock);
  158. static struct mmp_param_gate_clk mpmu_gate_clks[] = {
  159. {MMP2_CLK_I2S0, "i2s0_clk", "i2s0_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x200000, 0x200000, 0x0, 0, &acgr_lock},
  160. {MMP2_CLK_I2S1, "i2s1_clk", "i2s1_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x100000, 0x100000, 0x0, 0, &acgr_lock},
  161. };
  162. static void mmp2_main_clk_init(struct mmp2_clk_unit *pxa_unit)
  163. {
  164. struct clk *clk;
  165. struct mmp_clk_unit *unit = &pxa_unit->unit;
  166. mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
  167. ARRAY_SIZE(fixed_rate_clks));
  168. if (pxa_unit->model == CLK_MODEL_MMP3) {
  169. mmp_register_pll_clks(unit, mmp3_pll_clks,
  170. pxa_unit->mpmu_base,
  171. ARRAY_SIZE(mmp3_pll_clks));
  172. } else {
  173. mmp_register_pll_clks(unit, pll_clks,
  174. pxa_unit->mpmu_base,
  175. ARRAY_SIZE(pll_clks));
  176. }
  177. mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
  178. ARRAY_SIZE(fixed_factor_clks));
  179. clk = mmp_clk_register_factor("uart_pll", "pll1_4",
  180. CLK_SET_RATE_PARENT,
  181. pxa_unit->mpmu_base + MPMU_UART_PLL,
  182. &uart_factor_masks, uart_factor_tbl,
  183. ARRAY_SIZE(uart_factor_tbl), NULL);
  184. mmp_clk_add(unit, MMP2_CLK_UART_PLL, clk);
  185. mmp_clk_register_factor("i2s0_pll", "pll1_4",
  186. CLK_SET_RATE_PARENT,
  187. pxa_unit->mpmu_base + MPMU_I2S0_PLL,
  188. &i2s_factor_masks, i2s_factor_tbl,
  189. ARRAY_SIZE(i2s_factor_tbl), NULL);
  190. mmp_clk_register_factor("i2s1_pll", "pll1_4",
  191. CLK_SET_RATE_PARENT,
  192. pxa_unit->mpmu_base + MPMU_I2S1_PLL,
  193. &i2s_factor_masks, i2s_factor_tbl,
  194. ARRAY_SIZE(i2s_factor_tbl), NULL);
  195. mmp_register_gate_clks(unit, mpmu_gate_clks, pxa_unit->mpmu_base,
  196. ARRAY_SIZE(mpmu_gate_clks));
  197. }
  198. static DEFINE_SPINLOCK(uart0_lock);
  199. static DEFINE_SPINLOCK(uart1_lock);
  200. static DEFINE_SPINLOCK(uart2_lock);
  201. static const char * const uart_parent_names[] = {"uart_pll", "vctcxo"};
  202. static DEFINE_SPINLOCK(ssp0_lock);
  203. static DEFINE_SPINLOCK(ssp1_lock);
  204. static DEFINE_SPINLOCK(ssp2_lock);
  205. static DEFINE_SPINLOCK(ssp3_lock);
  206. static const char * const ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
  207. static DEFINE_SPINLOCK(timer_lock);
  208. static const char * const timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
  209. static DEFINE_SPINLOCK(reset_lock);
  210. static struct mmp_param_mux_clk apbc_mux_clks[] = {
  211. {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
  212. {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
  213. {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
  214. {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock},
  215. {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
  216. {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
  217. {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
  218. {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
  219. {0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER, 4, 3, 0, &timer_lock},
  220. };
  221. static struct mmp_param_gate_clk apbc_gate_clks[] = {
  222. {MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},
  223. {MMP2_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock},
  224. {MMP2_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock},
  225. {MMP2_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock},
  226. {MMP2_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock},
  227. {MMP2_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_lock},
  228. {MMP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock},
  229. {MMP2_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
  230. {MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
  231. {MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock},
  232. {MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lock},
  233. {MMP2_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x7, 0x3, 0x0, 0, &reset_lock},
  234. {MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lock},
  235. /* The gate clocks has mux parent. */
  236. {MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uart0_lock},
  237. {MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uart1_lock},
  238. {MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
  239. {MMP2_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, APBC_UART3, 0x7, 0x3, 0x0, 0, &uart2_lock},
  240. {MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lock},
  241. {MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lock},
  242. {MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lock},
  243. {MMP2_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x7, 0x3, 0x0, 0, &ssp3_lock},
  244. {MMP2_CLK_TIMER, "timer_clk", "timer_mux", CLK_SET_RATE_PARENT, APBC_TIMER, 0x7, 0x3, 0x0, 0, &timer_lock},
  245. {MMP2_CLK_THERMAL0, "thermal0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL0, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
  246. };
  247. static struct mmp_param_gate_clk mmp3_apbc_gate_clks[] = {
  248. {MMP3_CLK_THERMAL1, "thermal1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL1, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
  249. {MMP3_CLK_THERMAL2, "thermal2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL2, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
  250. {MMP3_CLK_THERMAL3, "thermal3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL3, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
  251. };
  252. static void mmp2_apb_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
  253. {
  254. struct mmp_clk_unit *unit = &pxa_unit->unit;
  255. mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
  256. ARRAY_SIZE(apbc_mux_clks));
  257. mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
  258. ARRAY_SIZE(apbc_gate_clks));
  259. if (pxa_unit->model == CLK_MODEL_MMP3) {
  260. mmp_register_gate_clks(unit, mmp3_apbc_gate_clks, pxa_unit->apbc_base,
  261. ARRAY_SIZE(mmp3_apbc_gate_clks));
  262. }
  263. }
  264. static DEFINE_SPINLOCK(sdh_lock);
  265. static const char * const sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
  266. static struct mmp_clk_mix_config sdh_mix_config = {
  267. .reg_info = DEFINE_MIX_REG_INFO(4, 10, 2, 8, 32),
  268. };
  269. static DEFINE_SPINLOCK(usb_lock);
  270. static DEFINE_SPINLOCK(usbhsic0_lock);
  271. static DEFINE_SPINLOCK(usbhsic1_lock);
  272. static DEFINE_SPINLOCK(disp0_lock);
  273. static DEFINE_SPINLOCK(disp1_lock);
  274. static const char * const disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
  275. static DEFINE_SPINLOCK(ccic0_lock);
  276. static DEFINE_SPINLOCK(ccic1_lock);
  277. static const char * const ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"};
  278. static DEFINE_SPINLOCK(gpu_lock);
  279. static const char * const mmp2_gpu_gc_parent_names[] = {"pll1_2", "pll1_3", "pll2_2", "pll2_3", "pll2", "usb_pll"};
  280. static u32 mmp2_gpu_gc_parent_table[] = { 0x0000, 0x0040, 0x0080, 0x00c0, 0x1000, 0x1040 };
  281. static const char * const mmp2_gpu_bus_parent_names[] = {"pll1_4", "pll2", "pll2_2", "usb_pll"};
  282. static u32 mmp2_gpu_bus_parent_table[] = { 0x0000, 0x0020, 0x0030, 0x4020 };
  283. static const char * const mmp3_gpu_bus_parent_names[] = {"pll1_4", "pll1_6", "pll1_2", "pll2_2"};
  284. static const char * const mmp3_gpu_gc_parent_names[] = {"pll1", "pll2", "pll1_p", "pll2_p"};
  285. static DEFINE_SPINLOCK(audio_lock);
  286. static struct mmp_clk_mix_config ccic0_mix_config = {
  287. .reg_info = DEFINE_MIX_REG_INFO(4, 17, 2, 6, 32),
  288. };
  289. static struct mmp_clk_mix_config ccic1_mix_config = {
  290. .reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32),
  291. };
  292. static struct mmp_param_mux_clk apmu_mux_clks[] = {
  293. {MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},
  294. {MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
  295. };
  296. static struct mmp_param_mux_clk mmp3_apmu_mux_clks[] = {
  297. {0, "gpu_bus_mux", mmp3_gpu_bus_parent_names, ARRAY_SIZE(mmp3_gpu_bus_parent_names),
  298. CLK_SET_RATE_PARENT, APMU_GPU, 4, 2, 0, &gpu_lock},
  299. {0, "gpu_3d_mux", mmp3_gpu_gc_parent_names, ARRAY_SIZE(mmp3_gpu_gc_parent_names),
  300. CLK_SET_RATE_PARENT, APMU_GPU, 6, 2, 0, &gpu_lock},
  301. {0, "gpu_2d_mux", mmp3_gpu_gc_parent_names, ARRAY_SIZE(mmp3_gpu_gc_parent_names),
  302. CLK_SET_RATE_PARENT, APMU_GPU, 12, 2, 0, &gpu_lock},
  303. };
  304. static struct mmp_param_div_clk apmu_div_clks[] = {
  305. {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &disp0_lock},
  306. {0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
  307. {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, CLK_DIVIDER_ONE_BASED, &disp1_lock},
  308. {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
  309. {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
  310. };
  311. static struct mmp_param_div_clk mmp3_apmu_div_clks[] = {
  312. {0, "gpu_3d_div", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 24, 4, 0, &gpu_lock},
  313. {0, "gpu_2d_div", "gpu_2d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 28, 4, 0, &gpu_lock},
  314. };
  315. static struct mmp_param_gate_clk apmu_gate_clks[] = {
  316. {MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
  317. {MMP2_CLK_USBHSIC0, "usbhsic0_clk", "usb_pll", 0, APMU_USBHSIC0, 0x1b, 0x1b, 0x0, 0, &usbhsic0_lock},
  318. {MMP2_CLK_USBHSIC1, "usbhsic1_clk", "usb_pll", 0, APMU_USBHSIC1, 0x1b, 0x1b, 0x0, 0, &usbhsic1_lock},
  319. /* The gate clocks has mux parent. */
  320. {MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
  321. {MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
  322. {MMP2_CLK_SDH2, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
  323. {MMP2_CLK_SDH3, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
  324. {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x12, 0x12, 0x0, 0, &disp0_lock},
  325. {MMP2_CLK_DISP0_LCDC, "disp0_lcdc_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x09, 0x09, 0x0, 0, &disp0_lock},
  326. {MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
  327. {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x09, 0x09, 0x0, 0, &disp1_lock},
  328. {MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock},
  329. {MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
  330. {MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
  331. {MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
  332. {MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
  333. {MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
  334. {MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
  335. {MMP2_CLK_GPU_BUS, "gpu_bus_clk", "gpu_bus_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0xa, 0xa, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
  336. {MMP2_CLK_AUDIO, "audio_clk", "audio_mix_clk", CLK_SET_RATE_PARENT, APMU_AUDIO, 0x12, 0x12, 0x0, 0, &audio_lock},
  337. };
  338. static struct mmp_param_gate_clk mmp2_apmu_gate_clks[] = {
  339. {MMP2_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
  340. };
  341. static struct mmp_param_gate_clk mmp3_apmu_gate_clks[] = {
  342. {MMP3_CLK_SDH4, "sdh4_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH4, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
  343. {MMP3_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
  344. {MMP3_CLK_GPU_2D, "gpu_2d_clk", "gpu_2d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x1c0000, 0x1c0000, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
  345. };
  346. static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
  347. {
  348. struct clk *clk;
  349. struct mmp_clk_unit *unit = &pxa_unit->unit;
  350. sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0;
  351. clk = mmp_clk_register_mix(NULL, "sdh_mix_clk", sdh_parent_names,
  352. ARRAY_SIZE(sdh_parent_names),
  353. CLK_SET_RATE_PARENT,
  354. &sdh_mix_config, &sdh_lock);
  355. ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0;
  356. clk = mmp_clk_register_mix(NULL, "ccic0_mix_clk", ccic_parent_names,
  357. ARRAY_SIZE(ccic_parent_names),
  358. CLK_SET_RATE_PARENT,
  359. &ccic0_mix_config, &ccic0_lock);
  360. mmp_clk_add(unit, MMP2_CLK_CCIC0_MIX, clk);
  361. ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1;
  362. clk = mmp_clk_register_mix(NULL, "ccic1_mix_clk", ccic_parent_names,
  363. ARRAY_SIZE(ccic_parent_names),
  364. CLK_SET_RATE_PARENT,
  365. &ccic1_mix_config, &ccic1_lock);
  366. mmp_clk_add(unit, MMP2_CLK_CCIC1_MIX, clk);
  367. mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
  368. ARRAY_SIZE(apmu_mux_clks));
  369. mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
  370. ARRAY_SIZE(apmu_div_clks));
  371. mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
  372. ARRAY_SIZE(apmu_gate_clks));
  373. if (pxa_unit->model == CLK_MODEL_MMP3) {
  374. mmp_register_mux_clks(unit, mmp3_apmu_mux_clks, pxa_unit->apmu_base,
  375. ARRAY_SIZE(mmp3_apmu_mux_clks));
  376. mmp_register_div_clks(unit, mmp3_apmu_div_clks, pxa_unit->apmu_base,
  377. ARRAY_SIZE(mmp3_apmu_div_clks));
  378. mmp_register_gate_clks(unit, mmp3_apmu_gate_clks, pxa_unit->apmu_base,
  379. ARRAY_SIZE(mmp3_apmu_gate_clks));
  380. } else {
  381. clk_register_mux_table(NULL, "gpu_3d_mux", mmp2_gpu_gc_parent_names,
  382. ARRAY_SIZE(mmp2_gpu_gc_parent_names),
  383. CLK_SET_RATE_PARENT,
  384. pxa_unit->apmu_base + APMU_GPU,
  385. 0, 0x10c0, 0,
  386. mmp2_gpu_gc_parent_table, &gpu_lock);
  387. clk_register_mux_table(NULL, "gpu_bus_mux", mmp2_gpu_bus_parent_names,
  388. ARRAY_SIZE(mmp2_gpu_bus_parent_names),
  389. CLK_SET_RATE_PARENT,
  390. pxa_unit->apmu_base + APMU_GPU,
  391. 0, 0x4030, 0,
  392. mmp2_gpu_bus_parent_table, &gpu_lock);
  393. mmp_register_gate_clks(unit, mmp2_apmu_gate_clks, pxa_unit->apmu_base,
  394. ARRAY_SIZE(mmp2_apmu_gate_clks));
  395. }
  396. }
  397. static void mmp2_clk_reset_init(struct device_node *np,
  398. struct mmp2_clk_unit *pxa_unit)
  399. {
  400. struct mmp_clk_reset_cell *cells;
  401. int i, nr_resets;
  402. nr_resets = ARRAY_SIZE(apbc_gate_clks);
  403. cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
  404. if (!cells)
  405. return;
  406. for (i = 0; i < nr_resets; i++) {
  407. cells[i].clk_id = apbc_gate_clks[i].id;
  408. cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
  409. cells[i].flags = 0;
  410. cells[i].lock = apbc_gate_clks[i].lock;
  411. cells[i].bits = 0x4;
  412. }
  413. mmp_clk_reset_register(np, cells, nr_resets);
  414. }
  415. static void mmp2_pm_domain_init(struct device_node *np,
  416. struct mmp2_clk_unit *pxa_unit)
  417. {
  418. if (pxa_unit->model == CLK_MODEL_MMP3) {
  419. pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU]
  420. = mmp_pm_domain_register("gpu",
  421. pxa_unit->apmu_base + APMU_GPU,
  422. 0x0600, 0x40003, 0x18000c, 0, &gpu_lock);
  423. } else {
  424. pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU]
  425. = mmp_pm_domain_register("gpu",
  426. pxa_unit->apmu_base + APMU_GPU,
  427. 0x8600, 0x00003, 0x00000c,
  428. MMP_PM_DOMAIN_NO_DISABLE, &gpu_lock);
  429. }
  430. pxa_unit->pd_data.num_domains++;
  431. pxa_unit->pm_domains[MMP2_POWER_DOMAIN_AUDIO]
  432. = mmp_pm_domain_register("audio",
  433. pxa_unit->apmu_base + APMU_AUDIO,
  434. 0x600, 0x2, 0, 0, &audio_lock);
  435. pxa_unit->pd_data.num_domains++;
  436. if (pxa_unit->model == CLK_MODEL_MMP3) {
  437. pxa_unit->pm_domains[MMP3_POWER_DOMAIN_CAMERA]
  438. = mmp_pm_domain_register("camera",
  439. pxa_unit->apmu_base + APMU_CAMERA,
  440. 0x600, 0, 0, 0, NULL);
  441. pxa_unit->pd_data.num_domains++;
  442. }
  443. pxa_unit->pd_data.domains = pxa_unit->pm_domains;
  444. of_genpd_add_provider_onecell(np, &pxa_unit->pd_data);
  445. }
  446. static void __init mmp2_clk_init(struct device_node *np)
  447. {
  448. struct mmp2_clk_unit *pxa_unit;
  449. pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
  450. if (!pxa_unit)
  451. return;
  452. if (of_device_is_compatible(np, "marvell,mmp3-clock"))
  453. pxa_unit->model = CLK_MODEL_MMP3;
  454. else
  455. pxa_unit->model = CLK_MODEL_MMP2;
  456. pxa_unit->mpmu_base = of_iomap(np, 0);
  457. if (!pxa_unit->mpmu_base) {
  458. pr_err("failed to map mpmu registers\n");
  459. goto free_memory;
  460. }
  461. pxa_unit->apmu_base = of_iomap(np, 1);
  462. if (!pxa_unit->apmu_base) {
  463. pr_err("failed to map apmu registers\n");
  464. goto unmap_mpmu_region;
  465. }
  466. pxa_unit->apbc_base = of_iomap(np, 2);
  467. if (!pxa_unit->apbc_base) {
  468. pr_err("failed to map apbc registers\n");
  469. goto unmap_apmu_region;
  470. }
  471. mmp2_pm_domain_init(np, pxa_unit);
  472. mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS);
  473. mmp2_main_clk_init(pxa_unit);
  474. mmp2_apb_periph_clk_init(pxa_unit);
  475. mmp2_axi_periph_clk_init(pxa_unit);
  476. mmp2_clk_reset_init(np, pxa_unit);
  477. return;
  478. unmap_apmu_region:
  479. iounmap(pxa_unit->apmu_base);
  480. unmap_mpmu_region:
  481. iounmap(pxa_unit->mpmu_base);
  482. free_memory:
  483. kfree(pxa_unit);
  484. }
  485. CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init);
  486. CLK_OF_DECLARE(mmp3_clk, "marvell,mmp3-clock", mmp2_clk_init);