clk-mmp2.c 15 KB

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  1. /*
  2. * mmp2 clock framework source file
  3. *
  4. * Copyright (C) 2012 Marvell
  5. * Chao Xie <xiechao.mail@gmail.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/io.h>
  16. #include <linux/delay.h>
  17. #include <linux/err.h>
  18. #include <linux/clk/mmp.h>
  19. #include "clk.h"
  20. #define APBC_RTC 0x0
  21. #define APBC_TWSI0 0x4
  22. #define APBC_TWSI1 0x8
  23. #define APBC_TWSI2 0xc
  24. #define APBC_TWSI3 0x10
  25. #define APBC_TWSI4 0x7c
  26. #define APBC_TWSI5 0x80
  27. #define APBC_KPC 0x18
  28. #define APBC_UART0 0x2c
  29. #define APBC_UART1 0x30
  30. #define APBC_UART2 0x34
  31. #define APBC_UART3 0x88
  32. #define APBC_GPIO 0x38
  33. #define APBC_PWM0 0x3c
  34. #define APBC_PWM1 0x40
  35. #define APBC_PWM2 0x44
  36. #define APBC_PWM3 0x48
  37. #define APBC_SSP0 0x50
  38. #define APBC_SSP1 0x54
  39. #define APBC_SSP2 0x58
  40. #define APBC_SSP3 0x5c
  41. #define APMU_SDH0 0x54
  42. #define APMU_SDH1 0x58
  43. #define APMU_SDH2 0xe8
  44. #define APMU_SDH3 0xec
  45. #define APMU_USB 0x5c
  46. #define APMU_DISP0 0x4c
  47. #define APMU_DISP1 0x110
  48. #define APMU_CCIC0 0x50
  49. #define APMU_CCIC1 0xf4
  50. #define MPMU_UART_PLL 0x14
  51. static DEFINE_SPINLOCK(clk_lock);
  52. static struct mmp_clk_factor_masks uart_factor_masks = {
  53. .factor = 2,
  54. .num_mask = 0x1fff,
  55. .den_mask = 0x1fff,
  56. .num_shift = 16,
  57. .den_shift = 0,
  58. };
  59. static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
  60. {.num = 8125, .den = 1536}, /*14.745MHZ */
  61. {.num = 3521, .den = 689}, /*19.23MHZ */
  62. };
  63. static const char *uart_parent[] = {"uart_pll", "vctcxo"};
  64. static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
  65. static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
  66. static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
  67. static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
  68. void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
  69. phys_addr_t apbc_phys)
  70. {
  71. struct clk *clk;
  72. struct clk *vctcxo;
  73. void __iomem *mpmu_base;
  74. void __iomem *apmu_base;
  75. void __iomem *apbc_base;
  76. mpmu_base = ioremap(mpmu_phys, SZ_4K);
  77. if (!mpmu_base) {
  78. pr_err("error to ioremap MPMU base\n");
  79. return;
  80. }
  81. apmu_base = ioremap(apmu_phys, SZ_4K);
  82. if (!apmu_base) {
  83. pr_err("error to ioremap APMU base\n");
  84. return;
  85. }
  86. apbc_base = ioremap(apbc_phys, SZ_4K);
  87. if (!apbc_base) {
  88. pr_err("error to ioremap APBC base\n");
  89. return;
  90. }
  91. clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
  92. clk_register_clkdev(clk, "clk32", NULL);
  93. vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
  94. clk_register_clkdev(vctcxo, "vctcxo", NULL);
  95. clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000);
  96. clk_register_clkdev(clk, "pll1", NULL);
  97. clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000);
  98. clk_register_clkdev(clk, "usb_pll", NULL);
  99. clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000);
  100. clk_register_clkdev(clk, "pll2", NULL);
  101. clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
  102. CLK_SET_RATE_PARENT, 1, 2);
  103. clk_register_clkdev(clk, "pll1_2", NULL);
  104. clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
  105. CLK_SET_RATE_PARENT, 1, 2);
  106. clk_register_clkdev(clk, "pll1_4", NULL);
  107. clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
  108. CLK_SET_RATE_PARENT, 1, 2);
  109. clk_register_clkdev(clk, "pll1_8", NULL);
  110. clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
  111. CLK_SET_RATE_PARENT, 1, 2);
  112. clk_register_clkdev(clk, "pll1_16", NULL);
  113. clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
  114. CLK_SET_RATE_PARENT, 1, 5);
  115. clk_register_clkdev(clk, "pll1_20", NULL);
  116. clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
  117. CLK_SET_RATE_PARENT, 1, 3);
  118. clk_register_clkdev(clk, "pll1_3", NULL);
  119. clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
  120. CLK_SET_RATE_PARENT, 1, 2);
  121. clk_register_clkdev(clk, "pll1_6", NULL);
  122. clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
  123. CLK_SET_RATE_PARENT, 1, 2);
  124. clk_register_clkdev(clk, "pll1_12", NULL);
  125. clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
  126. CLK_SET_RATE_PARENT, 1, 2);
  127. clk_register_clkdev(clk, "pll2_2", NULL);
  128. clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
  129. CLK_SET_RATE_PARENT, 1, 2);
  130. clk_register_clkdev(clk, "pll2_4", NULL);
  131. clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
  132. CLK_SET_RATE_PARENT, 1, 2);
  133. clk_register_clkdev(clk, "pll2_8", NULL);
  134. clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
  135. CLK_SET_RATE_PARENT, 1, 2);
  136. clk_register_clkdev(clk, "pll2_16", NULL);
  137. clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
  138. CLK_SET_RATE_PARENT, 1, 3);
  139. clk_register_clkdev(clk, "pll2_3", NULL);
  140. clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
  141. CLK_SET_RATE_PARENT, 1, 2);
  142. clk_register_clkdev(clk, "pll2_6", NULL);
  143. clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
  144. CLK_SET_RATE_PARENT, 1, 2);
  145. clk_register_clkdev(clk, "pll2_12", NULL);
  146. clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
  147. CLK_SET_RATE_PARENT, 1, 2);
  148. clk_register_clkdev(clk, "vctcxo_2", NULL);
  149. clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
  150. CLK_SET_RATE_PARENT, 1, 2);
  151. clk_register_clkdev(clk, "vctcxo_4", NULL);
  152. clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
  153. mpmu_base + MPMU_UART_PLL,
  154. &uart_factor_masks, uart_factor_tbl,
  155. ARRAY_SIZE(uart_factor_tbl), &clk_lock);
  156. clk_set_rate(clk, 14745600);
  157. clk_register_clkdev(clk, "uart_pll", NULL);
  158. clk = mmp_clk_register_apbc("twsi0", "vctcxo",
  159. apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
  160. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
  161. clk = mmp_clk_register_apbc("twsi1", "vctcxo",
  162. apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
  163. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
  164. clk = mmp_clk_register_apbc("twsi2", "vctcxo",
  165. apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
  166. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
  167. clk = mmp_clk_register_apbc("twsi3", "vctcxo",
  168. apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
  169. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
  170. clk = mmp_clk_register_apbc("twsi4", "vctcxo",
  171. apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
  172. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
  173. clk = mmp_clk_register_apbc("twsi5", "vctcxo",
  174. apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
  175. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
  176. clk = mmp_clk_register_apbc("gpio", "vctcxo",
  177. apbc_base + APBC_GPIO, 10, 0, &clk_lock);
  178. clk_register_clkdev(clk, NULL, "mmp2-gpio");
  179. clk = mmp_clk_register_apbc("kpc", "clk32",
  180. apbc_base + APBC_KPC, 10, 0, &clk_lock);
  181. clk_register_clkdev(clk, NULL, "pxa27x-keypad");
  182. clk = mmp_clk_register_apbc("rtc", "clk32",
  183. apbc_base + APBC_RTC, 10, 0, &clk_lock);
  184. clk_register_clkdev(clk, NULL, "mmp-rtc");
  185. clk = mmp_clk_register_apbc("pwm0", "vctcxo",
  186. apbc_base + APBC_PWM0, 10, 0, &clk_lock);
  187. clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
  188. clk = mmp_clk_register_apbc("pwm1", "vctcxo",
  189. apbc_base + APBC_PWM1, 10, 0, &clk_lock);
  190. clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
  191. clk = mmp_clk_register_apbc("pwm2", "vctcxo",
  192. apbc_base + APBC_PWM2, 10, 0, &clk_lock);
  193. clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
  194. clk = mmp_clk_register_apbc("pwm3", "vctcxo",
  195. apbc_base + APBC_PWM3, 10, 0, &clk_lock);
  196. clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
  197. clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
  198. ARRAY_SIZE(uart_parent),
  199. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  200. apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
  201. clk_set_parent(clk, vctcxo);
  202. clk_register_clkdev(clk, "uart_mux.0", NULL);
  203. clk = mmp_clk_register_apbc("uart0", "uart0_mux",
  204. apbc_base + APBC_UART0, 10, 0, &clk_lock);
  205. clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
  206. clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
  207. ARRAY_SIZE(uart_parent),
  208. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  209. apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
  210. clk_set_parent(clk, vctcxo);
  211. clk_register_clkdev(clk, "uart_mux.1", NULL);
  212. clk = mmp_clk_register_apbc("uart1", "uart1_mux",
  213. apbc_base + APBC_UART1, 10, 0, &clk_lock);
  214. clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
  215. clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
  216. ARRAY_SIZE(uart_parent),
  217. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  218. apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
  219. clk_set_parent(clk, vctcxo);
  220. clk_register_clkdev(clk, "uart_mux.2", NULL);
  221. clk = mmp_clk_register_apbc("uart2", "uart2_mux",
  222. apbc_base + APBC_UART2, 10, 0, &clk_lock);
  223. clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
  224. clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
  225. ARRAY_SIZE(uart_parent),
  226. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  227. apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
  228. clk_set_parent(clk, vctcxo);
  229. clk_register_clkdev(clk, "uart_mux.3", NULL);
  230. clk = mmp_clk_register_apbc("uart3", "uart3_mux",
  231. apbc_base + APBC_UART3, 10, 0, &clk_lock);
  232. clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
  233. clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
  234. ARRAY_SIZE(ssp_parent),
  235. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  236. apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
  237. clk_register_clkdev(clk, "uart_mux.0", NULL);
  238. clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
  239. apbc_base + APBC_SSP0, 10, 0, &clk_lock);
  240. clk_register_clkdev(clk, NULL, "mmp-ssp.0");
  241. clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
  242. ARRAY_SIZE(ssp_parent),
  243. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  244. apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
  245. clk_register_clkdev(clk, "ssp_mux.1", NULL);
  246. clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
  247. apbc_base + APBC_SSP1, 10, 0, &clk_lock);
  248. clk_register_clkdev(clk, NULL, "mmp-ssp.1");
  249. clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
  250. ARRAY_SIZE(ssp_parent),
  251. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  252. apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
  253. clk_register_clkdev(clk, "ssp_mux.2", NULL);
  254. clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
  255. apbc_base + APBC_SSP2, 10, 0, &clk_lock);
  256. clk_register_clkdev(clk, NULL, "mmp-ssp.2");
  257. clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
  258. ARRAY_SIZE(ssp_parent),
  259. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  260. apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
  261. clk_register_clkdev(clk, "ssp_mux.3", NULL);
  262. clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
  263. apbc_base + APBC_SSP3, 10, 0, &clk_lock);
  264. clk_register_clkdev(clk, NULL, "mmp-ssp.3");
  265. clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
  266. ARRAY_SIZE(sdh_parent),
  267. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  268. apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
  269. clk_register_clkdev(clk, "sdh_mux", NULL);
  270. clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
  271. CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
  272. 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
  273. clk_register_clkdev(clk, "sdh_div", NULL);
  274. clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
  275. 0x1b, &clk_lock);
  276. clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
  277. clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
  278. 0x1b, &clk_lock);
  279. clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
  280. clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
  281. 0x1b, &clk_lock);
  282. clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
  283. clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
  284. 0x1b, &clk_lock);
  285. clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
  286. clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
  287. 0x9, &clk_lock);
  288. clk_register_clkdev(clk, "usb_clk", NULL);
  289. clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
  290. ARRAY_SIZE(disp_parent),
  291. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  292. apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
  293. clk_register_clkdev(clk, "disp_mux.0", NULL);
  294. clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
  295. CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
  296. 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
  297. clk_register_clkdev(clk, "disp_div.0", NULL);
  298. clk = mmp_clk_register_apmu("disp0", "disp0_div",
  299. apmu_base + APMU_DISP0, 0x1b, &clk_lock);
  300. clk_register_clkdev(clk, NULL, "mmp-disp.0");
  301. clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
  302. apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
  303. clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
  304. clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
  305. apmu_base + APMU_DISP0, 0x1024, &clk_lock);
  306. clk_register_clkdev(clk, "disp_sphy.0", NULL);
  307. clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
  308. ARRAY_SIZE(disp_parent),
  309. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  310. apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
  311. clk_register_clkdev(clk, "disp_mux.1", NULL);
  312. clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
  313. CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
  314. 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
  315. clk_register_clkdev(clk, "disp_div.1", NULL);
  316. clk = mmp_clk_register_apmu("disp1", "disp1_div",
  317. apmu_base + APMU_DISP1, 0x1b, &clk_lock);
  318. clk_register_clkdev(clk, NULL, "mmp-disp.1");
  319. clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
  320. apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
  321. clk_register_clkdev(clk, "ccic_arbiter", NULL);
  322. clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
  323. ARRAY_SIZE(ccic_parent),
  324. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  325. apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
  326. clk_register_clkdev(clk, "ccic_mux.0", NULL);
  327. clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
  328. CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
  329. 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
  330. clk_register_clkdev(clk, "ccic_div.0", NULL);
  331. clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
  332. apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
  333. clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
  334. clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
  335. apmu_base + APMU_CCIC0, 0x24, &clk_lock);
  336. clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
  337. clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
  338. CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
  339. 10, 5, 0, &clk_lock);
  340. clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
  341. clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
  342. apmu_base + APMU_CCIC0, 0x300, &clk_lock);
  343. clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
  344. clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
  345. ARRAY_SIZE(ccic_parent),
  346. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  347. apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
  348. clk_register_clkdev(clk, "ccic_mux.1", NULL);
  349. clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
  350. CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
  351. 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
  352. clk_register_clkdev(clk, "ccic_div.1", NULL);
  353. clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
  354. apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
  355. clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
  356. clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
  357. apmu_base + APMU_CCIC1, 0x24, &clk_lock);
  358. clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
  359. clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
  360. CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
  361. 10, 5, 0, &clk_lock);
  362. clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
  363. clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
  364. apmu_base + APMU_CCIC1, 0x300, &clk_lock);
  365. clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
  366. }