clk-audio.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * MMP Audio Clock Controller driver
  4. *
  5. * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pm_clock.h>
  12. #include <linux/pm_runtime.h>
  13. #include <linux/slab.h>
  14. #include <dt-bindings/clock/marvell,mmp2-audio.h>
  15. /* Audio Controller Registers */
  16. #define SSPA_AUD_CTRL 0x04
  17. #define SSPA_AUD_PLL_CTRL0 0x08
  18. #define SSPA_AUD_PLL_CTRL1 0x0c
  19. /* SSPA Audio Control Register */
  20. #define SSPA_AUD_CTRL_SYSCLK_SHIFT 0
  21. #define SSPA_AUD_CTRL_SYSCLK_DIV_SHIFT 1
  22. #define SSPA_AUD_CTRL_SSPA0_MUX_SHIFT 7
  23. #define SSPA_AUD_CTRL_SSPA0_SHIFT 8
  24. #define SSPA_AUD_CTRL_SSPA0_DIV_SHIFT 9
  25. #define SSPA_AUD_CTRL_SSPA1_SHIFT 16
  26. #define SSPA_AUD_CTRL_SSPA1_DIV_SHIFT 17
  27. #define SSPA_AUD_CTRL_SSPA1_MUX_SHIFT 23
  28. #define SSPA_AUD_CTRL_DIV_MASK 0x7e
  29. /* SSPA Audio PLL Control 0 Register */
  30. #define SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO_MASK (0x7 << 28)
  31. #define SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(x) ((x) << 28)
  32. #define SSPA_AUD_PLL_CTRL0_FRACT_MASK (0xfffff << 8)
  33. #define SSPA_AUD_PLL_CTRL0_FRACT(x) ((x) << 8)
  34. #define SSPA_AUD_PLL_CTRL0_ENA_DITHER (1 << 7)
  35. #define SSPA_AUD_PLL_CTRL0_ICP_2UA (0 << 5)
  36. #define SSPA_AUD_PLL_CTRL0_ICP_5UA (1 << 5)
  37. #define SSPA_AUD_PLL_CTRL0_ICP_7UA (2 << 5)
  38. #define SSPA_AUD_PLL_CTRL0_ICP_10UA (3 << 5)
  39. #define SSPA_AUD_PLL_CTRL0_DIV_FBCCLK_MASK (0x3 << 3)
  40. #define SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(x) ((x) << 3)
  41. #define SSPA_AUD_PLL_CTRL0_DIV_MCLK_MASK (0x1 << 2)
  42. #define SSPA_AUD_PLL_CTRL0_DIV_MCLK(x) ((x) << 2)
  43. #define SSPA_AUD_PLL_CTRL0_PD_OVPROT_DIS (1 << 1)
  44. #define SSPA_AUD_PLL_CTRL0_PU (1 << 0)
  45. /* SSPA Audio PLL Control 1 Register */
  46. #define SSPA_AUD_PLL_CTRL1_SEL_FAST_CLK (1 << 24)
  47. #define SSPA_AUD_PLL_CTRL1_CLK_SEL_MASK (1 << 11)
  48. #define SSPA_AUD_PLL_CTRL1_CLK_SEL_AUDIO_PLL (1 << 11)
  49. #define SSPA_AUD_PLL_CTRL1_CLK_SEL_VCXO (0 << 11)
  50. #define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN_MASK (0x7ff << 0)
  51. #define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(x) ((x) << 0)
  52. struct mmp2_audio_clk {
  53. void __iomem *mmio_base;
  54. struct clk_hw audio_pll_hw;
  55. struct clk_mux sspa_mux;
  56. struct clk_mux sspa1_mux;
  57. struct clk_divider sysclk_div;
  58. struct clk_divider sspa0_div;
  59. struct clk_divider sspa1_div;
  60. struct clk_gate sysclk_gate;
  61. struct clk_gate sspa0_gate;
  62. struct clk_gate sspa1_gate;
  63. u32 aud_ctrl;
  64. u32 aud_pll_ctrl0;
  65. u32 aud_pll_ctrl1;
  66. spinlock_t lock;
  67. /* Must be last */
  68. struct clk_hw_onecell_data clk_data;
  69. };
  70. static const struct {
  71. unsigned long parent_rate;
  72. unsigned long freq_vco;
  73. unsigned char mclk;
  74. unsigned char fbcclk;
  75. unsigned short fract;
  76. } predivs[] = {
  77. { 26000000, 135475200, 0, 0, 0x8a18 },
  78. { 26000000, 147456000, 0, 1, 0x0da1 },
  79. { 38400000, 135475200, 1, 2, 0x8208 },
  80. { 38400000, 147456000, 1, 3, 0xaaaa },
  81. };
  82. static const struct {
  83. unsigned char divisor;
  84. unsigned char modulo;
  85. unsigned char pattern;
  86. } postdivs[] = {
  87. { 1, 3, 0, },
  88. { 2, 5, 0, },
  89. { 4, 0, 0, },
  90. { 6, 1, 1, },
  91. { 8, 1, 0, },
  92. { 9, 1, 2, },
  93. { 12, 2, 1, },
  94. { 16, 2, 0, },
  95. { 18, 2, 2, },
  96. { 24, 4, 1, },
  97. { 36, 4, 2, },
  98. { 48, 6, 1, },
  99. { 72, 6, 2, },
  100. };
  101. static unsigned long audio_pll_recalc_rate(struct clk_hw *hw,
  102. unsigned long parent_rate)
  103. {
  104. struct mmp2_audio_clk *priv = container_of(hw, struct mmp2_audio_clk, audio_pll_hw);
  105. unsigned int prediv;
  106. unsigned int postdiv;
  107. u32 aud_pll_ctrl0;
  108. u32 aud_pll_ctrl1;
  109. aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0);
  110. aud_pll_ctrl0 &= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO_MASK |
  111. SSPA_AUD_PLL_CTRL0_FRACT_MASK |
  112. SSPA_AUD_PLL_CTRL0_ENA_DITHER |
  113. SSPA_AUD_PLL_CTRL0_DIV_FBCCLK_MASK |
  114. SSPA_AUD_PLL_CTRL0_DIV_MCLK_MASK |
  115. SSPA_AUD_PLL_CTRL0_PU;
  116. aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1);
  117. aud_pll_ctrl1 &= SSPA_AUD_PLL_CTRL1_CLK_SEL_MASK |
  118. SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN_MASK;
  119. for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) {
  120. if (predivs[prediv].parent_rate != parent_rate)
  121. continue;
  122. for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
  123. unsigned long freq;
  124. u32 val;
  125. val = SSPA_AUD_PLL_CTRL0_ENA_DITHER;
  126. val |= SSPA_AUD_PLL_CTRL0_PU;
  127. val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo);
  128. val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract);
  129. val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk);
  130. val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk);
  131. if (val != aud_pll_ctrl0)
  132. continue;
  133. val = SSPA_AUD_PLL_CTRL1_CLK_SEL_AUDIO_PLL;
  134. val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern);
  135. if (val != aud_pll_ctrl1)
  136. continue;
  137. freq = predivs[prediv].freq_vco;
  138. freq /= postdivs[postdiv].divisor;
  139. return freq;
  140. }
  141. }
  142. return 0;
  143. }
  144. static long audio_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  145. unsigned long *parent_rate)
  146. {
  147. unsigned int prediv;
  148. unsigned int postdiv;
  149. long rounded = 0;
  150. for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) {
  151. if (predivs[prediv].parent_rate != *parent_rate)
  152. continue;
  153. for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
  154. long freq = predivs[prediv].freq_vco;
  155. freq /= postdivs[postdiv].divisor;
  156. if (freq == rate)
  157. return rate;
  158. if (freq < rate)
  159. continue;
  160. if (rounded && freq > rounded)
  161. continue;
  162. rounded = freq;
  163. }
  164. }
  165. return rounded;
  166. }
  167. static int audio_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  168. unsigned long parent_rate)
  169. {
  170. struct mmp2_audio_clk *priv = container_of(hw, struct mmp2_audio_clk, audio_pll_hw);
  171. unsigned int prediv;
  172. unsigned int postdiv;
  173. unsigned long val;
  174. for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) {
  175. if (predivs[prediv].parent_rate != parent_rate)
  176. continue;
  177. for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
  178. if (rate * postdivs[postdiv].divisor != predivs[prediv].freq_vco)
  179. continue;
  180. val = SSPA_AUD_PLL_CTRL0_ENA_DITHER;
  181. val |= SSPA_AUD_PLL_CTRL0_PU;
  182. val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo);
  183. val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract);
  184. val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk);
  185. val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk);
  186. writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0);
  187. val = SSPA_AUD_PLL_CTRL1_CLK_SEL_AUDIO_PLL;
  188. val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern);
  189. writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1);
  190. return 0;
  191. }
  192. }
  193. return -ERANGE;
  194. }
  195. static const struct clk_ops audio_pll_ops = {
  196. .recalc_rate = audio_pll_recalc_rate,
  197. .round_rate = audio_pll_round_rate,
  198. .set_rate = audio_pll_set_rate,
  199. };
  200. static int register_clocks(struct mmp2_audio_clk *priv, struct device *dev)
  201. {
  202. const struct clk_parent_data sspa_mux_parents[] = {
  203. { .hw = &priv->audio_pll_hw },
  204. { .fw_name = "i2s0" },
  205. };
  206. const struct clk_parent_data sspa1_mux_parents[] = {
  207. { .hw = &priv->audio_pll_hw },
  208. { .fw_name = "i2s1" },
  209. };
  210. int ret;
  211. priv->audio_pll_hw.init = CLK_HW_INIT_FW_NAME("audio_pll",
  212. "vctcxo", &audio_pll_ops,
  213. CLK_SET_RATE_PARENT);
  214. ret = devm_clk_hw_register(dev, &priv->audio_pll_hw);
  215. if (ret)
  216. return ret;
  217. priv->sspa_mux.hw.init = CLK_HW_INIT_PARENTS_DATA("sspa_mux",
  218. sspa_mux_parents, &clk_mux_ops,
  219. CLK_SET_RATE_PARENT);
  220. priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL;
  221. priv->sspa_mux.mask = 1;
  222. priv->sspa_mux.shift = SSPA_AUD_CTRL_SSPA0_MUX_SHIFT;
  223. ret = devm_clk_hw_register(dev, &priv->sspa_mux.hw);
  224. if (ret)
  225. return ret;
  226. priv->sysclk_div.hw.init = CLK_HW_INIT_HW("sys_div",
  227. &priv->sspa_mux.hw, &clk_divider_ops,
  228. CLK_SET_RATE_PARENT);
  229. priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
  230. priv->sysclk_div.shift = SSPA_AUD_CTRL_SYSCLK_DIV_SHIFT;
  231. priv->sysclk_div.width = 6;
  232. priv->sysclk_div.flags = CLK_DIVIDER_ONE_BASED;
  233. priv->sysclk_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
  234. priv->sysclk_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
  235. ret = devm_clk_hw_register(dev, &priv->sysclk_div.hw);
  236. if (ret)
  237. return ret;
  238. priv->sysclk_gate.hw.init = CLK_HW_INIT_HW("sys_clk",
  239. &priv->sysclk_div.hw, &clk_gate_ops,
  240. CLK_SET_RATE_PARENT);
  241. priv->sysclk_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
  242. priv->sysclk_gate.bit_idx = SSPA_AUD_CTRL_SYSCLK_SHIFT;
  243. ret = devm_clk_hw_register(dev, &priv->sysclk_gate.hw);
  244. if (ret)
  245. return ret;
  246. priv->sspa0_div.hw.init = CLK_HW_INIT_HW("sspa0_div",
  247. &priv->sspa_mux.hw, &clk_divider_ops, 0);
  248. priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
  249. priv->sspa0_div.shift = SSPA_AUD_CTRL_SSPA0_DIV_SHIFT;
  250. priv->sspa0_div.width = 6;
  251. priv->sspa0_div.flags = CLK_DIVIDER_ONE_BASED;
  252. priv->sspa0_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
  253. priv->sspa0_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
  254. ret = devm_clk_hw_register(dev, &priv->sspa0_div.hw);
  255. if (ret)
  256. return ret;
  257. priv->sspa0_gate.hw.init = CLK_HW_INIT_HW("sspa0_clk",
  258. &priv->sspa0_div.hw, &clk_gate_ops,
  259. CLK_SET_RATE_PARENT);
  260. priv->sspa0_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
  261. priv->sspa0_gate.bit_idx = SSPA_AUD_CTRL_SSPA0_SHIFT;
  262. ret = devm_clk_hw_register(dev, &priv->sspa0_gate.hw);
  263. if (ret)
  264. return ret;
  265. priv->sspa1_mux.hw.init = CLK_HW_INIT_PARENTS_DATA("sspa1_mux",
  266. sspa1_mux_parents, &clk_mux_ops,
  267. CLK_SET_RATE_PARENT);
  268. priv->sspa1_mux.reg = priv->mmio_base + SSPA_AUD_CTRL;
  269. priv->sspa1_mux.mask = 1;
  270. priv->sspa1_mux.shift = SSPA_AUD_CTRL_SSPA1_MUX_SHIFT;
  271. ret = devm_clk_hw_register(dev, &priv->sspa1_mux.hw);
  272. if (ret)
  273. return ret;
  274. priv->sspa1_div.hw.init = CLK_HW_INIT_HW("sspa1_div",
  275. &priv->sspa1_mux.hw, &clk_divider_ops, 0);
  276. priv->sspa1_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
  277. priv->sspa1_div.shift = SSPA_AUD_CTRL_SSPA1_DIV_SHIFT;
  278. priv->sspa1_div.width = 6;
  279. priv->sspa1_div.flags = CLK_DIVIDER_ONE_BASED;
  280. priv->sspa1_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
  281. priv->sspa1_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
  282. ret = devm_clk_hw_register(dev, &priv->sspa1_div.hw);
  283. if (ret)
  284. return ret;
  285. priv->sspa1_gate.hw.init = CLK_HW_INIT_HW("sspa1_clk",
  286. &priv->sspa1_div.hw, &clk_gate_ops,
  287. CLK_SET_RATE_PARENT);
  288. priv->sspa1_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
  289. priv->sspa1_gate.bit_idx = SSPA_AUD_CTRL_SSPA1_SHIFT;
  290. ret = devm_clk_hw_register(dev, &priv->sspa1_gate.hw);
  291. if (ret)
  292. return ret;
  293. priv->clk_data.hws[MMP2_CLK_AUDIO_SYSCLK] = &priv->sysclk_gate.hw;
  294. priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA0] = &priv->sspa0_gate.hw;
  295. priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA1] = &priv->sspa1_gate.hw;
  296. priv->clk_data.num = MMP2_CLK_AUDIO_NR_CLKS;
  297. return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
  298. &priv->clk_data);
  299. }
  300. static int mmp2_audio_clk_probe(struct platform_device *pdev)
  301. {
  302. struct mmp2_audio_clk *priv;
  303. int ret;
  304. priv = devm_kzalloc(&pdev->dev,
  305. struct_size(priv, clk_data.hws,
  306. MMP2_CLK_AUDIO_NR_CLKS),
  307. GFP_KERNEL);
  308. if (!priv)
  309. return -ENOMEM;
  310. spin_lock_init(&priv->lock);
  311. platform_set_drvdata(pdev, priv);
  312. priv->mmio_base = devm_platform_ioremap_resource(pdev, 0);
  313. if (IS_ERR(priv->mmio_base))
  314. return PTR_ERR(priv->mmio_base);
  315. pm_runtime_enable(&pdev->dev);
  316. ret = pm_clk_create(&pdev->dev);
  317. if (ret)
  318. goto disable_pm_runtime;
  319. ret = pm_clk_add(&pdev->dev, "audio");
  320. if (ret)
  321. goto destroy_pm_clk;
  322. ret = register_clocks(priv, &pdev->dev);
  323. if (ret)
  324. goto destroy_pm_clk;
  325. return 0;
  326. destroy_pm_clk:
  327. pm_clk_destroy(&pdev->dev);
  328. disable_pm_runtime:
  329. pm_runtime_disable(&pdev->dev);
  330. return ret;
  331. }
  332. static int mmp2_audio_clk_remove(struct platform_device *pdev)
  333. {
  334. pm_clk_destroy(&pdev->dev);
  335. pm_runtime_disable(&pdev->dev);
  336. return 0;
  337. }
  338. #ifdef CONFIG_PM
  339. static int mmp2_audio_clk_suspend(struct device *dev)
  340. {
  341. struct mmp2_audio_clk *priv = dev_get_drvdata(dev);
  342. priv->aud_ctrl = readl(priv->mmio_base + SSPA_AUD_CTRL);
  343. priv->aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0);
  344. priv->aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1);
  345. pm_clk_suspend(dev);
  346. return 0;
  347. }
  348. static int mmp2_audio_clk_resume(struct device *dev)
  349. {
  350. struct mmp2_audio_clk *priv = dev_get_drvdata(dev);
  351. pm_clk_resume(dev);
  352. writel(priv->aud_ctrl, priv->mmio_base + SSPA_AUD_CTRL);
  353. writel(priv->aud_pll_ctrl0, priv->mmio_base + SSPA_AUD_PLL_CTRL0);
  354. writel(priv->aud_pll_ctrl1, priv->mmio_base + SSPA_AUD_PLL_CTRL1);
  355. return 0;
  356. }
  357. #endif
  358. static const struct dev_pm_ops mmp2_audio_clk_pm_ops = {
  359. SET_RUNTIME_PM_OPS(mmp2_audio_clk_suspend, mmp2_audio_clk_resume, NULL)
  360. };
  361. static const struct of_device_id mmp2_audio_clk_of_match[] = {
  362. { .compatible = "marvell,mmp2-audio-clock" },
  363. {}
  364. };
  365. MODULE_DEVICE_TABLE(of, mmp2_audio_clk_of_match);
  366. static struct platform_driver mmp2_audio_clk_driver = {
  367. .driver = {
  368. .name = "mmp2-audio-clock",
  369. .of_match_table = of_match_ptr(mmp2_audio_clk_of_match),
  370. .pm = &mmp2_audio_clk_pm_ops,
  371. },
  372. .probe = mmp2_audio_clk_probe,
  373. .remove = mmp2_audio_clk_remove,
  374. };
  375. module_platform_driver(mmp2_audio_clk_driver);
  376. MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
  377. MODULE_DESCRIPTION("Clock driver for MMP2 Audio subsystem");
  378. MODULE_LICENSE("GPL");