clk-stm32mp1.c 54 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
  4. * Author: Olivier Bideau <olivier.bideau@st.com> for STMicroelectronics.
  5. * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/delay.h>
  10. #include <linux/err.h>
  11. #include <linux/io.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include <linux/slab.h>
  15. #include <linux/spinlock.h>
  16. #include <dt-bindings/clock/stm32mp1-clks.h>
  17. static DEFINE_SPINLOCK(rlock);
  18. #define RCC_OCENSETR 0x0C
  19. #define RCC_HSICFGR 0x18
  20. #define RCC_RDLSICR 0x144
  21. #define RCC_PLL1CR 0x80
  22. #define RCC_PLL1CFGR1 0x84
  23. #define RCC_PLL1CFGR2 0x88
  24. #define RCC_PLL2CR 0x94
  25. #define RCC_PLL2CFGR1 0x98
  26. #define RCC_PLL2CFGR2 0x9C
  27. #define RCC_PLL3CR 0x880
  28. #define RCC_PLL3CFGR1 0x884
  29. #define RCC_PLL3CFGR2 0x888
  30. #define RCC_PLL4CR 0x894
  31. #define RCC_PLL4CFGR1 0x898
  32. #define RCC_PLL4CFGR2 0x89C
  33. #define RCC_APB1ENSETR 0xA00
  34. #define RCC_APB2ENSETR 0xA08
  35. #define RCC_APB3ENSETR 0xA10
  36. #define RCC_APB4ENSETR 0x200
  37. #define RCC_APB5ENSETR 0x208
  38. #define RCC_AHB2ENSETR 0xA18
  39. #define RCC_AHB3ENSETR 0xA20
  40. #define RCC_AHB4ENSETR 0xA28
  41. #define RCC_AHB5ENSETR 0x210
  42. #define RCC_AHB6ENSETR 0x218
  43. #define RCC_AHB6LPENSETR 0x318
  44. #define RCC_RCK12SELR 0x28
  45. #define RCC_RCK3SELR 0x820
  46. #define RCC_RCK4SELR 0x824
  47. #define RCC_MPCKSELR 0x20
  48. #define RCC_ASSCKSELR 0x24
  49. #define RCC_MSSCKSELR 0x48
  50. #define RCC_SPI6CKSELR 0xC4
  51. #define RCC_SDMMC12CKSELR 0x8F4
  52. #define RCC_SDMMC3CKSELR 0x8F8
  53. #define RCC_FMCCKSELR 0x904
  54. #define RCC_I2C46CKSELR 0xC0
  55. #define RCC_I2C12CKSELR 0x8C0
  56. #define RCC_I2C35CKSELR 0x8C4
  57. #define RCC_UART1CKSELR 0xC8
  58. #define RCC_QSPICKSELR 0x900
  59. #define RCC_ETHCKSELR 0x8FC
  60. #define RCC_RNG1CKSELR 0xCC
  61. #define RCC_RNG2CKSELR 0x920
  62. #define RCC_GPUCKSELR 0x938
  63. #define RCC_USBCKSELR 0x91C
  64. #define RCC_STGENCKSELR 0xD4
  65. #define RCC_SPDIFCKSELR 0x914
  66. #define RCC_SPI2S1CKSELR 0x8D8
  67. #define RCC_SPI2S23CKSELR 0x8DC
  68. #define RCC_SPI2S45CKSELR 0x8E0
  69. #define RCC_CECCKSELR 0x918
  70. #define RCC_LPTIM1CKSELR 0x934
  71. #define RCC_LPTIM23CKSELR 0x930
  72. #define RCC_LPTIM45CKSELR 0x92C
  73. #define RCC_UART24CKSELR 0x8E8
  74. #define RCC_UART35CKSELR 0x8EC
  75. #define RCC_UART6CKSELR 0x8E4
  76. #define RCC_UART78CKSELR 0x8F0
  77. #define RCC_FDCANCKSELR 0x90C
  78. #define RCC_SAI1CKSELR 0x8C8
  79. #define RCC_SAI2CKSELR 0x8CC
  80. #define RCC_SAI3CKSELR 0x8D0
  81. #define RCC_SAI4CKSELR 0x8D4
  82. #define RCC_ADCCKSELR 0x928
  83. #define RCC_MPCKDIVR 0x2C
  84. #define RCC_DSICKSELR 0x924
  85. #define RCC_CPERCKSELR 0xD0
  86. #define RCC_MCO1CFGR 0x800
  87. #define RCC_MCO2CFGR 0x804
  88. #define RCC_BDCR 0x140
  89. #define RCC_AXIDIVR 0x30
  90. #define RCC_MCUDIVR 0x830
  91. #define RCC_APB1DIVR 0x834
  92. #define RCC_APB2DIVR 0x838
  93. #define RCC_APB3DIVR 0x83C
  94. #define RCC_APB4DIVR 0x3C
  95. #define RCC_APB5DIVR 0x40
  96. #define RCC_TIMG1PRER 0x828
  97. #define RCC_TIMG2PRER 0x82C
  98. #define RCC_RTCDIVR 0x44
  99. #define RCC_DBGCFGR 0x80C
  100. #define RCC_CLR 0x4
  101. static const char * const ref12_parents[] = {
  102. "ck_hsi", "ck_hse"
  103. };
  104. static const char * const ref3_parents[] = {
  105. "ck_hsi", "ck_hse", "ck_csi"
  106. };
  107. static const char * const ref4_parents[] = {
  108. "ck_hsi", "ck_hse", "ck_csi"
  109. };
  110. static const char * const cpu_src[] = {
  111. "ck_hsi", "ck_hse", "pll1_p"
  112. };
  113. static const char * const axi_src[] = {
  114. "ck_hsi", "ck_hse", "pll2_p"
  115. };
  116. static const char * const per_src[] = {
  117. "ck_hsi", "ck_csi", "ck_hse"
  118. };
  119. static const char * const mcu_src[] = {
  120. "ck_hsi", "ck_hse", "ck_csi", "pll3_p"
  121. };
  122. static const char * const sdmmc12_src[] = {
  123. "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
  124. };
  125. static const char * const sdmmc3_src[] = {
  126. "ck_mcu", "pll3_r", "pll4_p", "ck_hsi"
  127. };
  128. static const char * const fmc_src[] = {
  129. "ck_axi", "pll3_r", "pll4_p", "ck_per"
  130. };
  131. static const char * const qspi_src[] = {
  132. "ck_axi", "pll3_r", "pll4_p", "ck_per"
  133. };
  134. static const char * const eth_src[] = {
  135. "pll4_p", "pll3_q"
  136. };
  137. static const char * const rng_src[] = {
  138. "ck_csi", "pll4_r", "ck_lse", "ck_lsi"
  139. };
  140. static const char * const usbphy_src[] = {
  141. "ck_hse", "pll4_r", "clk-hse-div2"
  142. };
  143. static const char * const usbo_src[] = {
  144. "pll4_r", "ck_usbo_48m"
  145. };
  146. static const char * const stgen_src[] = {
  147. "ck_hsi", "ck_hse"
  148. };
  149. static const char * const spdif_src[] = {
  150. "pll4_p", "pll3_q", "ck_hsi"
  151. };
  152. static const char * const spi123_src[] = {
  153. "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
  154. };
  155. static const char * const spi45_src[] = {
  156. "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
  157. };
  158. static const char * const spi6_src[] = {
  159. "pclk5", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "pll3_q"
  160. };
  161. static const char * const cec_src[] = {
  162. "ck_lse", "ck_lsi", "ck_csi"
  163. };
  164. static const char * const i2c12_src[] = {
  165. "pclk1", "pll4_r", "ck_hsi", "ck_csi"
  166. };
  167. static const char * const i2c35_src[] = {
  168. "pclk1", "pll4_r", "ck_hsi", "ck_csi"
  169. };
  170. static const char * const i2c46_src[] = {
  171. "pclk5", "pll3_q", "ck_hsi", "ck_csi"
  172. };
  173. static const char * const lptim1_src[] = {
  174. "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
  175. };
  176. static const char * const lptim23_src[] = {
  177. "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
  178. };
  179. static const char * const lptim45_src[] = {
  180. "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
  181. };
  182. static const char * const usart1_src[] = {
  183. "pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
  184. };
  185. static const char * const usart234578_src[] = {
  186. "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
  187. };
  188. static const char * const usart6_src[] = {
  189. "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
  190. };
  191. static const char * const fdcan_src[] = {
  192. "ck_hse", "pll3_q", "pll4_q", "pll4_r"
  193. };
  194. static const char * const sai_src[] = {
  195. "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
  196. };
  197. static const char * const sai2_src[] = {
  198. "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
  199. };
  200. static const char * const adc12_src[] = {
  201. "pll4_r", "ck_per", "pll3_q"
  202. };
  203. static const char * const dsi_src[] = {
  204. "ck_dsi_phy", "pll4_p"
  205. };
  206. static const char * const rtc_src[] = {
  207. "off", "ck_lse", "ck_lsi", "ck_hse_rtc"
  208. };
  209. static const char * const mco1_src[] = {
  210. "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
  211. };
  212. static const char * const mco2_src[] = {
  213. "ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"
  214. };
  215. static const char * const ck_trace_src[] = {
  216. "ck_axi"
  217. };
  218. static const struct clk_div_table axi_div_table[] = {
  219. { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
  220. { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
  221. { 0 },
  222. };
  223. static const struct clk_div_table mcu_div_table[] = {
  224. { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
  225. { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
  226. { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
  227. { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
  228. { 0 },
  229. };
  230. static const struct clk_div_table apb_div_table[] = {
  231. { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
  232. { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
  233. { 0 },
  234. };
  235. static const struct clk_div_table ck_trace_div_table[] = {
  236. { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
  237. { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
  238. { 0 },
  239. };
  240. #define MAX_MUX_CLK 2
  241. struct stm32_mmux {
  242. u8 nbr_clk;
  243. struct clk_hw *hws[MAX_MUX_CLK];
  244. };
  245. struct stm32_clk_mmux {
  246. struct clk_mux mux;
  247. struct stm32_mmux *mmux;
  248. };
  249. struct stm32_mgate {
  250. u8 nbr_clk;
  251. u32 flag;
  252. };
  253. struct stm32_clk_mgate {
  254. struct clk_gate gate;
  255. struct stm32_mgate *mgate;
  256. u32 mask;
  257. };
  258. struct clock_config {
  259. u32 id;
  260. const char *name;
  261. const char *parent_name;
  262. const char * const *parent_names;
  263. int num_parents;
  264. unsigned long flags;
  265. void *cfg;
  266. struct clk_hw * (*func)(struct device *dev,
  267. struct clk_hw_onecell_data *clk_data,
  268. void __iomem *base, spinlock_t *lock,
  269. const struct clock_config *cfg);
  270. };
  271. #define NO_ID ~0
  272. struct gate_cfg {
  273. u32 reg_off;
  274. u8 bit_idx;
  275. u8 gate_flags;
  276. };
  277. struct fixed_factor_cfg {
  278. unsigned int mult;
  279. unsigned int div;
  280. };
  281. struct div_cfg {
  282. u32 reg_off;
  283. u8 shift;
  284. u8 width;
  285. u8 div_flags;
  286. const struct clk_div_table *table;
  287. };
  288. struct mux_cfg {
  289. u32 reg_off;
  290. u8 shift;
  291. u8 width;
  292. u8 mux_flags;
  293. u32 *table;
  294. };
  295. struct stm32_gate_cfg {
  296. struct gate_cfg *gate;
  297. struct stm32_mgate *mgate;
  298. const struct clk_ops *ops;
  299. };
  300. struct stm32_div_cfg {
  301. struct div_cfg *div;
  302. const struct clk_ops *ops;
  303. };
  304. struct stm32_mux_cfg {
  305. struct mux_cfg *mux;
  306. struct stm32_mmux *mmux;
  307. const struct clk_ops *ops;
  308. };
  309. /* STM32 Composite clock */
  310. struct stm32_composite_cfg {
  311. const struct stm32_gate_cfg *gate;
  312. const struct stm32_div_cfg *div;
  313. const struct stm32_mux_cfg *mux;
  314. };
  315. static struct clk_hw *
  316. _clk_hw_register_gate(struct device *dev,
  317. struct clk_hw_onecell_data *clk_data,
  318. void __iomem *base, spinlock_t *lock,
  319. const struct clock_config *cfg)
  320. {
  321. struct gate_cfg *gate_cfg = cfg->cfg;
  322. return clk_hw_register_gate(dev,
  323. cfg->name,
  324. cfg->parent_name,
  325. cfg->flags,
  326. gate_cfg->reg_off + base,
  327. gate_cfg->bit_idx,
  328. gate_cfg->gate_flags,
  329. lock);
  330. }
  331. static struct clk_hw *
  332. _clk_hw_register_fixed_factor(struct device *dev,
  333. struct clk_hw_onecell_data *clk_data,
  334. void __iomem *base, spinlock_t *lock,
  335. const struct clock_config *cfg)
  336. {
  337. struct fixed_factor_cfg *ff_cfg = cfg->cfg;
  338. return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name,
  339. cfg->flags, ff_cfg->mult,
  340. ff_cfg->div);
  341. }
  342. static struct clk_hw *
  343. _clk_hw_register_divider_table(struct device *dev,
  344. struct clk_hw_onecell_data *clk_data,
  345. void __iomem *base, spinlock_t *lock,
  346. const struct clock_config *cfg)
  347. {
  348. struct div_cfg *div_cfg = cfg->cfg;
  349. return clk_hw_register_divider_table(dev,
  350. cfg->name,
  351. cfg->parent_name,
  352. cfg->flags,
  353. div_cfg->reg_off + base,
  354. div_cfg->shift,
  355. div_cfg->width,
  356. div_cfg->div_flags,
  357. div_cfg->table,
  358. lock);
  359. }
  360. static struct clk_hw *
  361. _clk_hw_register_mux(struct device *dev,
  362. struct clk_hw_onecell_data *clk_data,
  363. void __iomem *base, spinlock_t *lock,
  364. const struct clock_config *cfg)
  365. {
  366. struct mux_cfg *mux_cfg = cfg->cfg;
  367. return clk_hw_register_mux(dev, cfg->name, cfg->parent_names,
  368. cfg->num_parents, cfg->flags,
  369. mux_cfg->reg_off + base, mux_cfg->shift,
  370. mux_cfg->width, mux_cfg->mux_flags, lock);
  371. }
  372. /* MP1 Gate clock with set & clear registers */
  373. static int mp1_gate_clk_enable(struct clk_hw *hw)
  374. {
  375. if (!clk_gate_ops.is_enabled(hw))
  376. clk_gate_ops.enable(hw);
  377. return 0;
  378. }
  379. static void mp1_gate_clk_disable(struct clk_hw *hw)
  380. {
  381. struct clk_gate *gate = to_clk_gate(hw);
  382. unsigned long flags = 0;
  383. if (clk_gate_ops.is_enabled(hw)) {
  384. spin_lock_irqsave(gate->lock, flags);
  385. writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR);
  386. spin_unlock_irqrestore(gate->lock, flags);
  387. }
  388. }
  389. static const struct clk_ops mp1_gate_clk_ops = {
  390. .enable = mp1_gate_clk_enable,
  391. .disable = mp1_gate_clk_disable,
  392. .is_enabled = clk_gate_is_enabled,
  393. };
  394. static struct clk_hw *_get_stm32_mux(void __iomem *base,
  395. const struct stm32_mux_cfg *cfg,
  396. spinlock_t *lock)
  397. {
  398. struct stm32_clk_mmux *mmux;
  399. struct clk_mux *mux;
  400. struct clk_hw *mux_hw;
  401. if (cfg->mmux) {
  402. mmux = kzalloc(sizeof(*mmux), GFP_KERNEL);
  403. if (!mmux)
  404. return ERR_PTR(-ENOMEM);
  405. mmux->mux.reg = cfg->mux->reg_off + base;
  406. mmux->mux.shift = cfg->mux->shift;
  407. mmux->mux.mask = (1 << cfg->mux->width) - 1;
  408. mmux->mux.flags = cfg->mux->mux_flags;
  409. mmux->mux.table = cfg->mux->table;
  410. mmux->mux.lock = lock;
  411. mmux->mmux = cfg->mmux;
  412. mux_hw = &mmux->mux.hw;
  413. cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
  414. } else {
  415. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  416. if (!mux)
  417. return ERR_PTR(-ENOMEM);
  418. mux->reg = cfg->mux->reg_off + base;
  419. mux->shift = cfg->mux->shift;
  420. mux->mask = (1 << cfg->mux->width) - 1;
  421. mux->flags = cfg->mux->mux_flags;
  422. mux->table = cfg->mux->table;
  423. mux->lock = lock;
  424. mux_hw = &mux->hw;
  425. }
  426. return mux_hw;
  427. }
  428. static struct clk_hw *_get_stm32_div(void __iomem *base,
  429. const struct stm32_div_cfg *cfg,
  430. spinlock_t *lock)
  431. {
  432. struct clk_divider *div;
  433. div = kzalloc(sizeof(*div), GFP_KERNEL);
  434. if (!div)
  435. return ERR_PTR(-ENOMEM);
  436. div->reg = cfg->div->reg_off + base;
  437. div->shift = cfg->div->shift;
  438. div->width = cfg->div->width;
  439. div->flags = cfg->div->div_flags;
  440. div->table = cfg->div->table;
  441. div->lock = lock;
  442. return &div->hw;
  443. }
  444. static struct clk_hw *
  445. _get_stm32_gate(void __iomem *base,
  446. const struct stm32_gate_cfg *cfg, spinlock_t *lock)
  447. {
  448. struct stm32_clk_mgate *mgate;
  449. struct clk_gate *gate;
  450. struct clk_hw *gate_hw;
  451. if (cfg->mgate) {
  452. mgate = kzalloc(sizeof(*mgate), GFP_KERNEL);
  453. if (!mgate)
  454. return ERR_PTR(-ENOMEM);
  455. mgate->gate.reg = cfg->gate->reg_off + base;
  456. mgate->gate.bit_idx = cfg->gate->bit_idx;
  457. mgate->gate.flags = cfg->gate->gate_flags;
  458. mgate->gate.lock = lock;
  459. mgate->mask = BIT(cfg->mgate->nbr_clk++);
  460. mgate->mgate = cfg->mgate;
  461. gate_hw = &mgate->gate.hw;
  462. } else {
  463. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  464. if (!gate)
  465. return ERR_PTR(-ENOMEM);
  466. gate->reg = cfg->gate->reg_off + base;
  467. gate->bit_idx = cfg->gate->bit_idx;
  468. gate->flags = cfg->gate->gate_flags;
  469. gate->lock = lock;
  470. gate_hw = &gate->hw;
  471. }
  472. return gate_hw;
  473. }
  474. static struct clk_hw *
  475. clk_stm32_register_gate_ops(struct device *dev,
  476. const char *name,
  477. const char *parent_name,
  478. unsigned long flags,
  479. void __iomem *base,
  480. const struct stm32_gate_cfg *cfg,
  481. spinlock_t *lock)
  482. {
  483. struct clk_init_data init = { NULL };
  484. struct clk_hw *hw;
  485. int ret;
  486. init.name = name;
  487. init.parent_names = &parent_name;
  488. init.num_parents = 1;
  489. init.flags = flags;
  490. init.ops = &clk_gate_ops;
  491. if (cfg->ops)
  492. init.ops = cfg->ops;
  493. hw = _get_stm32_gate(base, cfg, lock);
  494. if (IS_ERR(hw))
  495. return ERR_PTR(-ENOMEM);
  496. hw->init = &init;
  497. ret = clk_hw_register(dev, hw);
  498. if (ret)
  499. hw = ERR_PTR(ret);
  500. return hw;
  501. }
  502. static struct clk_hw *
  503. clk_stm32_register_composite(struct device *dev,
  504. const char *name, const char * const *parent_names,
  505. int num_parents, void __iomem *base,
  506. const struct stm32_composite_cfg *cfg,
  507. unsigned long flags, spinlock_t *lock)
  508. {
  509. const struct clk_ops *mux_ops, *div_ops, *gate_ops;
  510. struct clk_hw *mux_hw, *div_hw, *gate_hw;
  511. mux_hw = NULL;
  512. div_hw = NULL;
  513. gate_hw = NULL;
  514. mux_ops = NULL;
  515. div_ops = NULL;
  516. gate_ops = NULL;
  517. if (cfg->mux) {
  518. mux_hw = _get_stm32_mux(base, cfg->mux, lock);
  519. if (!IS_ERR(mux_hw)) {
  520. mux_ops = &clk_mux_ops;
  521. if (cfg->mux->ops)
  522. mux_ops = cfg->mux->ops;
  523. }
  524. }
  525. if (cfg->div) {
  526. div_hw = _get_stm32_div(base, cfg->div, lock);
  527. if (!IS_ERR(div_hw)) {
  528. div_ops = &clk_divider_ops;
  529. if (cfg->div->ops)
  530. div_ops = cfg->div->ops;
  531. }
  532. }
  533. if (cfg->gate) {
  534. gate_hw = _get_stm32_gate(base, cfg->gate, lock);
  535. if (!IS_ERR(gate_hw)) {
  536. gate_ops = &clk_gate_ops;
  537. if (cfg->gate->ops)
  538. gate_ops = cfg->gate->ops;
  539. }
  540. }
  541. return clk_hw_register_composite(dev, name, parent_names, num_parents,
  542. mux_hw, mux_ops, div_hw, div_ops,
  543. gate_hw, gate_ops, flags);
  544. }
  545. #define to_clk_mgate(_gate) container_of(_gate, struct stm32_clk_mgate, gate)
  546. static int mp1_mgate_clk_enable(struct clk_hw *hw)
  547. {
  548. struct clk_gate *gate = to_clk_gate(hw);
  549. struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
  550. clk_mgate->mgate->flag |= clk_mgate->mask;
  551. mp1_gate_clk_enable(hw);
  552. return 0;
  553. }
  554. static void mp1_mgate_clk_disable(struct clk_hw *hw)
  555. {
  556. struct clk_gate *gate = to_clk_gate(hw);
  557. struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
  558. clk_mgate->mgate->flag &= ~clk_mgate->mask;
  559. if (clk_mgate->mgate->flag == 0)
  560. mp1_gate_clk_disable(hw);
  561. }
  562. static const struct clk_ops mp1_mgate_clk_ops = {
  563. .enable = mp1_mgate_clk_enable,
  564. .disable = mp1_mgate_clk_disable,
  565. .is_enabled = clk_gate_is_enabled,
  566. };
  567. #define to_clk_mmux(_mux) container_of(_mux, struct stm32_clk_mmux, mux)
  568. static u8 clk_mmux_get_parent(struct clk_hw *hw)
  569. {
  570. return clk_mux_ops.get_parent(hw);
  571. }
  572. static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
  573. {
  574. struct clk_mux *mux = to_clk_mux(hw);
  575. struct stm32_clk_mmux *clk_mmux = to_clk_mmux(mux);
  576. struct clk_hw *hwp;
  577. int ret, n;
  578. ret = clk_mux_ops.set_parent(hw, index);
  579. if (ret)
  580. return ret;
  581. hwp = clk_hw_get_parent(hw);
  582. for (n = 0; n < clk_mmux->mmux->nbr_clk; n++)
  583. if (clk_mmux->mmux->hws[n] != hw)
  584. clk_hw_reparent(clk_mmux->mmux->hws[n], hwp);
  585. return 0;
  586. }
  587. static const struct clk_ops clk_mmux_ops = {
  588. .get_parent = clk_mmux_get_parent,
  589. .set_parent = clk_mmux_set_parent,
  590. .determine_rate = __clk_mux_determine_rate,
  591. };
  592. /* STM32 PLL */
  593. struct stm32_pll_obj {
  594. /* lock pll enable/disable registers */
  595. spinlock_t *lock;
  596. void __iomem *reg;
  597. struct clk_hw hw;
  598. };
  599. #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
  600. #define PLL_ON BIT(0)
  601. #define PLL_RDY BIT(1)
  602. #define DIVN_MASK 0x1FF
  603. #define DIVM_MASK 0x3F
  604. #define DIVM_SHIFT 16
  605. #define DIVN_SHIFT 0
  606. #define FRAC_OFFSET 0xC
  607. #define FRAC_MASK 0x1FFF
  608. #define FRAC_SHIFT 3
  609. #define FRACLE BIT(16)
  610. static int __pll_is_enabled(struct clk_hw *hw)
  611. {
  612. struct stm32_pll_obj *clk_elem = to_pll(hw);
  613. return readl_relaxed(clk_elem->reg) & PLL_ON;
  614. }
  615. #define TIMEOUT 5
  616. static int pll_enable(struct clk_hw *hw)
  617. {
  618. struct stm32_pll_obj *clk_elem = to_pll(hw);
  619. u32 reg;
  620. unsigned long flags = 0;
  621. unsigned int timeout = TIMEOUT;
  622. int bit_status = 0;
  623. spin_lock_irqsave(clk_elem->lock, flags);
  624. if (__pll_is_enabled(hw))
  625. goto unlock;
  626. reg = readl_relaxed(clk_elem->reg);
  627. reg |= PLL_ON;
  628. writel_relaxed(reg, clk_elem->reg);
  629. /* We can't use readl_poll_timeout() because we can be blocked if
  630. * someone enables this clock before clocksource changes.
  631. * Only jiffies counter is available. Jiffies are incremented by
  632. * interruptions and enable op does not allow to be interrupted.
  633. */
  634. do {
  635. bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY);
  636. if (bit_status)
  637. udelay(120);
  638. } while (bit_status && --timeout);
  639. unlock:
  640. spin_unlock_irqrestore(clk_elem->lock, flags);
  641. return bit_status;
  642. }
  643. static void pll_disable(struct clk_hw *hw)
  644. {
  645. struct stm32_pll_obj *clk_elem = to_pll(hw);
  646. u32 reg;
  647. unsigned long flags = 0;
  648. spin_lock_irqsave(clk_elem->lock, flags);
  649. reg = readl_relaxed(clk_elem->reg);
  650. reg &= ~PLL_ON;
  651. writel_relaxed(reg, clk_elem->reg);
  652. spin_unlock_irqrestore(clk_elem->lock, flags);
  653. }
  654. static u32 pll_frac_val(struct clk_hw *hw)
  655. {
  656. struct stm32_pll_obj *clk_elem = to_pll(hw);
  657. u32 reg, frac = 0;
  658. reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET);
  659. if (reg & FRACLE)
  660. frac = (reg >> FRAC_SHIFT) & FRAC_MASK;
  661. return frac;
  662. }
  663. static unsigned long pll_recalc_rate(struct clk_hw *hw,
  664. unsigned long parent_rate)
  665. {
  666. struct stm32_pll_obj *clk_elem = to_pll(hw);
  667. u32 reg;
  668. u32 frac, divm, divn;
  669. u64 rate, rate_frac = 0;
  670. reg = readl_relaxed(clk_elem->reg + 4);
  671. divm = ((reg >> DIVM_SHIFT) & DIVM_MASK) + 1;
  672. divn = ((reg >> DIVN_SHIFT) & DIVN_MASK) + 1;
  673. rate = (u64)parent_rate * divn;
  674. do_div(rate, divm);
  675. frac = pll_frac_val(hw);
  676. if (frac) {
  677. rate_frac = (u64)parent_rate * (u64)frac;
  678. do_div(rate_frac, (divm * 8192));
  679. }
  680. return rate + rate_frac;
  681. }
  682. static int pll_is_enabled(struct clk_hw *hw)
  683. {
  684. struct stm32_pll_obj *clk_elem = to_pll(hw);
  685. unsigned long flags = 0;
  686. int ret;
  687. spin_lock_irqsave(clk_elem->lock, flags);
  688. ret = __pll_is_enabled(hw);
  689. spin_unlock_irqrestore(clk_elem->lock, flags);
  690. return ret;
  691. }
  692. static const struct clk_ops pll_ops = {
  693. .enable = pll_enable,
  694. .disable = pll_disable,
  695. .recalc_rate = pll_recalc_rate,
  696. .is_enabled = pll_is_enabled,
  697. };
  698. static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
  699. const char *parent_name,
  700. void __iomem *reg,
  701. unsigned long flags,
  702. spinlock_t *lock)
  703. {
  704. struct stm32_pll_obj *element;
  705. struct clk_init_data init;
  706. struct clk_hw *hw;
  707. int err;
  708. element = kzalloc(sizeof(*element), GFP_KERNEL);
  709. if (!element)
  710. return ERR_PTR(-ENOMEM);
  711. init.name = name;
  712. init.ops = &pll_ops;
  713. init.flags = flags;
  714. init.parent_names = &parent_name;
  715. init.num_parents = 1;
  716. element->hw.init = &init;
  717. element->reg = reg;
  718. element->lock = lock;
  719. hw = &element->hw;
  720. err = clk_hw_register(dev, hw);
  721. if (err) {
  722. kfree(element);
  723. return ERR_PTR(err);
  724. }
  725. return hw;
  726. }
  727. /* Kernel Timer */
  728. struct timer_cker {
  729. /* lock the kernel output divider register */
  730. spinlock_t *lock;
  731. void __iomem *apbdiv;
  732. void __iomem *timpre;
  733. struct clk_hw hw;
  734. };
  735. #define to_timer_cker(_hw) container_of(_hw, struct timer_cker, hw)
  736. #define APB_DIV_MASK 0x07
  737. #define TIM_PRE_MASK 0x01
  738. static unsigned long __bestmult(struct clk_hw *hw, unsigned long rate,
  739. unsigned long parent_rate)
  740. {
  741. struct timer_cker *tim_ker = to_timer_cker(hw);
  742. u32 prescaler;
  743. unsigned int mult = 0;
  744. prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
  745. if (prescaler < 2)
  746. return 1;
  747. mult = 2;
  748. if (rate / parent_rate >= 4)
  749. mult = 4;
  750. return mult;
  751. }
  752. static long timer_ker_round_rate(struct clk_hw *hw, unsigned long rate,
  753. unsigned long *parent_rate)
  754. {
  755. unsigned long factor = __bestmult(hw, rate, *parent_rate);
  756. return *parent_rate * factor;
  757. }
  758. static int timer_ker_set_rate(struct clk_hw *hw, unsigned long rate,
  759. unsigned long parent_rate)
  760. {
  761. struct timer_cker *tim_ker = to_timer_cker(hw);
  762. unsigned long flags = 0;
  763. unsigned long factor = __bestmult(hw, rate, parent_rate);
  764. int ret = 0;
  765. spin_lock_irqsave(tim_ker->lock, flags);
  766. switch (factor) {
  767. case 1:
  768. break;
  769. case 2:
  770. writel_relaxed(0, tim_ker->timpre);
  771. break;
  772. case 4:
  773. writel_relaxed(1, tim_ker->timpre);
  774. break;
  775. default:
  776. ret = -EINVAL;
  777. }
  778. spin_unlock_irqrestore(tim_ker->lock, flags);
  779. return ret;
  780. }
  781. static unsigned long timer_ker_recalc_rate(struct clk_hw *hw,
  782. unsigned long parent_rate)
  783. {
  784. struct timer_cker *tim_ker = to_timer_cker(hw);
  785. u32 prescaler, timpre;
  786. u32 mul;
  787. prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
  788. timpre = readl_relaxed(tim_ker->timpre) & TIM_PRE_MASK;
  789. if (!prescaler)
  790. return parent_rate;
  791. mul = (timpre + 1) * 2;
  792. return parent_rate * mul;
  793. }
  794. static const struct clk_ops timer_ker_ops = {
  795. .recalc_rate = timer_ker_recalc_rate,
  796. .round_rate = timer_ker_round_rate,
  797. .set_rate = timer_ker_set_rate,
  798. };
  799. static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
  800. const char *parent_name,
  801. unsigned long flags,
  802. void __iomem *apbdiv,
  803. void __iomem *timpre,
  804. spinlock_t *lock)
  805. {
  806. struct timer_cker *tim_ker;
  807. struct clk_init_data init;
  808. struct clk_hw *hw;
  809. int err;
  810. tim_ker = kzalloc(sizeof(*tim_ker), GFP_KERNEL);
  811. if (!tim_ker)
  812. return ERR_PTR(-ENOMEM);
  813. init.name = name;
  814. init.ops = &timer_ker_ops;
  815. init.flags = flags;
  816. init.parent_names = &parent_name;
  817. init.num_parents = 1;
  818. tim_ker->hw.init = &init;
  819. tim_ker->lock = lock;
  820. tim_ker->apbdiv = apbdiv;
  821. tim_ker->timpre = timpre;
  822. hw = &tim_ker->hw;
  823. err = clk_hw_register(dev, hw);
  824. if (err) {
  825. kfree(tim_ker);
  826. return ERR_PTR(err);
  827. }
  828. return hw;
  829. }
  830. struct stm32_pll_cfg {
  831. u32 offset;
  832. };
  833. static struct clk_hw *_clk_register_pll(struct device *dev,
  834. struct clk_hw_onecell_data *clk_data,
  835. void __iomem *base, spinlock_t *lock,
  836. const struct clock_config *cfg)
  837. {
  838. struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
  839. return clk_register_pll(dev, cfg->name, cfg->parent_name,
  840. base + stm_pll_cfg->offset, cfg->flags, lock);
  841. }
  842. struct stm32_cktim_cfg {
  843. u32 offset_apbdiv;
  844. u32 offset_timpre;
  845. };
  846. static struct clk_hw *_clk_register_cktim(struct device *dev,
  847. struct clk_hw_onecell_data *clk_data,
  848. void __iomem *base, spinlock_t *lock,
  849. const struct clock_config *cfg)
  850. {
  851. struct stm32_cktim_cfg *cktim_cfg = cfg->cfg;
  852. return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags,
  853. cktim_cfg->offset_apbdiv + base,
  854. cktim_cfg->offset_timpre + base, lock);
  855. }
  856. static struct clk_hw *
  857. _clk_stm32_register_gate(struct device *dev,
  858. struct clk_hw_onecell_data *clk_data,
  859. void __iomem *base, spinlock_t *lock,
  860. const struct clock_config *cfg)
  861. {
  862. return clk_stm32_register_gate_ops(dev,
  863. cfg->name,
  864. cfg->parent_name,
  865. cfg->flags,
  866. base,
  867. cfg->cfg,
  868. lock);
  869. }
  870. static struct clk_hw *
  871. _clk_stm32_register_composite(struct device *dev,
  872. struct clk_hw_onecell_data *clk_data,
  873. void __iomem *base, spinlock_t *lock,
  874. const struct clock_config *cfg)
  875. {
  876. return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names,
  877. cfg->num_parents, base, cfg->cfg,
  878. cfg->flags, lock);
  879. }
  880. #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
  881. {\
  882. .id = _id,\
  883. .name = _name,\
  884. .parent_name = _parent,\
  885. .flags = _flags,\
  886. .cfg = &(struct gate_cfg) {\
  887. .reg_off = _offset,\
  888. .bit_idx = _bit_idx,\
  889. .gate_flags = _gate_flags,\
  890. },\
  891. .func = _clk_hw_register_gate,\
  892. }
  893. #define FIXED_FACTOR(_id, _name, _parent, _flags, _mult, _div)\
  894. {\
  895. .id = _id,\
  896. .name = _name,\
  897. .parent_name = _parent,\
  898. .flags = _flags,\
  899. .cfg = &(struct fixed_factor_cfg) {\
  900. .mult = _mult,\
  901. .div = _div,\
  902. },\
  903. .func = _clk_hw_register_fixed_factor,\
  904. }
  905. #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
  906. _div_flags, _div_table)\
  907. {\
  908. .id = _id,\
  909. .name = _name,\
  910. .parent_name = _parent,\
  911. .flags = _flags,\
  912. .cfg = &(struct div_cfg) {\
  913. .reg_off = _offset,\
  914. .shift = _shift,\
  915. .width = _width,\
  916. .div_flags = _div_flags,\
  917. .table = _div_table,\
  918. },\
  919. .func = _clk_hw_register_divider_table,\
  920. }
  921. #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\
  922. DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
  923. _div_flags, NULL)
  924. #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\
  925. {\
  926. .id = _id,\
  927. .name = _name,\
  928. .parent_names = _parents,\
  929. .num_parents = ARRAY_SIZE(_parents),\
  930. .flags = _flags,\
  931. .cfg = &(struct mux_cfg) {\
  932. .reg_off = _offset,\
  933. .shift = _shift,\
  934. .width = _width,\
  935. .mux_flags = _mux_flags,\
  936. },\
  937. .func = _clk_hw_register_mux,\
  938. }
  939. #define PLL(_id, _name, _parent, _flags, _offset)\
  940. {\
  941. .id = _id,\
  942. .name = _name,\
  943. .parent_name = _parent,\
  944. .flags = _flags,\
  945. .cfg = &(struct stm32_pll_cfg) {\
  946. .offset = _offset,\
  947. },\
  948. .func = _clk_register_pll,\
  949. }
  950. #define STM32_CKTIM(_name, _parent, _flags, _offset_apbdiv, _offset_timpre)\
  951. {\
  952. .id = NO_ID,\
  953. .name = _name,\
  954. .parent_name = _parent,\
  955. .flags = _flags,\
  956. .cfg = &(struct stm32_cktim_cfg) {\
  957. .offset_apbdiv = _offset_apbdiv,\
  958. .offset_timpre = _offset_timpre,\
  959. },\
  960. .func = _clk_register_cktim,\
  961. }
  962. #define STM32_TIM(_id, _name, _parent, _offset_set, _bit_idx)\
  963. GATE_MP1(_id, _name, _parent, CLK_SET_RATE_PARENT,\
  964. _offset_set, _bit_idx, 0)
  965. /* STM32 GATE */
  966. #define STM32_GATE(_id, _name, _parent, _flags, _gate)\
  967. {\
  968. .id = _id,\
  969. .name = _name,\
  970. .parent_name = _parent,\
  971. .flags = _flags,\
  972. .cfg = (struct stm32_gate_cfg *) {_gate},\
  973. .func = _clk_stm32_register_gate,\
  974. }
  975. #define _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags, _mgate, _ops)\
  976. (&(struct stm32_gate_cfg) {\
  977. &(struct gate_cfg) {\
  978. .reg_off = _gate_offset,\
  979. .bit_idx = _gate_bit_idx,\
  980. .gate_flags = _gate_flags,\
  981. },\
  982. .mgate = _mgate,\
  983. .ops = _ops,\
  984. })
  985. #define _STM32_MGATE(_mgate)\
  986. (&per_gate_cfg[_mgate])
  987. #define _GATE(_gate_offset, _gate_bit_idx, _gate_flags)\
  988. _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
  989. NULL, NULL)\
  990. #define _GATE_MP1(_gate_offset, _gate_bit_idx, _gate_flags)\
  991. _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
  992. NULL, &mp1_gate_clk_ops)\
  993. #define _MGATE_MP1(_mgate)\
  994. .gate = &per_gate_cfg[_mgate]
  995. #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
  996. STM32_GATE(_id, _name, _parent, _flags,\
  997. _GATE_MP1(_offset, _bit_idx, _gate_flags))
  998. #define MGATE_MP1(_id, _name, _parent, _flags, _mgate)\
  999. STM32_GATE(_id, _name, _parent, _flags,\
  1000. _STM32_MGATE(_mgate))
  1001. #define _STM32_DIV(_div_offset, _div_shift, _div_width,\
  1002. _div_flags, _div_table, _ops)\
  1003. .div = &(struct stm32_div_cfg) {\
  1004. &(struct div_cfg) {\
  1005. .reg_off = _div_offset,\
  1006. .shift = _div_shift,\
  1007. .width = _div_width,\
  1008. .div_flags = _div_flags,\
  1009. .table = _div_table,\
  1010. },\
  1011. .ops = _ops,\
  1012. }
  1013. #define _DIV(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
  1014. _STM32_DIV(_div_offset, _div_shift, _div_width,\
  1015. _div_flags, _div_table, NULL)\
  1016. #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
  1017. .mux = &(struct stm32_mux_cfg) {\
  1018. &(struct mux_cfg) {\
  1019. .reg_off = _offset,\
  1020. .shift = _shift,\
  1021. .width = _width,\
  1022. .mux_flags = _mux_flags,\
  1023. .table = NULL,\
  1024. },\
  1025. .mmux = _mmux,\
  1026. .ops = _ops,\
  1027. }
  1028. #define _MUX(_offset, _shift, _width, _mux_flags)\
  1029. _STM32_MUX(_offset, _shift, _width, _mux_flags, NULL, NULL)\
  1030. #define _MMUX(_mmux) .mux = &ker_mux_cfg[_mmux]
  1031. #define PARENT(_parent) ((const char *[]) { _parent})
  1032. #define _NO_MUX .mux = NULL
  1033. #define _NO_DIV .div = NULL
  1034. #define _NO_GATE .gate = NULL
  1035. #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\
  1036. {\
  1037. .id = _id,\
  1038. .name = _name,\
  1039. .parent_names = _parents,\
  1040. .num_parents = ARRAY_SIZE(_parents),\
  1041. .flags = _flags,\
  1042. .cfg = &(struct stm32_composite_cfg) {\
  1043. _gate,\
  1044. _mux,\
  1045. _div,\
  1046. },\
  1047. .func = _clk_stm32_register_composite,\
  1048. }
  1049. #define PCLK(_id, _name, _parent, _flags, _mgate)\
  1050. MGATE_MP1(_id, _name, _parent, _flags, _mgate)
  1051. #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
  1052. COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
  1053. CLK_SET_RATE_NO_REPARENT | _flags,\
  1054. _MGATE_MP1(_mgate),\
  1055. _MMUX(_mmux),\
  1056. _NO_DIV)
  1057. enum {
  1058. G_SAI1,
  1059. G_SAI2,
  1060. G_SAI3,
  1061. G_SAI4,
  1062. G_SPI1,
  1063. G_SPI2,
  1064. G_SPI3,
  1065. G_SPI4,
  1066. G_SPI5,
  1067. G_SPI6,
  1068. G_SPDIF,
  1069. G_I2C1,
  1070. G_I2C2,
  1071. G_I2C3,
  1072. G_I2C4,
  1073. G_I2C5,
  1074. G_I2C6,
  1075. G_USART2,
  1076. G_UART4,
  1077. G_USART3,
  1078. G_UART5,
  1079. G_USART1,
  1080. G_USART6,
  1081. G_UART7,
  1082. G_UART8,
  1083. G_LPTIM1,
  1084. G_LPTIM2,
  1085. G_LPTIM3,
  1086. G_LPTIM4,
  1087. G_LPTIM5,
  1088. G_LTDC,
  1089. G_DSI,
  1090. G_QSPI,
  1091. G_FMC,
  1092. G_SDMMC1,
  1093. G_SDMMC2,
  1094. G_SDMMC3,
  1095. G_USBO,
  1096. G_USBPHY,
  1097. G_RNG1,
  1098. G_RNG2,
  1099. G_FDCAN,
  1100. G_DAC12,
  1101. G_CEC,
  1102. G_ADC12,
  1103. G_GPU,
  1104. G_STGEN,
  1105. G_DFSDM,
  1106. G_ADFSDM,
  1107. G_TIM2,
  1108. G_TIM3,
  1109. G_TIM4,
  1110. G_TIM5,
  1111. G_TIM6,
  1112. G_TIM7,
  1113. G_TIM12,
  1114. G_TIM13,
  1115. G_TIM14,
  1116. G_MDIO,
  1117. G_TIM1,
  1118. G_TIM8,
  1119. G_TIM15,
  1120. G_TIM16,
  1121. G_TIM17,
  1122. G_SYSCFG,
  1123. G_VREF,
  1124. G_TMPSENS,
  1125. G_PMBCTRL,
  1126. G_HDP,
  1127. G_IWDG2,
  1128. G_STGENRO,
  1129. G_DMA1,
  1130. G_DMA2,
  1131. G_DMAMUX,
  1132. G_DCMI,
  1133. G_CRYP2,
  1134. G_HASH2,
  1135. G_CRC2,
  1136. G_HSEM,
  1137. G_IPCC,
  1138. G_GPIOA,
  1139. G_GPIOB,
  1140. G_GPIOC,
  1141. G_GPIOD,
  1142. G_GPIOE,
  1143. G_GPIOF,
  1144. G_GPIOG,
  1145. G_GPIOH,
  1146. G_GPIOI,
  1147. G_GPIOJ,
  1148. G_GPIOK,
  1149. G_MDMA,
  1150. G_ETHCK,
  1151. G_ETHTX,
  1152. G_ETHRX,
  1153. G_ETHMAC,
  1154. G_CRC1,
  1155. G_USBH,
  1156. G_ETHSTP,
  1157. G_RTCAPB,
  1158. G_TZC1,
  1159. G_TZC2,
  1160. G_TZPC,
  1161. G_IWDG1,
  1162. G_BSEC,
  1163. G_GPIOZ,
  1164. G_CRYP1,
  1165. G_HASH1,
  1166. G_BKPSRAM,
  1167. G_DDRPERFM,
  1168. G_LAST
  1169. };
  1170. static struct stm32_mgate mp1_mgate[G_LAST];
  1171. #define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
  1172. _mgate, _ops)\
  1173. [_id] = {\
  1174. &(struct gate_cfg) {\
  1175. .reg_off = _gate_offset,\
  1176. .bit_idx = _gate_bit_idx,\
  1177. .gate_flags = _gate_flags,\
  1178. },\
  1179. .mgate = _mgate,\
  1180. .ops = _ops,\
  1181. }
  1182. #define K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
  1183. _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
  1184. NULL, &mp1_gate_clk_ops)
  1185. #define K_MGATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
  1186. _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
  1187. &mp1_mgate[_id], &mp1_mgate_clk_ops)
  1188. /* Peripheral gates */
  1189. static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
  1190. /* Multi gates */
  1191. K_GATE(G_MDIO, RCC_APB1ENSETR, 31, 0),
  1192. K_MGATE(G_DAC12, RCC_APB1ENSETR, 29, 0),
  1193. K_MGATE(G_CEC, RCC_APB1ENSETR, 27, 0),
  1194. K_MGATE(G_SPDIF, RCC_APB1ENSETR, 26, 0),
  1195. K_MGATE(G_I2C5, RCC_APB1ENSETR, 24, 0),
  1196. K_MGATE(G_I2C3, RCC_APB1ENSETR, 23, 0),
  1197. K_MGATE(G_I2C2, RCC_APB1ENSETR, 22, 0),
  1198. K_MGATE(G_I2C1, RCC_APB1ENSETR, 21, 0),
  1199. K_MGATE(G_UART8, RCC_APB1ENSETR, 19, 0),
  1200. K_MGATE(G_UART7, RCC_APB1ENSETR, 18, 0),
  1201. K_MGATE(G_UART5, RCC_APB1ENSETR, 17, 0),
  1202. K_MGATE(G_UART4, RCC_APB1ENSETR, 16, 0),
  1203. K_MGATE(G_USART3, RCC_APB1ENSETR, 15, 0),
  1204. K_MGATE(G_USART2, RCC_APB1ENSETR, 14, 0),
  1205. K_MGATE(G_SPI3, RCC_APB1ENSETR, 12, 0),
  1206. K_MGATE(G_SPI2, RCC_APB1ENSETR, 11, 0),
  1207. K_MGATE(G_LPTIM1, RCC_APB1ENSETR, 9, 0),
  1208. K_GATE(G_TIM14, RCC_APB1ENSETR, 8, 0),
  1209. K_GATE(G_TIM13, RCC_APB1ENSETR, 7, 0),
  1210. K_GATE(G_TIM12, RCC_APB1ENSETR, 6, 0),
  1211. K_GATE(G_TIM7, RCC_APB1ENSETR, 5, 0),
  1212. K_GATE(G_TIM6, RCC_APB1ENSETR, 4, 0),
  1213. K_GATE(G_TIM5, RCC_APB1ENSETR, 3, 0),
  1214. K_GATE(G_TIM4, RCC_APB1ENSETR, 2, 0),
  1215. K_GATE(G_TIM3, RCC_APB1ENSETR, 1, 0),
  1216. K_GATE(G_TIM2, RCC_APB1ENSETR, 0, 0),
  1217. K_MGATE(G_FDCAN, RCC_APB2ENSETR, 24, 0),
  1218. K_GATE(G_ADFSDM, RCC_APB2ENSETR, 21, 0),
  1219. K_GATE(G_DFSDM, RCC_APB2ENSETR, 20, 0),
  1220. K_MGATE(G_SAI3, RCC_APB2ENSETR, 18, 0),
  1221. K_MGATE(G_SAI2, RCC_APB2ENSETR, 17, 0),
  1222. K_MGATE(G_SAI1, RCC_APB2ENSETR, 16, 0),
  1223. K_MGATE(G_USART6, RCC_APB2ENSETR, 13, 0),
  1224. K_MGATE(G_SPI5, RCC_APB2ENSETR, 10, 0),
  1225. K_MGATE(G_SPI4, RCC_APB2ENSETR, 9, 0),
  1226. K_MGATE(G_SPI1, RCC_APB2ENSETR, 8, 0),
  1227. K_GATE(G_TIM17, RCC_APB2ENSETR, 4, 0),
  1228. K_GATE(G_TIM16, RCC_APB2ENSETR, 3, 0),
  1229. K_GATE(G_TIM15, RCC_APB2ENSETR, 2, 0),
  1230. K_GATE(G_TIM8, RCC_APB2ENSETR, 1, 0),
  1231. K_GATE(G_TIM1, RCC_APB2ENSETR, 0, 0),
  1232. K_GATE(G_HDP, RCC_APB3ENSETR, 20, 0),
  1233. K_GATE(G_PMBCTRL, RCC_APB3ENSETR, 17, 0),
  1234. K_GATE(G_TMPSENS, RCC_APB3ENSETR, 16, 0),
  1235. K_GATE(G_VREF, RCC_APB3ENSETR, 13, 0),
  1236. K_GATE(G_SYSCFG, RCC_APB3ENSETR, 11, 0),
  1237. K_MGATE(G_SAI4, RCC_APB3ENSETR, 8, 0),
  1238. K_MGATE(G_LPTIM5, RCC_APB3ENSETR, 3, 0),
  1239. K_MGATE(G_LPTIM4, RCC_APB3ENSETR, 2, 0),
  1240. K_MGATE(G_LPTIM3, RCC_APB3ENSETR, 1, 0),
  1241. K_MGATE(G_LPTIM2, RCC_APB3ENSETR, 0, 0),
  1242. K_GATE(G_STGENRO, RCC_APB4ENSETR, 20, 0),
  1243. K_MGATE(G_USBPHY, RCC_APB4ENSETR, 16, 0),
  1244. K_GATE(G_IWDG2, RCC_APB4ENSETR, 15, 0),
  1245. K_GATE(G_DDRPERFM, RCC_APB4ENSETR, 8, 0),
  1246. K_MGATE(G_DSI, RCC_APB4ENSETR, 4, 0),
  1247. K_MGATE(G_LTDC, RCC_APB4ENSETR, 0, 0),
  1248. K_GATE(G_STGEN, RCC_APB5ENSETR, 20, 0),
  1249. K_GATE(G_BSEC, RCC_APB5ENSETR, 16, 0),
  1250. K_GATE(G_IWDG1, RCC_APB5ENSETR, 15, 0),
  1251. K_GATE(G_TZPC, RCC_APB5ENSETR, 13, 0),
  1252. K_GATE(G_TZC2, RCC_APB5ENSETR, 12, 0),
  1253. K_GATE(G_TZC1, RCC_APB5ENSETR, 11, 0),
  1254. K_GATE(G_RTCAPB, RCC_APB5ENSETR, 8, 0),
  1255. K_MGATE(G_USART1, RCC_APB5ENSETR, 4, 0),
  1256. K_MGATE(G_I2C6, RCC_APB5ENSETR, 3, 0),
  1257. K_MGATE(G_I2C4, RCC_APB5ENSETR, 2, 0),
  1258. K_MGATE(G_SPI6, RCC_APB5ENSETR, 0, 0),
  1259. K_MGATE(G_SDMMC3, RCC_AHB2ENSETR, 16, 0),
  1260. K_MGATE(G_USBO, RCC_AHB2ENSETR, 8, 0),
  1261. K_MGATE(G_ADC12, RCC_AHB2ENSETR, 5, 0),
  1262. K_GATE(G_DMAMUX, RCC_AHB2ENSETR, 2, 0),
  1263. K_GATE(G_DMA2, RCC_AHB2ENSETR, 1, 0),
  1264. K_GATE(G_DMA1, RCC_AHB2ENSETR, 0, 0),
  1265. K_GATE(G_IPCC, RCC_AHB3ENSETR, 12, 0),
  1266. K_GATE(G_HSEM, RCC_AHB3ENSETR, 11, 0),
  1267. K_GATE(G_CRC2, RCC_AHB3ENSETR, 7, 0),
  1268. K_MGATE(G_RNG2, RCC_AHB3ENSETR, 6, 0),
  1269. K_GATE(G_HASH2, RCC_AHB3ENSETR, 5, 0),
  1270. K_GATE(G_CRYP2, RCC_AHB3ENSETR, 4, 0),
  1271. K_GATE(G_DCMI, RCC_AHB3ENSETR, 0, 0),
  1272. K_GATE(G_GPIOK, RCC_AHB4ENSETR, 10, 0),
  1273. K_GATE(G_GPIOJ, RCC_AHB4ENSETR, 9, 0),
  1274. K_GATE(G_GPIOI, RCC_AHB4ENSETR, 8, 0),
  1275. K_GATE(G_GPIOH, RCC_AHB4ENSETR, 7, 0),
  1276. K_GATE(G_GPIOG, RCC_AHB4ENSETR, 6, 0),
  1277. K_GATE(G_GPIOF, RCC_AHB4ENSETR, 5, 0),
  1278. K_GATE(G_GPIOE, RCC_AHB4ENSETR, 4, 0),
  1279. K_GATE(G_GPIOD, RCC_AHB4ENSETR, 3, 0),
  1280. K_GATE(G_GPIOC, RCC_AHB4ENSETR, 2, 0),
  1281. K_GATE(G_GPIOB, RCC_AHB4ENSETR, 1, 0),
  1282. K_GATE(G_GPIOA, RCC_AHB4ENSETR, 0, 0),
  1283. K_GATE(G_BKPSRAM, RCC_AHB5ENSETR, 8, 0),
  1284. K_MGATE(G_RNG1, RCC_AHB5ENSETR, 6, 0),
  1285. K_GATE(G_HASH1, RCC_AHB5ENSETR, 5, 0),
  1286. K_GATE(G_CRYP1, RCC_AHB5ENSETR, 4, 0),
  1287. K_GATE(G_GPIOZ, RCC_AHB5ENSETR, 0, 0),
  1288. K_GATE(G_USBH, RCC_AHB6ENSETR, 24, 0),
  1289. K_GATE(G_CRC1, RCC_AHB6ENSETR, 20, 0),
  1290. K_MGATE(G_SDMMC2, RCC_AHB6ENSETR, 17, 0),
  1291. K_MGATE(G_SDMMC1, RCC_AHB6ENSETR, 16, 0),
  1292. K_MGATE(G_QSPI, RCC_AHB6ENSETR, 14, 0),
  1293. K_MGATE(G_FMC, RCC_AHB6ENSETR, 12, 0),
  1294. K_GATE(G_ETHMAC, RCC_AHB6ENSETR, 10, 0),
  1295. K_GATE(G_ETHRX, RCC_AHB6ENSETR, 9, 0),
  1296. K_GATE(G_ETHTX, RCC_AHB6ENSETR, 8, 0),
  1297. K_GATE(G_ETHCK, RCC_AHB6ENSETR, 7, 0),
  1298. K_MGATE(G_GPU, RCC_AHB6ENSETR, 5, 0),
  1299. K_GATE(G_MDMA, RCC_AHB6ENSETR, 0, 0),
  1300. K_GATE(G_ETHSTP, RCC_AHB6LPENSETR, 11, 0),
  1301. };
  1302. enum {
  1303. M_SDMMC12,
  1304. M_SDMMC3,
  1305. M_FMC,
  1306. M_QSPI,
  1307. M_RNG1,
  1308. M_RNG2,
  1309. M_USBPHY,
  1310. M_USBO,
  1311. M_STGEN,
  1312. M_SPDIF,
  1313. M_SPI1,
  1314. M_SPI23,
  1315. M_SPI45,
  1316. M_SPI6,
  1317. M_CEC,
  1318. M_I2C12,
  1319. M_I2C35,
  1320. M_I2C46,
  1321. M_LPTIM1,
  1322. M_LPTIM23,
  1323. M_LPTIM45,
  1324. M_USART1,
  1325. M_UART24,
  1326. M_UART35,
  1327. M_USART6,
  1328. M_UART78,
  1329. M_SAI1,
  1330. M_SAI2,
  1331. M_SAI3,
  1332. M_SAI4,
  1333. M_DSI,
  1334. M_FDCAN,
  1335. M_ADC12,
  1336. M_ETHCK,
  1337. M_CKPER,
  1338. M_LAST
  1339. };
  1340. static struct stm32_mmux ker_mux[M_LAST];
  1341. #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
  1342. [_id] = {\
  1343. &(struct mux_cfg) {\
  1344. .reg_off = _offset,\
  1345. .shift = _shift,\
  1346. .width = _width,\
  1347. .mux_flags = _mux_flags,\
  1348. .table = NULL,\
  1349. },\
  1350. .mmux = _mmux,\
  1351. .ops = _ops,\
  1352. }
  1353. #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\
  1354. _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
  1355. NULL, NULL)
  1356. #define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\
  1357. _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
  1358. &ker_mux[_id], &clk_mmux_ops)
  1359. static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
  1360. /* Kernel multi mux */
  1361. K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
  1362. K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
  1363. K_MMUX(M_SPI45, RCC_SPI2S45CKSELR, 0, 3, 0),
  1364. K_MMUX(M_I2C12, RCC_I2C12CKSELR, 0, 3, 0),
  1365. K_MMUX(M_I2C35, RCC_I2C35CKSELR, 0, 3, 0),
  1366. K_MMUX(M_LPTIM23, RCC_LPTIM23CKSELR, 0, 3, 0),
  1367. K_MMUX(M_LPTIM45, RCC_LPTIM45CKSELR, 0, 3, 0),
  1368. K_MMUX(M_UART24, RCC_UART24CKSELR, 0, 3, 0),
  1369. K_MMUX(M_UART35, RCC_UART35CKSELR, 0, 3, 0),
  1370. K_MMUX(M_UART78, RCC_UART78CKSELR, 0, 3, 0),
  1371. K_MMUX(M_SAI1, RCC_SAI1CKSELR, 0, 3, 0),
  1372. K_MMUX(M_ETHCK, RCC_ETHCKSELR, 0, 2, 0),
  1373. K_MMUX(M_I2C46, RCC_I2C46CKSELR, 0, 3, 0),
  1374. /* Kernel simple mux */
  1375. K_MUX(M_RNG2, RCC_RNG2CKSELR, 0, 2, 0),
  1376. K_MUX(M_SDMMC3, RCC_SDMMC3CKSELR, 0, 3, 0),
  1377. K_MUX(M_FMC, RCC_FMCCKSELR, 0, 2, 0),
  1378. K_MUX(M_QSPI, RCC_QSPICKSELR, 0, 2, 0),
  1379. K_MUX(M_USBPHY, RCC_USBCKSELR, 0, 2, 0),
  1380. K_MUX(M_USBO, RCC_USBCKSELR, 4, 1, 0),
  1381. K_MUX(M_SPDIF, RCC_SPDIFCKSELR, 0, 2, 0),
  1382. K_MUX(M_SPI1, RCC_SPI2S1CKSELR, 0, 3, 0),
  1383. K_MUX(M_CEC, RCC_CECCKSELR, 0, 2, 0),
  1384. K_MUX(M_LPTIM1, RCC_LPTIM1CKSELR, 0, 3, 0),
  1385. K_MUX(M_USART6, RCC_UART6CKSELR, 0, 3, 0),
  1386. K_MUX(M_FDCAN, RCC_FDCANCKSELR, 0, 2, 0),
  1387. K_MUX(M_SAI2, RCC_SAI2CKSELR, 0, 3, 0),
  1388. K_MUX(M_SAI3, RCC_SAI3CKSELR, 0, 3, 0),
  1389. K_MUX(M_SAI4, RCC_SAI4CKSELR, 0, 3, 0),
  1390. K_MUX(M_ADC12, RCC_ADCCKSELR, 0, 2, 0),
  1391. K_MUX(M_DSI, RCC_DSICKSELR, 0, 1, 0),
  1392. K_MUX(M_CKPER, RCC_CPERCKSELR, 0, 2, 0),
  1393. K_MUX(M_RNG1, RCC_RNG1CKSELR, 0, 2, 0),
  1394. K_MUX(M_STGEN, RCC_STGENCKSELR, 0, 2, 0),
  1395. K_MUX(M_USART1, RCC_UART1CKSELR, 0, 3, 0),
  1396. K_MUX(M_SPI6, RCC_SPI6CKSELR, 0, 3, 0),
  1397. };
  1398. static const struct clock_config stm32mp1_clock_cfg[] = {
  1399. /* Oscillator divider */
  1400. DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
  1401. RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
  1402. /* External / Internal Oscillators */
  1403. GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
  1404. /* ck_csi is used by IO compensation and should be critical */
  1405. GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
  1406. RCC_OCENSETR, 4, 0),
  1407. GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
  1408. GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
  1409. GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
  1410. FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
  1411. /* ref clock pll */
  1412. MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
  1413. 0, 2, CLK_MUX_READ_ONLY),
  1414. MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
  1415. 0, 2, CLK_MUX_READ_ONLY),
  1416. MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
  1417. 0, 2, CLK_MUX_READ_ONLY),
  1418. /* PLLs */
  1419. PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
  1420. PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
  1421. PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR),
  1422. PLL(PLL4, "pll4", "ref4", CLK_IGNORE_UNUSED, RCC_PLL4CR),
  1423. /* ODF */
  1424. COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
  1425. _GATE(RCC_PLL1CR, 4, 0),
  1426. _NO_MUX,
  1427. _DIV(RCC_PLL1CFGR2, 0, 7, 0, NULL)),
  1428. COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,
  1429. _GATE(RCC_PLL2CR, 4, 0),
  1430. _NO_MUX,
  1431. _DIV(RCC_PLL2CFGR2, 0, 7, 0, NULL)),
  1432. COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,
  1433. _GATE(RCC_PLL2CR, 5, 0),
  1434. _NO_MUX,
  1435. _DIV(RCC_PLL2CFGR2, 8, 7, 0, NULL)),
  1436. COMPOSITE(PLL2_R, "pll2_r", PARENT("pll2"), CLK_IS_CRITICAL,
  1437. _GATE(RCC_PLL2CR, 6, 0),
  1438. _NO_MUX,
  1439. _DIV(RCC_PLL2CFGR2, 16, 7, 0, NULL)),
  1440. COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,
  1441. _GATE(RCC_PLL3CR, 4, 0),
  1442. _NO_MUX,
  1443. _DIV(RCC_PLL3CFGR2, 0, 7, 0, NULL)),
  1444. COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,
  1445. _GATE(RCC_PLL3CR, 5, 0),
  1446. _NO_MUX,
  1447. _DIV(RCC_PLL3CFGR2, 8, 7, 0, NULL)),
  1448. COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,
  1449. _GATE(RCC_PLL3CR, 6, 0),
  1450. _NO_MUX,
  1451. _DIV(RCC_PLL3CFGR2, 16, 7, 0, NULL)),
  1452. COMPOSITE(PLL4_P, "pll4_p", PARENT("pll4"), 0,
  1453. _GATE(RCC_PLL4CR, 4, 0),
  1454. _NO_MUX,
  1455. _DIV(RCC_PLL4CFGR2, 0, 7, 0, NULL)),
  1456. COMPOSITE(PLL4_Q, "pll4_q", PARENT("pll4"), 0,
  1457. _GATE(RCC_PLL4CR, 5, 0),
  1458. _NO_MUX,
  1459. _DIV(RCC_PLL4CFGR2, 8, 7, 0, NULL)),
  1460. COMPOSITE(PLL4_R, "pll4_r", PARENT("pll4"), 0,
  1461. _GATE(RCC_PLL4CR, 6, 0),
  1462. _NO_MUX,
  1463. _DIV(RCC_PLL4CFGR2, 16, 7, 0, NULL)),
  1464. /* MUX system clocks */
  1465. MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
  1466. RCC_CPERCKSELR, 0, 2, 0),
  1467. MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
  1468. CLK_IS_CRITICAL, RCC_MPCKSELR, 0, 2, 0),
  1469. COMPOSITE(CK_AXI, "ck_axi", axi_src, CLK_IS_CRITICAL |
  1470. CLK_OPS_PARENT_ENABLE,
  1471. _NO_GATE,
  1472. _MUX(RCC_ASSCKSELR, 0, 2, 0),
  1473. _DIV(RCC_AXIDIVR, 0, 3, 0, axi_div_table)),
  1474. COMPOSITE(CK_MCU, "ck_mcu", mcu_src, CLK_IS_CRITICAL |
  1475. CLK_OPS_PARENT_ENABLE,
  1476. _NO_GATE,
  1477. _MUX(RCC_MSSCKSELR, 0, 2, 0),
  1478. _DIV(RCC_MCUDIVR, 0, 4, 0, mcu_div_table)),
  1479. DIV_TABLE(NO_ID, "pclk1", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB1DIVR, 0,
  1480. 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
  1481. DIV_TABLE(NO_ID, "pclk2", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB2DIVR, 0,
  1482. 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
  1483. DIV_TABLE(NO_ID, "pclk3", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB3DIVR, 0,
  1484. 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
  1485. DIV_TABLE(NO_ID, "pclk4", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB4DIVR, 0,
  1486. 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
  1487. DIV_TABLE(NO_ID, "pclk5", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB5DIVR, 0,
  1488. 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
  1489. /* Kernel Timers */
  1490. STM32_CKTIM("ck1_tim", "pclk1", 0, RCC_APB1DIVR, RCC_TIMG1PRER),
  1491. STM32_CKTIM("ck2_tim", "pclk2", 0, RCC_APB2DIVR, RCC_TIMG2PRER),
  1492. STM32_TIM(TIM2_K, "tim2_k", "ck1_tim", RCC_APB1ENSETR, 0),
  1493. STM32_TIM(TIM3_K, "tim3_k", "ck1_tim", RCC_APB1ENSETR, 1),
  1494. STM32_TIM(TIM4_K, "tim4_k", "ck1_tim", RCC_APB1ENSETR, 2),
  1495. STM32_TIM(TIM5_K, "tim5_k", "ck1_tim", RCC_APB1ENSETR, 3),
  1496. STM32_TIM(TIM6_K, "tim6_k", "ck1_tim", RCC_APB1ENSETR, 4),
  1497. STM32_TIM(TIM7_K, "tim7_k", "ck1_tim", RCC_APB1ENSETR, 5),
  1498. STM32_TIM(TIM12_K, "tim12_k", "ck1_tim", RCC_APB1ENSETR, 6),
  1499. STM32_TIM(TIM13_K, "tim13_k", "ck1_tim", RCC_APB1ENSETR, 7),
  1500. STM32_TIM(TIM14_K, "tim14_k", "ck1_tim", RCC_APB1ENSETR, 8),
  1501. STM32_TIM(TIM1_K, "tim1_k", "ck2_tim", RCC_APB2ENSETR, 0),
  1502. STM32_TIM(TIM8_K, "tim8_k", "ck2_tim", RCC_APB2ENSETR, 1),
  1503. STM32_TIM(TIM15_K, "tim15_k", "ck2_tim", RCC_APB2ENSETR, 2),
  1504. STM32_TIM(TIM16_K, "tim16_k", "ck2_tim", RCC_APB2ENSETR, 3),
  1505. STM32_TIM(TIM17_K, "tim17_k", "ck2_tim", RCC_APB2ENSETR, 4),
  1506. /* Peripheral clocks */
  1507. PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
  1508. PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
  1509. PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
  1510. PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
  1511. PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
  1512. PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
  1513. PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
  1514. PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
  1515. PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
  1516. PCLK(LPTIM1, "lptim1", "pclk1", 0, G_LPTIM1),
  1517. PCLK(SPI2, "spi2", "pclk1", 0, G_SPI2),
  1518. PCLK(SPI3, "spi3", "pclk1", 0, G_SPI3),
  1519. PCLK(USART2, "usart2", "pclk1", 0, G_USART2),
  1520. PCLK(USART3, "usart3", "pclk1", 0, G_USART3),
  1521. PCLK(UART4, "uart4", "pclk1", 0, G_UART4),
  1522. PCLK(UART5, "uart5", "pclk1", 0, G_UART5),
  1523. PCLK(UART7, "uart7", "pclk1", 0, G_UART7),
  1524. PCLK(UART8, "uart8", "pclk1", 0, G_UART8),
  1525. PCLK(I2C1, "i2c1", "pclk1", 0, G_I2C1),
  1526. PCLK(I2C2, "i2c2", "pclk1", 0, G_I2C2),
  1527. PCLK(I2C3, "i2c3", "pclk1", 0, G_I2C3),
  1528. PCLK(I2C5, "i2c5", "pclk1", 0, G_I2C5),
  1529. PCLK(SPDIF, "spdif", "pclk1", 0, G_SPDIF),
  1530. PCLK(CEC, "cec", "pclk1", 0, G_CEC),
  1531. PCLK(DAC12, "dac12", "pclk1", 0, G_DAC12),
  1532. PCLK(MDIO, "mdio", "pclk1", 0, G_MDIO),
  1533. PCLK(TIM1, "tim1", "pclk2", CLK_IGNORE_UNUSED, G_TIM1),
  1534. PCLK(TIM8, "tim8", "pclk2", CLK_IGNORE_UNUSED, G_TIM8),
  1535. PCLK(TIM15, "tim15", "pclk2", CLK_IGNORE_UNUSED, G_TIM15),
  1536. PCLK(TIM16, "tim16", "pclk2", CLK_IGNORE_UNUSED, G_TIM16),
  1537. PCLK(TIM17, "tim17", "pclk2", CLK_IGNORE_UNUSED, G_TIM17),
  1538. PCLK(SPI1, "spi1", "pclk2", 0, G_SPI1),
  1539. PCLK(SPI4, "spi4", "pclk2", 0, G_SPI4),
  1540. PCLK(SPI5, "spi5", "pclk2", 0, G_SPI5),
  1541. PCLK(USART6, "usart6", "pclk2", 0, G_USART6),
  1542. PCLK(SAI1, "sai1", "pclk2", 0, G_SAI1),
  1543. PCLK(SAI2, "sai2", "pclk2", 0, G_SAI2),
  1544. PCLK(SAI3, "sai3", "pclk2", 0, G_SAI3),
  1545. PCLK(DFSDM, "dfsdm", "pclk2", 0, G_DFSDM),
  1546. PCLK(FDCAN, "fdcan", "pclk2", 0, G_FDCAN),
  1547. PCLK(LPTIM2, "lptim2", "pclk3", 0, G_LPTIM2),
  1548. PCLK(LPTIM3, "lptim3", "pclk3", 0, G_LPTIM3),
  1549. PCLK(LPTIM4, "lptim4", "pclk3", 0, G_LPTIM4),
  1550. PCLK(LPTIM5, "lptim5", "pclk3", 0, G_LPTIM5),
  1551. PCLK(SAI4, "sai4", "pclk3", 0, G_SAI4),
  1552. PCLK(SYSCFG, "syscfg", "pclk3", 0, G_SYSCFG),
  1553. PCLK(VREF, "vref", "pclk3", 13, G_VREF),
  1554. PCLK(TMPSENS, "tmpsens", "pclk3", 0, G_TMPSENS),
  1555. PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, G_PMBCTRL),
  1556. PCLK(HDP, "hdp", "pclk3", 0, G_HDP),
  1557. PCLK(LTDC, "ltdc", "pclk4", 0, G_LTDC),
  1558. PCLK(DSI, "dsi", "pclk4", 0, G_DSI),
  1559. PCLK(IWDG2, "iwdg2", "pclk4", 0, G_IWDG2),
  1560. PCLK(USBPHY, "usbphy", "pclk4", 0, G_USBPHY),
  1561. PCLK(STGENRO, "stgenro", "pclk4", 0, G_STGENRO),
  1562. PCLK(SPI6, "spi6", "pclk5", 0, G_SPI6),
  1563. PCLK(I2C4, "i2c4", "pclk5", 0, G_I2C4),
  1564. PCLK(I2C6, "i2c6", "pclk5", 0, G_I2C6),
  1565. PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
  1566. PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
  1567. CLK_IS_CRITICAL, G_RTCAPB),
  1568. PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
  1569. PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
  1570. PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
  1571. PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
  1572. PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
  1573. PCLK(STGEN, "stgen", "pclk5", CLK_IGNORE_UNUSED, G_STGEN),
  1574. PCLK(DMA1, "dma1", "ck_mcu", 0, G_DMA1),
  1575. PCLK(DMA2, "dma2", "ck_mcu", 0, G_DMA2),
  1576. PCLK(DMAMUX, "dmamux", "ck_mcu", 0, G_DMAMUX),
  1577. PCLK(ADC12, "adc12", "ck_mcu", 0, G_ADC12),
  1578. PCLK(USBO, "usbo", "ck_mcu", 0, G_USBO),
  1579. PCLK(SDMMC3, "sdmmc3", "ck_mcu", 0, G_SDMMC3),
  1580. PCLK(DCMI, "dcmi", "ck_mcu", 0, G_DCMI),
  1581. PCLK(CRYP2, "cryp2", "ck_mcu", 0, G_CRYP2),
  1582. PCLK(HASH2, "hash2", "ck_mcu", 0, G_HASH2),
  1583. PCLK(RNG2, "rng2", "ck_mcu", 0, G_RNG2),
  1584. PCLK(CRC2, "crc2", "ck_mcu", 0, G_CRC2),
  1585. PCLK(HSEM, "hsem", "ck_mcu", 0, G_HSEM),
  1586. PCLK(IPCC, "ipcc", "ck_mcu", 0, G_IPCC),
  1587. PCLK(GPIOA, "gpioa", "ck_mcu", 0, G_GPIOA),
  1588. PCLK(GPIOB, "gpiob", "ck_mcu", 0, G_GPIOB),
  1589. PCLK(GPIOC, "gpioc", "ck_mcu", 0, G_GPIOC),
  1590. PCLK(GPIOD, "gpiod", "ck_mcu", 0, G_GPIOD),
  1591. PCLK(GPIOE, "gpioe", "ck_mcu", 0, G_GPIOE),
  1592. PCLK(GPIOF, "gpiof", "ck_mcu", 0, G_GPIOF),
  1593. PCLK(GPIOG, "gpiog", "ck_mcu", 0, G_GPIOG),
  1594. PCLK(GPIOH, "gpioh", "ck_mcu", 0, G_GPIOH),
  1595. PCLK(GPIOI, "gpioi", "ck_mcu", 0, G_GPIOI),
  1596. PCLK(GPIOJ, "gpioj", "ck_mcu", 0, G_GPIOJ),
  1597. PCLK(GPIOK, "gpiok", "ck_mcu", 0, G_GPIOK),
  1598. PCLK(GPIOZ, "gpioz", "ck_axi", CLK_IGNORE_UNUSED, G_GPIOZ),
  1599. PCLK(CRYP1, "cryp1", "ck_axi", CLK_IGNORE_UNUSED, G_CRYP1),
  1600. PCLK(HASH1, "hash1", "ck_axi", CLK_IGNORE_UNUSED, G_HASH1),
  1601. PCLK(RNG1, "rng1", "ck_axi", 0, G_RNG1),
  1602. PCLK(BKPSRAM, "bkpsram", "ck_axi", CLK_IGNORE_UNUSED, G_BKPSRAM),
  1603. PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA),
  1604. PCLK(GPU, "gpu", "ck_axi", 0, G_GPU),
  1605. PCLK(ETHTX, "ethtx", "ck_axi", 0, G_ETHTX),
  1606. PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX),
  1607. PCLK(ETHMAC, "ethmac", "ck_axi", 0, G_ETHMAC),
  1608. PCLK(FMC, "fmc", "ck_axi", CLK_IGNORE_UNUSED, G_FMC),
  1609. PCLK(QSPI, "qspi", "ck_axi", CLK_IGNORE_UNUSED, G_QSPI),
  1610. PCLK(SDMMC1, "sdmmc1", "ck_axi", 0, G_SDMMC1),
  1611. PCLK(SDMMC2, "sdmmc2", "ck_axi", 0, G_SDMMC2),
  1612. PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
  1613. PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
  1614. PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
  1615. PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, G_DDRPERFM),
  1616. /* Kernel clocks */
  1617. KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
  1618. KCLK(SDMMC2_K, "sdmmc2_k", sdmmc12_src, 0, G_SDMMC2, M_SDMMC12),
  1619. KCLK(SDMMC3_K, "sdmmc3_k", sdmmc3_src, 0, G_SDMMC3, M_SDMMC3),
  1620. KCLK(FMC_K, "fmc_k", fmc_src, 0, G_FMC, M_FMC),
  1621. KCLK(QSPI_K, "qspi_k", qspi_src, 0, G_QSPI, M_QSPI),
  1622. KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
  1623. KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
  1624. KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
  1625. KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
  1626. KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
  1627. KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
  1628. KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
  1629. KCLK(SPI3_K, "spi3_k", spi123_src, 0, G_SPI3, M_SPI23),
  1630. KCLK(SPI4_K, "spi4_k", spi45_src, 0, G_SPI4, M_SPI45),
  1631. KCLK(SPI5_K, "spi5_k", spi45_src, 0, G_SPI5, M_SPI45),
  1632. KCLK(SPI6_K, "spi6_k", spi6_src, 0, G_SPI6, M_SPI6),
  1633. KCLK(CEC_K, "cec_k", cec_src, 0, G_CEC, M_CEC),
  1634. KCLK(I2C1_K, "i2c1_k", i2c12_src, 0, G_I2C1, M_I2C12),
  1635. KCLK(I2C2_K, "i2c2_k", i2c12_src, 0, G_I2C2, M_I2C12),
  1636. KCLK(I2C3_K, "i2c3_k", i2c35_src, 0, G_I2C3, M_I2C35),
  1637. KCLK(I2C5_K, "i2c5_k", i2c35_src, 0, G_I2C5, M_I2C35),
  1638. KCLK(I2C4_K, "i2c4_k", i2c46_src, 0, G_I2C4, M_I2C46),
  1639. KCLK(I2C6_K, "i2c6_k", i2c46_src, 0, G_I2C6, M_I2C46),
  1640. KCLK(LPTIM1_K, "lptim1_k", lptim1_src, 0, G_LPTIM1, M_LPTIM1),
  1641. KCLK(LPTIM2_K, "lptim2_k", lptim23_src, 0, G_LPTIM2, M_LPTIM23),
  1642. KCLK(LPTIM3_K, "lptim3_k", lptim23_src, 0, G_LPTIM3, M_LPTIM23),
  1643. KCLK(LPTIM4_K, "lptim4_k", lptim45_src, 0, G_LPTIM4, M_LPTIM45),
  1644. KCLK(LPTIM5_K, "lptim5_k", lptim45_src, 0, G_LPTIM5, M_LPTIM45),
  1645. KCLK(USART1_K, "usart1_k", usart1_src, 0, G_USART1, M_USART1),
  1646. KCLK(USART2_K, "usart2_k", usart234578_src, 0, G_USART2, M_UART24),
  1647. KCLK(USART3_K, "usart3_k", usart234578_src, 0, G_USART3, M_UART35),
  1648. KCLK(UART4_K, "uart4_k", usart234578_src, 0, G_UART4, M_UART24),
  1649. KCLK(UART5_K, "uart5_k", usart234578_src, 0, G_UART5, M_UART35),
  1650. KCLK(USART6_K, "uart6_k", usart6_src, 0, G_USART6, M_USART6),
  1651. KCLK(UART7_K, "uart7_k", usart234578_src, 0, G_UART7, M_UART78),
  1652. KCLK(UART8_K, "uart8_k", usart234578_src, 0, G_UART8, M_UART78),
  1653. KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
  1654. KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
  1655. KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
  1656. KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
  1657. KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
  1658. KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
  1659. KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
  1660. KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
  1661. KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO),
  1662. KCLK(ETHCK_K, "ethck_k", eth_src, 0, G_ETHCK, M_ETHCK),
  1663. /* Particulary Kernel Clocks (no mux or no gate) */
  1664. MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM),
  1665. MGATE_MP1(DSI_PX, "dsi_px", "pll4_q", CLK_SET_RATE_PARENT, G_DSI),
  1666. MGATE_MP1(LTDC_PX, "ltdc_px", "pll4_q", CLK_SET_RATE_PARENT, G_LTDC),
  1667. MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
  1668. MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
  1669. COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |
  1670. CLK_SET_RATE_NO_REPARENT,
  1671. _NO_GATE,
  1672. _MMUX(M_ETHCK),
  1673. _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
  1674. /* RTC clock */
  1675. DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
  1676. COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
  1677. CLK_SET_RATE_PARENT,
  1678. _GATE(RCC_BDCR, 20, 0),
  1679. _MUX(RCC_BDCR, 16, 2, 0),
  1680. _NO_DIV),
  1681. /* MCO clocks */
  1682. COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
  1683. CLK_SET_RATE_NO_REPARENT,
  1684. _GATE(RCC_MCO1CFGR, 12, 0),
  1685. _MUX(RCC_MCO1CFGR, 0, 3, 0),
  1686. _DIV(RCC_MCO1CFGR, 4, 4, 0, NULL)),
  1687. COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE |
  1688. CLK_SET_RATE_NO_REPARENT,
  1689. _GATE(RCC_MCO2CFGR, 12, 0),
  1690. _MUX(RCC_MCO2CFGR, 0, 3, 0),
  1691. _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
  1692. /* Debug clocks */
  1693. GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
  1694. RCC_DBGCFGR, 8, 0),
  1695. COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
  1696. _GATE(RCC_DBGCFGR, 9, 0),
  1697. _NO_MUX,
  1698. _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
  1699. };
  1700. struct stm32_clock_match_data {
  1701. const struct clock_config *cfg;
  1702. unsigned int num;
  1703. unsigned int maxbinding;
  1704. };
  1705. static struct stm32_clock_match_data stm32mp1_data = {
  1706. .cfg = stm32mp1_clock_cfg,
  1707. .num = ARRAY_SIZE(stm32mp1_clock_cfg),
  1708. .maxbinding = STM32MP1_LAST_CLK,
  1709. };
  1710. static const struct of_device_id stm32mp1_match_data[] = {
  1711. {
  1712. .compatible = "st,stm32mp1-rcc",
  1713. .data = &stm32mp1_data,
  1714. },
  1715. { }
  1716. };
  1717. static int stm32_register_hw_clk(struct device *dev,
  1718. struct clk_hw_onecell_data *clk_data,
  1719. void __iomem *base, spinlock_t *lock,
  1720. const struct clock_config *cfg)
  1721. {
  1722. struct clk_hw **hws;
  1723. struct clk_hw *hw = ERR_PTR(-ENOENT);
  1724. hws = clk_data->hws;
  1725. if (cfg->func)
  1726. hw = (*cfg->func)(dev, clk_data, base, lock, cfg);
  1727. if (IS_ERR(hw)) {
  1728. pr_err("Unable to register %s\n", cfg->name);
  1729. return PTR_ERR(hw);
  1730. }
  1731. if (cfg->id != NO_ID)
  1732. hws[cfg->id] = hw;
  1733. return 0;
  1734. }
  1735. static int stm32_rcc_init(struct device_node *np,
  1736. void __iomem *base,
  1737. const struct of_device_id *match_data)
  1738. {
  1739. struct clk_hw_onecell_data *clk_data;
  1740. struct clk_hw **hws;
  1741. const struct of_device_id *match;
  1742. const struct stm32_clock_match_data *data;
  1743. int err, n, max_binding;
  1744. match = of_match_node(match_data, np);
  1745. if (!match) {
  1746. pr_err("%s: match data not found\n", __func__);
  1747. return -ENODEV;
  1748. }
  1749. data = match->data;
  1750. max_binding = data->maxbinding;
  1751. clk_data = kzalloc(struct_size(clk_data, hws, max_binding),
  1752. GFP_KERNEL);
  1753. if (!clk_data)
  1754. return -ENOMEM;
  1755. clk_data->num = max_binding;
  1756. hws = clk_data->hws;
  1757. for (n = 0; n < max_binding; n++)
  1758. hws[n] = ERR_PTR(-ENOENT);
  1759. for (n = 0; n < data->num; n++) {
  1760. err = stm32_register_hw_clk(NULL, clk_data, base, &rlock,
  1761. &data->cfg[n]);
  1762. if (err) {
  1763. pr_err("%s: can't register %s\n", __func__,
  1764. data->cfg[n].name);
  1765. kfree(clk_data);
  1766. return err;
  1767. }
  1768. }
  1769. return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
  1770. }
  1771. static void stm32mp1_rcc_init(struct device_node *np)
  1772. {
  1773. void __iomem *base;
  1774. base = of_iomap(np, 0);
  1775. if (!base) {
  1776. pr_err("%pOFn: unable to map resource", np);
  1777. of_node_put(np);
  1778. return;
  1779. }
  1780. if (stm32_rcc_init(np, base, stm32mp1_match_data)) {
  1781. iounmap(base);
  1782. of_node_put(np);
  1783. }
  1784. }
  1785. CLK_OF_DECLARE_DRIVER(stm32mp1_rcc, "st,stm32mp1-rcc", stm32mp1_rcc_init);